ARM: tegra: power: Disable CL-DVFS clock on LP1 entry
authorAlex Frid <afrid@nvidia.com>
Sun, 16 Jun 2013 02:11:15 +0000 (19:11 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Tue, 17 Sep 2013 00:41:27 +0000 (17:41 -0700)
commit70e4e08132d8cde78f270b7c47c9c682d5e2cb39
tree0a3db044e7315ff7d7c3fe9dea3b76d2a3da1287
parentc815d2cf6d6c91fc063a2c23dc62b17c07c312a3
ARM: tegra: power: Disable CL-DVFS clock on LP1 entry

Disabled CL-DVFS logic clock on LP1 entry, and re-enabled it during
resume. If running DFLL is in open loop in LP1, and there is no need
to clock closed loop logic.

Change-Id: I097aa431d99cd24d1dd6a409ad37faecf8f579dd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239134
(cherry picked from commit 8b56a79525817fab6e4bc7a6d905f6544d791116)
Reviewed-on: http://git-master/r/240863
(cherry picked from commit adbe3ecbb0d81a8a5eaf548dc209cabdd2f58a51)
Reviewed-on: http://git-master/r/271888
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
arch/arm/mach-tegra/sleep-t30.S