ARM: tegra12: clock: Fix LP0 resume hangup at PLL
authorKaz Fukuoka <kfukuoka@nvidia.com>
Thu, 11 Jul 2013 22:26:45 +0000 (15:26 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:33:10 +0000 (13:33 -0700)
commit6cbe872f6769ab25d16688bae8f3b367091767f5
treea74ee54367a72f8b037f32693f03fe9b803e08a3
parentdf2129d497a03e8e1a42dd8e60df6e10b4d3df7e
ARM: tegra12: clock: Fix LP0 resume hangup at PLL

LP0 resume hanged up where PLL functions tried to print error
message when UART clock is still turned off. Fixed as follows.

- Initialize PLLC4, PLLD2, PLLDP with valid frequencies.
- Remove debug print in clk_set in those PLLs.

bug 1322653

Change-Id: I24bbb5261b00f8fa52638c19835d2e94b9c20b05
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/248062
(cherry picked from commit 5a832c6dfc870e0a6c5d099c34441b561e765361)
Reviewed-on: http://git-master/r/252090
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
arch/arm/mach-tegra/tegra12_clocks.c