ARM: tegra: clock: Lock DFLL 1st during cluster switch
authorAlex Frid <afrid@nvidia.com>
Tue, 15 Oct 2013 03:09:39 +0000 (20:09 -0700)
committerYu-Huan Hsu <yhsu@nvidia.com>
Mon, 21 Oct 2013 22:51:21 +0000 (15:51 -0700)
commit64c241076cc41da8d16f1b43a8a9b5d109dbce90
tree2d5ff6830bce9aa57f78c93ab0cff57858a1ae7d
parentcf664738b874376f99609f0c42e9f3fad07a4e15
ARM: tegra: clock: Lock DFLL 1st during cluster switch

During LP=>G CPU cluster switch lock DFLL in closed loop mode first,
and then disable LP CPU clock. This order change allowed to reduce
delay for G CPU to reach its target frequency.

Change-Id: If47779e2172cec8ccf9d66d74bbc2b219f7ddda2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/299683
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
arch/arm/mach-tegra/tegra11_clocks.c
arch/arm/mach-tegra/tegra12_clocks.c
arch/arm/mach-tegra/tegra14_clocks.c