ARM: tegra11: clock: Update XUSB plls configuration
authorAlex Frid <afrid@nvidia.com>
Thu, 10 Jan 2013 03:34:53 +0000 (19:34 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:56:42 +0000 (12:56 -0700)
commit3f15538bf2b21a4ee7999da71f8e4b58740cacff
treedc346ce4e211e384fffdfecdfd074e1c376eae20
parent4c1500c276a80c961b7059649692c1b967016627
ARM: tegra11: clock: Update XUSB plls configuration

- set PLLE spread spectrum coefficients
- added possible PLLE configuration with 12MHz input clock
- increased PLLREFE maximum rate to 672MHz

Bug 1167739

Change-Id: I435f4afc9f96d2338bb10dc2c7fca89c392aabe2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/190182
(cherry picked from commit 32c07f3ff04859034d8633a2c87f8eb207bc9ca9)
Reviewed-on: http://git-master/r/196805
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
arch/arm/mach-tegra/tegra11_clocks.c