ARM: tegra11: clock: Combine DFLL usage controls
authorAlex Frid <afrid@nvidia.com>
Wed, 24 Oct 2012 02:50:05 +0000 (19:50 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:40:12 +0000 (12:40 -0700)
commit309f826766ff45189696638c1edd17d7ce8e88ef
tree843b3d0c95f3fae34f023fe6bb9a98c6603bbe9c
parentd7795a4343bc819d038eba9ba48b68dab66533bc
ARM: tegra11: clock: Combine DFLL usage controls

Replaced 2 boolean DFLL usage controls: use_dfll and use_pll_cpu_low
with one integer use_dfll parameter. Integrated this common control
into dfll.data structure as the following enumeration:

0 = DFLL_RANGE_NONE - DFLL is not used as CPU clock source

1 = DFLL_RANGE_ALL_RATES - DFLL is used as CPU clock source at all
rates

2 = DFLL_RANGE_HIGH_RATES - DFLL is used as CPU clock source at high
rates above use_dfll_rate_min, CPU source is automatically switched
from DFLL to PLL when use_dfll_rate_min threshold is crossed down,
and from PLL to DFLL when it is crossed upwards. In the latter case
do not clip target rate to pll mode maximum even though the switch
starts while CPU is on PLL.

Change-Id: Ide963e614d9b67f30872ec040f78d7dfab6d485a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147351
(cherry picked from commit 78733e5984ac08ed3667414dd3a770eb4f306a67)
Reviewed-on: http://git-master/r/159412
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R562147ded1e746829377c65e5457587947a8baff
arch/arm/mach-tegra/dvfs.c
arch/arm/mach-tegra/dvfs.h
arch/arm/mach-tegra/tegra11_clocks.c