ARM: tegra14: CPU DVFS tables update
authorSeshendra Gadagottu <sgadagottu@nvidia.com>
Mon, 25 Mar 2013 21:06:13 +0000 (14:06 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:07:11 +0000 (13:07 -0700)
commit21f7ee9e9e9cc8ca083b2195f7b57fc8df260c6b
treec97054c4b1d7aa8369e440ee6b617836a44718a6
parent238df9b2ea5c81ca67ae406bc80a8d2c7a727bc1
ARM: tegra14: CPU DVFS tables update

Updated CPU DVFS tables with new silicon validation data.
Cpu process id's are updated based on cpu speedo value and
separate table is defined for each cpu process id.

Increased maximum CPU clock speed to 2.1 GHz based on new
silicon validation data.

Change-Id: Iab73020fcacded5db9d9f02605e625d1a0f3a169
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/212779
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arch/arm/mach-tegra/tegra14_clocks.c
arch/arm/mach-tegra/tegra14_dvfs.c
arch/arm/mach-tegra/tegra14_speedo.c