clock: tegra21: Update PLLC4 usage policy
authorAlex Frid <afrid@nvidia.com>
Sat, 12 Jul 2014 01:37:45 +0000 (18:37 -0700)
committerYu-Huan Hsu <yhsu@nvidia.com>
Fri, 18 Jul 2014 19:00:41 +0000 (12:00 -0700)
commit1789813d22d9e196343170af71e56c724b231d03
treec7fc85b3a2580544cbad47b4da00494f0b0d9a57
parenta6f1f3acc1d459967478c96fa013bc12ed7a1982
clock: tegra21: Update PLLC4 usage policy

- Set maximum PLLC4_OUT0 frequency in PLLC4 default configuration to
provide better scaling granularity for downstream clients
- Set PLLC4_OUT0 as high pll source for SCLK (instead of PLLC4_OUT1),
and host1x (instead of PLLC). Increased maximum clock limit for SCLK
mux to allow high PLLC4 rate.
- Added PLLC4_OUT0 to DVFS table

Bug 1413190

Change-Id: I38cf4c04d18f5b0814417a24509c16b7fedbefda
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437818
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
drivers/platform/tegra/tegra21_clocks.c
drivers/platform/tegra/tegra21_dvfs.c