clock: tegra21: Update XUSB HS clock mux control
authorAlex Frid <afrid@nvidia.com>
Tue, 29 Jul 2014 06:53:30 +0000 (23:53 -0700)
committerYu-Huan Hsu <yhsu@nvidia.com>
Thu, 31 Jul 2014 20:00:42 +0000 (13:00 -0700)
commit08ddc507faffc5b80ddf0fc2977dc4fffb89adfd
tree98e7fc2e0c9d284af6883957491832bee062a506
parente808c4cb0e66deaf2a3b75c3efe5e1ba3a0c5f08
clock: tegra21: Update XUSB HS clock mux control

- Expanded HS clock parent selection mux with XUSB SS source (in
  addition to XUSB SS divided-by-2 clock and PLLU 60MHz branch).
- Increased maximum HS clock rate accordingly.
- Added PERIPH_NO_RESET flag to mux clock object, since there is no reset
  associated with mux control).
- Removed dead HS mux initialization code.

Bug 1413190

Change-Id: I459a94a676ae04ada224ef3a84981932df2026ec
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/448634
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
drivers/platform/tegra/tegra21_clocks.c
drivers/platform/tegra/tegra21_dvfs.c