gpu:nvgpu:fix powergate disabling order
authorVijayakumar <vsubbu@nvidia.com>
Fri, 27 Jun 2014 09:20:31 +0000 (14:20 +0530)
committerEmad Mir <emir@nvidia.com>
Mon, 30 Jun 2014 18:16:48 +0000 (11:16 -0700)
commit07830a2f0c60122f475ff22514146185ba7a05f3
tree2ca46b8a871b0299ee207b2bdca476428a068495
parent1d4720a1840ed9f73bafb31447535b4bd3bd2b8d
gpu:nvgpu:fix powergate disabling order

ELPG has to disabled before we write to clock gating registers
If ELPG is engaged during clock gating register write it will
cause error in ELPG engine

Bug 200013495
Bug 200014542

Change-Id: I57d1c59fc9311686829d898faddc90149df4cb46
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/432127
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c