Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-3.10.git] / drivers / net / tg3.h
index 5e96706..829a84a 100644 (file)
 
 #define TG3_RX_INTERNAL_RING_SZ_5906   32
 
-#define RX_STD_MAX_SIZE_5705           512
-#define RX_STD_MAX_SIZE_5717           2048
-#define RX_JUMBO_MAX_SIZE              0xdeadbeef /* XXX */
+#define TG3_RX_STD_MAX_SIZE_5700       512
+#define TG3_RX_STD_MAX_SIZE_5717       2048
+#define TG3_RX_JMB_MAX_SIZE_5700       256
+#define TG3_RX_JMB_MAX_SIZE_5717       1024
+#define TG3_RX_RET_MAX_SIZE_5700       1024
+#define TG3_RX_RET_MAX_SIZE_5705       512
+#define TG3_RX_RET_MAX_SIZE_5717       4096
 
 /* First 256 bytes are a mirror of PCI config space. */
 #define TG3PCI_VENDOR                  0x00000000
@@ -54,6 +58,7 @@
 #define  TG3PCI_DEVICE_TIGON3_57791     0x16b2
 #define  TG3PCI_DEVICE_TIGON3_57795     0x16b6
 #define  TG3PCI_DEVICE_TIGON3_5719      0x1657
+#define  TG3PCI_DEVICE_TIGON3_5720      0x165f
 /* 0x04 --> 0x2c unused */
 #define TG3PCI_SUBVENDOR_ID_BROADCOM           PCI_VENDOR_ID_BROADCOM
 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6   0x1644
 #define   ASIC_REV_5717                         0x5717
 #define   ASIC_REV_57765                0x57785
 #define   ASIC_REV_5719                         0x5719
+#define   ASIC_REV_5720                         0x5720
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
 #define  TX_MODE_BIG_BCKOFF_ENABLE      0x00000020
 #define  TX_MODE_LONG_PAUSE_ENABLE      0x00000040
 #define  TX_MODE_MBUF_LOCKUP_FIX        0x00000100
+#define  TX_MODE_JMB_FRM_LEN            0x00400000
+#define  TX_MODE_CNT_DN_MODE            0x00800000
 #define MAC_TX_STATUS                  0x00000460
 #define  TX_STATUS_XOFFED               0x00000001
 #define  TX_STATUS_SENT_XOFF            0x00000002
 #define  TX_LENGTHS_IPG_SHIFT           8
 #define  TX_LENGTHS_IPG_CRS_MASK        0x00003000
 #define  TX_LENGTHS_IPG_CRS_SHIFT       12
+#define  TX_LENGTHS_JMB_FRM_LEN_MSK     0x00ff0000
+#define  TX_LENGTHS_CNT_DWN_VAL_MSK     0xff000000
 #define MAC_RX_MODE                    0x00000468
 #define  RX_MODE_RESET                  0x00000001
 #define  RX_MODE_ENABLE                         0x00000002
 #define  CPMU_HST_ACC_MACCLK_6_25       0x00130000
 /* 0x3620 --> 0x3630 unused */
 
+#define TG3_CPMU_CLCK_ORIDE            0x00003624
+#define  CPMU_CLCK_ORIDE_MAC_ORIDE_EN   0x80000000
+
 #define TG3_CPMU_CLCK_STAT             0x00003630
 #define  CPMU_CLCK_STAT_MAC_CLCK_MASK   0x001f0000
 #define  CPMU_CLCK_STAT_MAC_CLCK_62_5   0x00000000
 #define  RDMAC_MODE_MULT_DMA_RD_DIS     0x01000000
 #define  RDMAC_MODE_IPV4_LSO_EN                 0x08000000
 #define  RDMAC_MODE_IPV6_LSO_EN                 0x10000000
+#define  RDMAC_MODE_H2BNC_VLAN_DET      0x20000000
 #define RDMAC_STATUS                   0x00004804
 #define  RDMAC_STATUS_TGTABORT          0x00000004
 #define  RDMAC_STATUS_MSTABORT          0x00000008
 #define  GRC_MODE_WSWAP_NONFRM_DATA    0x00000004
 #define  GRC_MODE_BSWAP_DATA           0x00000010
 #define  GRC_MODE_WSWAP_DATA           0x00000020
+#define  GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
+#define  GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080
 #define  GRC_MODE_SPLITHDR             0x00000100
 #define  GRC_MODE_NOFRM_CRACKING       0x00000200
 #define  GRC_MODE_INCL_CRC             0x00000400
 #define  GRC_MODE_NOIRQ_ON_SENDS       0x00002000
 #define  GRC_MODE_NOIRQ_ON_RCV         0x00004000
 #define  GRC_MODE_FORCE_PCI32BIT       0x00008000
+#define  GRC_MODE_B2HRX_ENABLE         0x00008000
 #define  GRC_MODE_HOST_STACKUP         0x00010000
 #define  GRC_MODE_HOST_SENDBDS         0x00020000
+#define  GRC_MODE_HTX2B_ENABLE         0x00040000
 #define  GRC_MODE_NO_TX_PHDR_CSUM      0x00100000
 #define  GRC_MODE_NVRAM_WR_ENABLE      0x00200000
 #define  GRC_MODE_PCIE_TL_SEL          0x00000000
 #define  FLASH_5717VENDOR_ATMEL_45USPT  0x03400000
 #define  FLASH_5717VENDOR_ST_25USPT     0x03400002
 #define  FLASH_5717VENDOR_ST_45USPT     0x03400001
+#define  FLASH_5720_EEPROM_HD           0x00000001
+#define  FLASH_5720_EEPROM_LD           0x00000003
+#define  FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
+#define  FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
+#define  FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
+#define  FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
+#define  FLASH_5720VENDOR_M_ST_M25PE10  0x02000000
+#define  FLASH_5720VENDOR_M_ST_M25PE20  0x02000002
+#define  FLASH_5720VENDOR_M_ST_M25PE40  0x02000001
+#define  FLASH_5720VENDOR_M_ST_M25PE80  0x02000003
+#define  FLASH_5720VENDOR_M_ST_M45PE10  0x03000000
+#define  FLASH_5720VENDOR_M_ST_M45PE20  0x03000002
+#define  FLASH_5720VENDOR_M_ST_M45PE40  0x03000001
+#define  FLASH_5720VENDOR_M_ST_M45PE80  0x03000003
+#define  FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
+#define  FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
+#define  FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
+#define  FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
+#define  FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
+#define  FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
+#define  FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
+#define  FLASH_5720VENDOR_A_ST_M25PE10  0x02800000
+#define  FLASH_5720VENDOR_A_ST_M25PE20  0x02800002
+#define  FLASH_5720VENDOR_A_ST_M25PE40  0x02800001
+#define  FLASH_5720VENDOR_A_ST_M25PE80  0x02800003
+#define  FLASH_5720VENDOR_A_ST_M45PE10  0x02c00000
+#define  FLASH_5720VENDOR_A_ST_M45PE20  0x02c00002
+#define  FLASH_5720VENDOR_A_ST_M45PE40  0x02c00001
+#define  FLASH_5720VENDOR_A_ST_M45PE80  0x02c00003
+#define  FLASH_5720VENDOR_ATMEL_45USPT  0x03c00000
+#define  FLASH_5720VENDOR_ST_25USPT     0x03c00002
+#define  FLASH_5720VENDOR_ST_45USPT     0x03c00001
 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK  0x70000000
 #define  FLASH_5752PAGE_SIZE_256        0x00000000
 #define  FLASH_5752PAGE_SIZE_512        0x10000000
@@ -2833,7 +2883,6 @@ struct tg3 {
        u32                             tg3_flags;
 #define TG3_FLAG_TAGGED_STATUS         0x00000001
 #define TG3_FLAG_TXD_MBOX_HWBUG                0x00000002
-#define TG3_FLAG_RX_CHECKSUMS          0x00000004
 #define TG3_FLAG_USE_LINKCHG_REG       0x00000008
 #define TG3_FLAG_ENABLE_ASF            0x00000020
 #define TG3_FLAG_ASPM_WORKAROUND       0x00000040
@@ -2859,7 +2908,6 @@ struct tg3 {
 #define TG3_FLAG_PAUSE_AUTONEG         0x02000000
 #define TG3_FLAG_CPMU_PRESENT          0x04000000
 #define TG3_FLAG_40BIT_DMA_BUG         0x08000000
-#define TG3_FLAG_BROKEN_CHECKSUMS      0x10000000
 #define TG3_FLAG_JUMBO_CAPABLE         0x20000000
 #define TG3_FLAG_CHIP_RESETTING                0x40000000
 #define TG3_FLAG_INIT_COMPLETE         0x80000000
@@ -2897,6 +2945,7 @@ struct tg3 {
 #define TG3_FLG3_5701_DMA_BUG          0x00000008
 #define TG3_FLG3_USE_PHYLIB            0x00000010
 #define TG3_FLG3_MDIOBUS_INITED                0x00000020
+#define TG3_FLG3_LRG_PROD_RING_CAP     0x00000080
 #define TG3_FLG3_RGMII_INBAND_DISABLE  0x00000100
 #define TG3_FLG3_RGMII_EXT_IBND_RX_EN  0x00000200
 #define TG3_FLG3_RGMII_EXT_IBND_TX_EN  0x00000400
@@ -2910,8 +2959,9 @@ struct tg3 {
 #define TG3_FLG3_SHORT_DMA_BUG         0x00200000
 #define TG3_FLG3_USE_JUMBO_BDFLAG      0x00400000
 #define TG3_FLG3_L1PLLPD_EN            0x00800000
-#define TG3_FLG3_5717_PLUS             0x01000000
+#define TG3_FLG3_57765_PLUS            0x01000000
 #define TG3_FLG3_APE_HAS_NCSI          0x02000000
+#define TG3_FLG3_5717_PLUS             0x04000000
 
        struct timer_list               timer;
        u16                             timer_counter;
@@ -2983,6 +3033,7 @@ struct tg3 {
 #define TG3_PHY_ID_BCM5718S            0xbc050ff0
 #define TG3_PHY_ID_BCM57765            0x5c0d8a40
 #define TG3_PHY_ID_BCM5719C            0x5c0d8a20
+#define TG3_PHY_ID_BCM5720C            0x5c0d8b60
 #define TG3_PHY_ID_BCM5906             0xdc00ac40
 #define TG3_PHY_ID_BCM8002             0x60010140
 #define TG3_PHY_ID_INVALID             0xffffffff
@@ -3049,6 +3100,7 @@ struct tg3 {
 
        int                             nvram_lock_cnt;
        u32                             nvram_size;
+#define TG3_NVRAM_SIZE_2KB             0x00000800
 #define TG3_NVRAM_SIZE_64KB            0x00010000
 #define TG3_NVRAM_SIZE_128KB           0x00020000
 #define TG3_NVRAM_SIZE_256KB           0x00040000
@@ -3064,6 +3116,9 @@ struct tg3 {
 #define JEDEC_SAIFUN                   0x4f
 #define JEDEC_SST                      0xbf
 
+#define ATMEL_AT24C02_CHIP_SIZE                TG3_NVRAM_SIZE_2KB
+#define ATMEL_AT24C02_PAGE_SIZE                (8)
+
 #define ATMEL_AT24C64_CHIP_SIZE                TG3_NVRAM_SIZE_64KB
 #define ATMEL_AT24C64_PAGE_SIZE                (32)