[TG3]: Add new 5761 NVRAM decode routines
[linux-3.10.git] / drivers / net / tg3.c
index 3a43426..3200c9c 100644 (file)
@@ -64,8 +64,8 @@
 
 #define DRV_MODULE_NAME                "tg3"
 #define PFX DRV_MODULE_NAME    ": "
-#define DRV_MODULE_VERSION     "3.77"
-#define DRV_MODULE_RELDATE     "May 31, 2007"
+#define DRV_MODULE_VERSION     "3.82"
+#define DRV_MODULE_RELDATE     "October 5, 2007"
 
 #define TG3_DEF_MAC_MODE       0
 #define TG3_DEF_RX_MODE                0
@@ -198,6 +198,8 @@ static struct pci_device_id tg3_pci_tbl[] = {
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
        {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
        {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
        {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
@@ -574,7 +576,7 @@ static void tg3_restart_ints(struct tg3 *tp)
 static inline void tg3_netif_stop(struct tg3 *tp)
 {
        tp->dev->trans_start = jiffies; /* prevent tx timeout */
-       netif_poll_disable(tp->dev);
+       napi_disable(&tp->napi);
        netif_tx_disable(tp->dev);
 }
 
@@ -585,7 +587,7 @@ static inline void tg3_netif_start(struct tg3 *tp)
         * so long as all callers are assured to have free tx slots
         * (such as after tg3_init_hw)
         */
-       netif_poll_enable(tp->dev);
+       napi_enable(&tp->napi);
        tp->hw_status->status |= SD_STATUS_UPDATED;
        tg3_enable_ints(tp);
 }
@@ -595,7 +597,8 @@ static void tg3_switch_clocks(struct tg3 *tp)
        u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
        u32 orig_clock_ctrl;
 
-       if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
+       if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
+           (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
                return;
 
        orig_clock_ctrl = clock_ctrl;
@@ -721,6 +724,44 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
        return ret;
 }
 
+static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
+{
+       u32 phy;
+
+       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
+           (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
+               return;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+               u32 ephy;
+
+               if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
+                       tg3_writephy(tp, MII_TG3_EPHY_TEST,
+                                    ephy | MII_TG3_EPHY_SHADOW_EN);
+                       if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
+                               if (enable)
+                                       phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
+                               else
+                                       phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
+                               tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
+                       }
+                       tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
+               }
+       } else {
+               phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
+                     MII_TG3_AUXCTL_SHDWSEL_MISC;
+               if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
+                   !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
+                       if (enable)
+                               phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
+                       else
+                               phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
+                       phy |= MII_TG3_AUXCTL_MISC_WREN;
+                       tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
+               }
+       }
+}
+
 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 {
        u32 val;
@@ -1045,23 +1086,11 @@ out:
        }
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
-               u32 phy_reg;
-
                /* adjust output voltage */
                tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
-
-               if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
-                       u32 phy_reg2;
-
-                       tg3_writephy(tp, MII_TG3_EPHY_TEST,
-                                    phy_reg | MII_TG3_EPHY_SHADOW_EN);
-                       /* Enable auto-MDIX */
-                       if (!tg3_readphy(tp, 0x10, &phy_reg2))
-                               tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
-                       tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
-               }
        }
 
+       tg3_phy_toggle_automdix(tp, 1);
        tg3_phy_set_wirespeed(tp);
        return 0;
 }
@@ -1162,6 +1191,19 @@ static void tg3_frob_aux_power(struct tg3 *tp)
        }
 }
 
+static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
+{
+       if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
+               return 1;
+       else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
+               if (speed != SPEED_10)
+                       return 1;
+       } else if (speed == SPEED_10)
+               return 1;
+
+       return 0;
+}
+
 static int tg3_setup_phy(struct tg3 *, int);
 
 #define RESET_KIND_SHUTDOWN    0
@@ -1320,9 +1362,17 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
                        else
                                mac_mode = MAC_MODE_PORT_MODE_MII;
 
-                       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
-                           !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
-                               mac_mode |= MAC_MODE_LINK_POLARITY;
+                       mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
+                       if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
+                           ASIC_REV_5700) {
+                               u32 speed = (tp->tg3_flags &
+                                            TG3_FLAG_WOL_SPEED_100MB) ?
+                                            SPEED_100 : SPEED_10;
+                               if (tg3_5700_link_polarity(tp, speed))
+                                       mac_mode |= MAC_MODE_LINK_POLARITY;
+                               else
+                                       mac_mode &= ~MAC_MODE_LINK_POLARITY;
+                       }
                } else {
                        mac_mode = MAC_MODE_PORT_MODE_TBI;
                }
@@ -1353,6 +1403,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
                tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
                            CLOCK_CTRL_PWRDOWN_PLL133, 40);
        } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
+                  (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
                   (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
                /* do nothing */
        } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
@@ -1990,15 +2041,12 @@ relink:
        if (tp->link_config.active_duplex == DUPLEX_HALF)
                tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
 
-       tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
-               if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
-                   (current_link_up == 1 &&
-                    tp->link_config.active_speed == SPEED_10))
-                       tp->mac_mode |= MAC_MODE_LINK_POLARITY;
-       } else {
-               if (current_link_up == 1)
+               if (current_link_up == 1 &&
+                   tg3_5700_link_polarity(tp, tp->link_config.active_speed))
                        tp->mac_mode |= MAC_MODE_LINK_POLARITY;
+               else
+                       tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
        }
 
        /* ??? Without this setting Netgear GA302T PHY does not
@@ -2639,6 +2687,9 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
 
                tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
                udelay(40);
+
+               tw32_f(MAC_MODE, tp->mac_mode);
+               udelay(40);
        }
 
 out:
@@ -2698,10 +2749,6 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
        else
                current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
 
-       tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
-       tw32_f(MAC_MODE, tp->mac_mode);
-       udelay(40);
-
        tp->hw_status->status =
                (SD_STATUS_UPDATED |
                 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
@@ -3428,11 +3475,12 @@ next_pkt_nopost:
        return received;
 }
 
-static int tg3_poll(struct net_device *netdev, int *budget)
+static int tg3_poll(struct napi_struct *napi, int budget)
 {
-       struct tg3 *tp = netdev_priv(netdev);
+       struct tg3 *tp = container_of(napi, struct tg3, napi);
+       struct net_device *netdev = tp->dev;
        struct tg3_hw_status *sblk = tp->hw_status;
-       int done;
+       int work_done = 0;
 
        /* handle link change and other phy events */
        if (!(tp->tg3_flags &
@@ -3451,7 +3499,7 @@ static int tg3_poll(struct net_device *netdev, int *budget)
        if (sblk->idx[0].tx_consumer != tp->tx_cons) {
                tg3_tx(tp);
                if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
-                       netif_rx_complete(netdev);
+                       netif_rx_complete(netdev, napi);
                        schedule_work(&tp->reset_task);
                        return 0;
                }
@@ -3459,20 +3507,10 @@ static int tg3_poll(struct net_device *netdev, int *budget)
 
        /* run RX thread, within the bounds set by NAPI.
         * All RX "locking" is done by ensuring outside
-        * code synchronizes with dev->poll()
+        * code synchronizes with tg3->napi.poll()
         */
-       if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
-               int orig_budget = *budget;
-               int work_done;
-
-               if (orig_budget > netdev->quota)
-                       orig_budget = netdev->quota;
-
-               work_done = tg3_rx(tp, orig_budget);
-
-               *budget -= work_done;
-               netdev->quota -= work_done;
-       }
+       if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
+               work_done = tg3_rx(tp, budget);
 
        if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
                tp->last_tag = sblk->status_tag;
@@ -3481,13 +3519,12 @@ static int tg3_poll(struct net_device *netdev, int *budget)
                sblk->status &= ~SD_STATUS_UPDATED;
 
        /* if no more work, tell net stack and NIC we're done */
-       done = !tg3_has_work(tp);
-       if (done) {
-               netif_rx_complete(netdev);
+       if (!tg3_has_work(tp)) {
+               netif_rx_complete(netdev, napi);
                tg3_restart_ints(tp);
        }
 
-       return (done ? 0 : 1);
+       return work_done;
 }
 
 static void tg3_irq_quiesce(struct tg3 *tp)
@@ -3512,9 +3549,9 @@ static inline int tg3_irq_sync(struct tg3 *tp)
  */
 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
 {
+       spin_lock_bh(&tp->lock);
        if (irq_sync)
                tg3_irq_quiesce(tp);
-       spin_lock_bh(&tp->lock);
 }
 
 static inline void tg3_full_unlock(struct tg3 *tp)
@@ -3534,7 +3571,7 @@ static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
        prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
 
        if (likely(!tg3_irq_sync(tp)))
-               netif_rx_schedule(dev);         /* schedule NAPI poll */
+               netif_rx_schedule(dev, &tp->napi);
 
        return IRQ_HANDLED;
 }
@@ -3559,7 +3596,7 @@ static irqreturn_t tg3_msi(int irq, void *dev_id)
         */
        tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
        if (likely(!tg3_irq_sync(tp)))
-               netif_rx_schedule(dev);         /* schedule NAPI poll */
+               netif_rx_schedule(dev, &tp->napi);
 
        return IRQ_RETVAL(1);
 }
@@ -3601,7 +3638,7 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id)
        sblk->status &= ~SD_STATUS_UPDATED;
        if (likely(tg3_has_work(tp))) {
                prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
-               netif_rx_schedule(dev);         /* schedule NAPI poll */
+               netif_rx_schedule(dev, &tp->napi);
        } else {
                /* No work, shared interrupt perhaps?  re-enable
                 * interrupts, and flush that PCI write
@@ -3647,7 +3684,7 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
        tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
        if (tg3_irq_sync(tp))
                goto out;
-       if (netif_rx_schedule_prep(dev)) {
+       if (netif_rx_schedule_prep(dev, &tp->napi)) {
                prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
                /* Update last_tag to mark that this status has been
                 * seen. Because interrupt may be shared, we may be
@@ -3655,7 +3692,7 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
                 * if tg3_poll() is not scheduled.
                 */
                tp->last_tag = sblk->status_tag;
-               __netif_rx_schedule(dev);
+               __netif_rx_schedule(dev, &tp->napi);
        }
 out:
        return IRQ_RETVAL(handled);
@@ -3694,7 +3731,7 @@ static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
                tg3_full_unlock(tp);
                del_timer_sync(&tp->timer);
                tp->irq_sync = 0;
-               netif_poll_enable(tp->dev);
+               napi_enable(&tp->napi);
                dev_close(tp->dev);
                tg3_full_lock(tp, 0);
        }
@@ -3889,7 +3926,7 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
        len = skb_headlen(skb);
 
        /* We are running in BH disabled context with netif_tx_lock
-        * and TX reclaim runs via tp->poll inside of a software
+        * and TX reclaim runs via tp->napi.poll inside of a software
         * interrupt.  Furthermore, IRQ processing runs lockless so we have
         * no IRQ context deadlocks to worry about either.  Rejoice!
         */
@@ -4044,7 +4081,7 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
        len = skb_headlen(skb);
 
        /* We are running in BH disabled context with netif_tx_lock
-        * and TX reclaim runs via tp->poll inside of a software
+        * and TX reclaim runs via tp->napi.poll inside of a software
         * interrupt.  Furthermore, IRQ processing runs lockless so we have
         * no IRQ context deadlocks to worry about either.  Rejoice!
         */
@@ -4804,6 +4841,64 @@ static int tg3_poll_fw(struct tg3 *tp)
        return 0;
 }
 
+/* Save PCI command register before chip reset */
+static void tg3_save_pci_state(struct tg3 *tp)
+{
+       u32 val;
+
+       pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);
+       tp->pci_cmd = val;
+}
+
+/* Restore PCI state after chip reset */
+static void tg3_restore_pci_state(struct tg3 *tp)
+{
+       u32 val;
+
+       /* Re-enable indirect register accesses. */
+       pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
+                              tp->misc_host_ctrl);
+
+       /* Set MAX PCI retry to zero. */
+       val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
+       if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
+           (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
+               val |= PCISTATE_RETRY_SAME_DMA;
+       pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
+
+       pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
+
+       /* Make sure PCI-X relaxed ordering bit is clear. */
+       if (tp->pcix_cap) {
+               u16 pcix_cmd;
+
+               pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
+                                    &pcix_cmd);
+               pcix_cmd &= ~PCI_X_CMD_ERO;
+               pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
+                                     pcix_cmd);
+       }
+
+       if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
+
+               /* Chip reset on 5780 will reset MSI enable bit,
+                * so need to restore it.
+                */
+               if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+                       u16 ctrl;
+
+                       pci_read_config_word(tp->pdev,
+                                            tp->msi_cap + PCI_MSI_FLAGS,
+                                            &ctrl);
+                       pci_write_config_word(tp->pdev,
+                                             tp->msi_cap + PCI_MSI_FLAGS,
+                                             ctrl | PCI_MSI_FLAGS_ENABLE);
+                       val = tr32(MSGINT_MODE);
+                       tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
+               }
+       }
+}
+
 static void tg3_stop_fw(struct tg3 *);
 
 /* tp->lock is held. */
@@ -4820,9 +4915,16 @@ static int tg3_chip_reset(struct tg3 *tp)
         */
        tp->nvram_lock_cnt = 0;
 
+       /* GRC_MISC_CFG core clock reset will clear the memory
+        * enable bit in PCI register 4 and the MSI enable bit
+        * on some chips, so we save relevant registers here.
+        */
+       tg3_save_pci_state(tp);
+
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
                tw32(GRC_FASTBOOT_PC, 0);
 
        /*
@@ -4918,50 +5020,14 @@ static int tg3_chip_reset(struct tg3 *tp)
                pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
        }
 
-       /* Re-enable indirect register accesses. */
-       pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
-                              tp->misc_host_ctrl);
-
-       /* Set MAX PCI retry to zero. */
-       val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
-       if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
-           (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
-               val |= PCISTATE_RETRY_SAME_DMA;
-       pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
-
-       pci_restore_state(tp->pdev);
+       tg3_restore_pci_state(tp);
 
        tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
 
-       /* Make sure PCI-X relaxed ordering bit is clear. */
-       pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
-       val &= ~PCIX_CAPS_RELAXED_ORDERING;
-       pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
-
-       if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
-               u32 val;
-
-               /* Chip reset on 5780 will reset MSI enable bit,
-                * so need to restore it.
-                */
-               if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
-                       u16 ctrl;
-
-                       pci_read_config_word(tp->pdev,
-                                            tp->msi_cap + PCI_MSI_FLAGS,
-                                            &ctrl);
-                       pci_write_config_word(tp->pdev,
-                                             tp->msi_cap + PCI_MSI_FLAGS,
-                                             ctrl | PCI_MSI_FLAGS_ENABLE);
-                       val = tr32(MSGINT_MODE);
-                       tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
-               }
-
+       val = 0;
+       if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
                val = tr32(MEMARB_MODE);
-               tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
-
-       } else
-               tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
+       tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
 
        if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
                tg3_stop_fw(tp);
@@ -4971,7 +5037,7 @@ static int tg3_chip_reset(struct tg3 *tp)
        tw32(GRC_MODE, tp->grc_mode);
 
        if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
-               u32 val = tr32(0xc4);
+               val = tr32(0xc4);
 
                tw32(0xc4, val | (1 << 15));
        }
@@ -5000,7 +5066,7 @@ static int tg3_chip_reset(struct tg3 *tp)
 
        if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
            tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
-               u32 val = tr32(0x7c00);
+               val = tr32(0x7c00);
 
                tw32(0x7c00, val | (1 << 25));
        }
@@ -6083,14 +6149,22 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 
        tg3_write_sig_legacy(tp, RESET_KIND_INIT);
 
+       if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0) {
+               val = tr32(TG3_CPMU_CTRL);
+               val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
+               tw32(TG3_CPMU_CTRL, val);
+       }
+
        /* This works around an issue with Athlon chipsets on
         * B3 tigon3 silicon.  This bit has no effect on any
         * other revision.  But do not set this on PCI Express
-        * chips.
+        * chips and don't even touch the clocks if the CPMU is present.
         */
-       if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
-               tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
-       tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
+       if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
+               if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
+                       tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
+               tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
+       }
 
        if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
            (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
@@ -6115,10 +6189,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        if (err)
                return err;
 
-       /* This value is determined during the probe time DMA
-        * engine test, tg3_test_dma.
-        */
-       tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) {
+               /* This value is determined during the probe time DMA
+                * engine test, tg3_test_dma.
+                */
+               tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
+       }
 
        tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
                          GRC_MODE_4X_NIC_SEND_RINGS |
@@ -6352,6 +6428,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                      RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
                      RDMAC_MODE_LNGREAD_ENAB);
 
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
+               rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
+                             RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
+                             RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
+
        /* If statement applies to 5705 and 5750 PCI devices only */
        if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
@@ -6444,6 +6525,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 
        tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
                MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
+       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
+           !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
+           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
+               tp->mac_mode |= MAC_MODE_LINK_POLARITY;
        tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
        udelay(40);
 
@@ -6509,22 +6594,27 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 
        /* Enable host coalescing bug fix */
        if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
-           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
+           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
+           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
                val |= (1 << 29);
 
        tw32_f(WDMAC_MODE, val);
        udelay(40);
 
-       if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
-               val = tr32(TG3PCI_X_CAPS);
+       if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
+               u16 pcix_cmd;
+
+               pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
+                                    &pcix_cmd);
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
-                       val &= ~PCIX_CAPS_BURST_MASK;
-                       val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
+                       pcix_cmd &= ~PCI_X_CMD_MAX_READ;
+                       pcix_cmd |= PCI_X_CMD_READ_2K;
                } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
-                       val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
-                       val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
+                       pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
+                       pcix_cmd |= PCI_X_CMD_READ_2K;
                }
-               tw32(TG3PCI_X_CAPS, val);
+               pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
+                                     pcix_cmd);
        }
 
        tw32_f(RDMAC_MODE, rdmac_mode);
@@ -7057,6 +7147,10 @@ static int tg3_open(struct net_device *dev)
                } else if (pci_enable_msi(tp->pdev) == 0) {
                        u32 msi_mode;
 
+                       /* Hardware bug - MSI won't work if INTX disabled. */
+                       if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
+                               pci_intx(tp->pdev, 1);
+
                        msi_mode = tr32(MSGINT_MODE);
                        tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
                        tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
@@ -7073,6 +7167,8 @@ static int tg3_open(struct net_device *dev)
                return err;
        }
 
+       napi_enable(&tp->napi);
+
        tg3_full_lock(tp, 0);
 
        err = tg3_init_hw(tp, 1);
@@ -7100,6 +7196,7 @@ static int tg3_open(struct net_device *dev)
        tg3_full_unlock(tp);
 
        if (err) {
+               napi_disable(&tp->napi);
                free_irq(tp->pdev->irq, dev);
                if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
                        pci_disable_msi(tp->pdev);
@@ -7125,6 +7222,8 @@ static int tg3_open(struct net_device *dev)
 
                        tg3_full_unlock(tp);
 
+                       napi_disable(&tp->napi);
+
                        return err;
                }
 
@@ -7386,6 +7485,7 @@ static int tg3_close(struct net_device *dev)
 {
        struct tg3 *tp = netdev_priv(dev);
 
+       napi_disable(&tp->napi);
        cancel_work_sync(&tp->reset_task);
 
        netif_stop_queue(dev);
@@ -7921,7 +8021,7 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
        buf = data;
        if (b_offset || odd_len) {
                buf = kmalloc(len, GFP_KERNEL);
-               if (buf == 0)
+               if (!buf)
                        return -ENOMEM;
                if (b_offset)
                        memcpy(buf, &start, 4);
@@ -8001,7 +8101,8 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 
        tp->link_config.autoneg = cmd->autoneg;
        if (cmd->autoneg == AUTONEG_ENABLE) {
-               tp->link_config.advertising = cmd->advertising;
+               tp->link_config.advertising = (cmd->advertising |
+                                             ADVERTISED_Autoneg);
                tp->link_config.speed = SPEED_INVALID;
                tp->link_config.duplex = DUPLEX_INVALID;
        } else {
@@ -8270,22 +8371,25 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
        }
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
-               ethtool_op_set_tx_hw_csum(dev, data);
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
+               ethtool_op_set_tx_ipv6_csum(dev, data);
        else
                ethtool_op_set_tx_csum(dev, data);
 
        return 0;
 }
 
-static int tg3_get_stats_count (struct net_device *dev)
+static int tg3_get_sset_count (struct net_device *dev, int sset)
 {
-       return TG3_NUM_STATS;
-}
-
-static int tg3_get_test_count (struct net_device *dev)
-{
-       return TG3_NUM_TEST;
+       switch (sset) {
+       case ETH_SS_TEST:
+               return TG3_NUM_TEST;
+       case ETH_SS_STATS:
+               return TG3_NUM_STATS;
+       default:
+               return -EOPNOTSUPP;
+       }
 }
 
 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
@@ -8350,7 +8454,7 @@ static void tg3_get_ethtool_stats (struct net_device *dev,
 static int tg3_test_nvram(struct tg3 *tp)
 {
        u32 *buf, csum, magic;
-       int i, j, err = 0, size;
+       int i, j, k, err = 0, size;
 
        if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
                return -EIO;
@@ -8404,7 +8508,6 @@ static int tg3_test_nvram(struct tg3 *tp)
                u8 data[NVRAM_SELFBOOT_DATA_SIZE];
                u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
                u8 *buf8 = (u8 *) buf;
-               int j, k;
 
                /* Separate the parity bits and the data bytes.  */
                for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
@@ -8765,7 +8868,8 @@ static int tg3_test_memory(struct tg3 *tp)
 
        if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
                        mem_tbl = mem_tbl_5755;
                else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
                        mem_tbl = mem_tbl_5906;
@@ -8805,7 +8909,9 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                        return 0;
 
                mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
-                          MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
+                          MAC_MODE_PORT_INT_LPBACK;
+               if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+                       mac_mode |= MAC_MODE_LINK_POLARITY;
                if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
                        mac_mode |= MAC_MODE_PORT_MODE_MII;
                else
@@ -8824,19 +8930,18 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                                             phytest | MII_TG3_EPHY_SHADOW_EN);
                                if (!tg3_readphy(tp, 0x1b, &phy))
                                        tg3_writephy(tp, 0x1b, phy & ~0x20);
-                               if (!tg3_readphy(tp, 0x10, &phy))
-                                       tg3_writephy(tp, 0x10, phy & ~0x4000);
                                tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
                        }
                        val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
                } else
                        val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
 
+               tg3_phy_toggle_automdix(tp, 0);
+
                tg3_writephy(tp, MII_BMCR, val);
                udelay(40);
 
-               mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
-                          MAC_MODE_LINK_POLARITY;
+               mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
                        tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
                        mac_mode |= MAC_MODE_PORT_MODE_MII;
@@ -8849,8 +8954,11 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                        udelay(10);
                        tw32_f(MAC_RX_MODE, tp->rx_mode);
                }
-               if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
-                       mac_mode &= ~MAC_MODE_LINK_POLARITY;
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
+                       if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
+                               mac_mode &= ~MAC_MODE_LINK_POLARITY;
+                       else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
+                               mac_mode |= MAC_MODE_LINK_POLARITY;
                        tg3_writephy(tp, MII_TG3_EXT_CTRL,
                                     MII_TG3_EXT_CTRL_LNK3_LED_MODE);
                }
@@ -9116,10 +9224,10 @@ static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
        /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
        __tg3_set_rx_mode(dev);
 
-       tg3_full_unlock(tp);
-
        if (netif_running(dev))
                tg3_netif_start(tp);
+
+       tg3_full_unlock(tp);
 }
 #endif
 
@@ -9206,21 +9314,16 @@ static const struct ethtool_ops tg3_ethtool_ops = {
        .set_pauseparam         = tg3_set_pauseparam,
        .get_rx_csum            = tg3_get_rx_csum,
        .set_rx_csum            = tg3_set_rx_csum,
-       .get_tx_csum            = ethtool_op_get_tx_csum,
        .set_tx_csum            = tg3_set_tx_csum,
-       .get_sg                 = ethtool_op_get_sg,
        .set_sg                 = ethtool_op_set_sg,
-       .get_tso                = ethtool_op_get_tso,
        .set_tso                = tg3_set_tso,
-       .self_test_count        = tg3_get_test_count,
        .self_test              = tg3_self_test,
        .get_strings            = tg3_get_strings,
        .phys_id                = tg3_phys_id,
-       .get_stats_count        = tg3_get_stats_count,
        .get_ethtool_stats      = tg3_get_ethtool_stats,
        .get_coalesce           = tg3_get_coalesce,
        .set_coalesce           = tg3_set_coalesce,
-       .get_perm_addr          = ethtool_op_get_perm_addr,
+       .get_sset_count         = tg3_get_sset_count,
 };
 
 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
@@ -9410,11 +9513,13 @@ static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
                case FLASH_5755VENDOR_ATMEL_FLASH_1:
                case FLASH_5755VENDOR_ATMEL_FLASH_2:
                case FLASH_5755VENDOR_ATMEL_FLASH_3:
+               case FLASH_5755VENDOR_ATMEL_FLASH_5:
                        tp->nvram_jedecnum = JEDEC_ATMEL;
                        tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
                        tp->tg3_flags2 |= TG3_FLG2_FLASH;
                        tp->nvram_pagesize = 264;
-                       if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1)
+                       if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
+                           nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
                                tp->nvram_size = (protect ? 0x3e200 : 0x80000);
                        else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
                                tp->nvram_size = (protect ? 0x1f200 : 0x40000);
@@ -9476,6 +9581,81 @@ static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
        }
 }
 
+static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
+{
+       u32 nvcfg1, protect = 0;
+
+       nvcfg1 = tr32(NVRAM_CFG1);
+
+       /* NVRAM protection for TPM */
+       if (nvcfg1 & (1 << 27)) {
+               tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
+               protect = 1;
+       }
+
+       nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
+       switch (nvcfg1) {
+               case FLASH_5761VENDOR_ATMEL_ADB021D:
+               case FLASH_5761VENDOR_ATMEL_ADB041D:
+               case FLASH_5761VENDOR_ATMEL_ADB081D:
+               case FLASH_5761VENDOR_ATMEL_ADB161D:
+               case FLASH_5761VENDOR_ATMEL_MDB021D:
+               case FLASH_5761VENDOR_ATMEL_MDB041D:
+               case FLASH_5761VENDOR_ATMEL_MDB081D:
+               case FLASH_5761VENDOR_ATMEL_MDB161D:
+                       tp->nvram_jedecnum = JEDEC_ATMEL;
+                       tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                       tp->tg3_flags2 |= TG3_FLG2_FLASH;
+                       tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
+                       tp->nvram_pagesize = 256;
+                       break;
+               case FLASH_5761VENDOR_ST_A_M45PE20:
+               case FLASH_5761VENDOR_ST_A_M45PE40:
+               case FLASH_5761VENDOR_ST_A_M45PE80:
+               case FLASH_5761VENDOR_ST_A_M45PE16:
+               case FLASH_5761VENDOR_ST_M_M45PE20:
+               case FLASH_5761VENDOR_ST_M_M45PE40:
+               case FLASH_5761VENDOR_ST_M_M45PE80:
+               case FLASH_5761VENDOR_ST_M_M45PE16:
+                       tp->nvram_jedecnum = JEDEC_ST;
+                       tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                       tp->tg3_flags2 |= TG3_FLG2_FLASH;
+                       tp->nvram_pagesize = 256;
+                       break;
+       }
+
+       if (protect) {
+               tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
+       } else {
+               switch (nvcfg1) {
+                       case FLASH_5761VENDOR_ATMEL_ADB161D:
+                       case FLASH_5761VENDOR_ATMEL_MDB161D:
+                       case FLASH_5761VENDOR_ST_A_M45PE16:
+                       case FLASH_5761VENDOR_ST_M_M45PE16:
+                               tp->nvram_size = 0x100000;
+                               break;
+                       case FLASH_5761VENDOR_ATMEL_ADB081D:
+                       case FLASH_5761VENDOR_ATMEL_MDB081D:
+                       case FLASH_5761VENDOR_ST_A_M45PE80:
+                       case FLASH_5761VENDOR_ST_M_M45PE80:
+                               tp->nvram_size = 0x80000;
+                               break;
+                       case FLASH_5761VENDOR_ATMEL_ADB041D:
+                       case FLASH_5761VENDOR_ATMEL_MDB041D:
+                       case FLASH_5761VENDOR_ST_A_M45PE40:
+                       case FLASH_5761VENDOR_ST_M_M45PE40:
+                               tp->nvram_size = 0x40000;
+                               break;
+                       case FLASH_5761VENDOR_ATMEL_ADB021D:
+                       case FLASH_5761VENDOR_ATMEL_MDB021D:
+                       case FLASH_5761VENDOR_ST_A_M45PE20:
+                       case FLASH_5761VENDOR_ST_M_M45PE20:
+                               tp->nvram_size = 0x20000;
+                               break;
+               }
+       }
+}
+
 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
 {
        tp->nvram_jedecnum = JEDEC_ATMEL;
@@ -9515,8 +9695,11 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
                        tg3_get_5752_nvram_info(tp);
                else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
                        tg3_get_5755_nvram_info(tp);
-               else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
+               else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
+                        GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
                        tg3_get_5787_nvram_info(tp);
+               else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
+                       tg3_get_5761_nvram_info(tp);
                else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
                        tg3_get_5906_nvram_info(tp);
                else
@@ -9594,6 +9777,7 @@ static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
        if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
            (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
            (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
+          !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
            (tp->nvram_jedecnum == JEDEC_ATMEL))
 
                addr = ((addr / tp->nvram_pagesize) <<
@@ -9608,6 +9792,7 @@ static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
        if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
            (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
            (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
+          !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
            (tp->nvram_jedecnum == JEDEC_ATMEL))
 
                addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
@@ -9828,6 +10013,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
                if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
                    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
                    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
+                   (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
                    (tp->nvram_jedecnum == JEDEC_ST) &&
                    (nvram_cmd & NVRAM_CMD_FIRST)) {
 
@@ -10446,6 +10632,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 
        tp->pci_chip_rev_id = (misc_ctrl_reg >>
                               MISC_HOST_CTRL_CHIPREV_SHIFT);
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
+               u32 prod_id_asic_rev;
+
+               pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
+                                     &prod_id_asic_rev);
+               tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
+       }
 
        /* Wrong chip ID in 5752 A0. This code can be removed later
         * as A0 is not in production.
@@ -10498,11 +10691,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                                continue;
                        }
                        if (pci_id->rev != PCI_ANY_ID) {
-                               u8 rev;
-
-                               pci_read_config_byte(bridge, PCI_REVISION_ID,
-                                                    &rev);
-                               if (rev > pci_id->rev)
+                               if (bridge->revision > pci_id->rev)
                                        continue;
                        }
                        if (bridge->subordinate &&
@@ -10569,6 +10758,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
                tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
@@ -10588,6 +10778,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
                        tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
                        tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
@@ -10605,6 +10796,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
+           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
                tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
 
@@ -10645,10 +10837,20 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                                       cacheline_sz_reg);
        }
 
+       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
+           (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
+               tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
+               if (!tp->pcix_cap) {
+                       printk(KERN_ERR PFX "Cannot find PCI-X "
+                                           "capability, aborting.\n");
+                       return -EIO;
+               }
+       }
+
        pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
                              &pci_state_reg);
 
-       if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
+       if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
                tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
 
                /* If this is a 5700 BX chipset, and we are in PCI-X
@@ -10659,7 +10861,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                 */
                if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
                        u32 pm_reg;
-                       u16 pci_cmd;
 
                        tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
 
@@ -10667,11 +10868,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                         * space registers clobbered due to this bug.
                         * So explicitly force the chip into D0 here.
                         */
-                       pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
+                       pci_read_config_dword(tp->pdev,
+                                             tp->pm_cap + PCI_PM_CTRL,
                                              &pm_reg);
                        pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
                        pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
-                       pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
+                       pci_write_config_dword(tp->pdev,
+                                              tp->pm_cap + PCI_PM_CTRL,
                                               pm_reg);
 
                        /* Also, force SERR#/PERR# in PCI command. */
@@ -10769,6 +10972,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
         */
        tg3_get_eeprom_hw_cfg(tp);
 
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
+               tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
+
        /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
         * GPIO1 driven high will bring 5700's external PHY out of reset.
         * It is also used as eeprom write protect on LOMs.
@@ -10835,7 +11041,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 
        if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) {
                        if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
                            tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
                                tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
@@ -10978,6 +11185,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
         */
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
                tp->dev->hard_start_xmit = tg3_start_xmit;
        else
@@ -11599,6 +11807,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
        case PHY_ID_BCM5780:    return "5780";
        case PHY_ID_BCM5755:    return "5755";
        case PHY_ID_BCM5787:    return "5787";
+       case PHY_ID_BCM5784:    return "5784";
        case PHY_ID_BCM5756:    return "5722/5756";
        case PHY_ID_BCM5906:    return "5906";
        case PHY_ID_BCM8002:    return "8002/serdes";
@@ -11758,7 +11967,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
                goto err_out_free_res;
        }
 
-       SET_MODULE_OWNER(dev);
        SET_NETDEV_DEV(dev, &pdev->dev);
 
 #if TG3_VLAN_TAG_USED
@@ -11805,7 +12013,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
        INIT_WORK(&tp->reset_task, tg3_reset_task);
 
        tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
-       if (tp->regs == 0UL) {
+       if (!tp->regs) {
                printk(KERN_ERR PFX "Cannot map device registers, "
                       "aborting.\n");
                err = -ENOMEM;
@@ -11825,9 +12033,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
        dev->set_mac_address = tg3_set_mac_addr;
        dev->do_ioctl = tg3_ioctl;
        dev->tx_timeout = tg3_tx_timeout;
-       dev->poll = tg3_poll;
+       netif_napi_add(dev, &tp->napi, tg3_poll, 64);
        dev->ethtool_ops = &tg3_ethtool_ops;
-       dev->weight = 64;
        dev->watchdog_timeo = TG3_TX_TIMEOUT;
        dev->change_mtu = tg3_change_mtu;
        dev->irq = pdev->irq;
@@ -11929,7 +12136,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
         */
        if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
            (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
-               pci_save_state(tp->pdev);
                tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
                tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
        }
@@ -11946,7 +12152,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
        if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
                dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
                        dev->features |= NETIF_F_IPV6_CSUM;
 
                tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
@@ -11958,12 +12165,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 
        tg3_init_coal(tp);
 
-       /* Now that we have fully setup the chip, save away a snapshot
-        * of the PCI config space.  We need to restore this after
-        * GRC_MISC_CFG core clock resets and some resume events.
-        */
-       pci_save_state(tp->pdev);
-
        pci_set_drvdata(pdev, dev);
 
        err = register_netdev(dev);
@@ -12047,6 +12248,12 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
        struct tg3 *tp = netdev_priv(dev);
        int err;
 
+       /* PCI register 4 needs to be saved whether netif_running() or not.
+        * MSI address and data need to be saved if using MSI and
+        * netif_running().
+        */
+       pci_save_state(pdev);
+
        if (!netif_running(dev))
                return 0;
 
@@ -12066,9 +12273,6 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
        tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
        tg3_full_unlock(tp);
 
-       /* Save MSI address and data for resume.  */
-       pci_save_state(pdev);
-
        err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
        if (err) {
                tg3_full_lock(tp, 0);
@@ -12096,15 +12300,20 @@ static int tg3_resume(struct pci_dev *pdev)
        struct tg3 *tp = netdev_priv(dev);
        int err;
 
+       pci_restore_state(tp->pdev);
+
        if (!netif_running(dev))
                return 0;
 
-       pci_restore_state(tp->pdev);
-
        err = tg3_set_power_state(tp, PCI_D0);
        if (err)
                return err;
 
+       /* Hardware bug - MSI won't work if INTX disabled. */
+       if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
+           (tp->tg3_flags2 & TG3_FLG2_USING_MSI))
+               pci_intx(tp->pdev, 1);
+
        netif_device_attach(dev);
 
        tg3_full_lock(tp, 0);