Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
[linux-3.10.git] / drivers / gpu / drm / radeon / r600_cs.c
index db8ef19..01a3ec8 100644 (file)
  *          Jerome Glisse
  */
 #include <linux/kernel.h>
-#include "drmP.h"
+#include <drm/drmP.h>
 #include "radeon.h"
 #include "r600d.h"
 #include "r600_reg_safe.h"
 
-static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
-                                       struct radeon_cs_reloc **cs_reloc);
-static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
-                                       struct radeon_cs_reloc **cs_reloc);
-typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
-static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
+static int r600_nomm;
 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
 
 
@@ -47,20 +42,30 @@ struct r600_cs_track {
        u32                     npipes;
        /* value we track */
        u32                     sq_config;
+       u32                     log_nsamples;
        u32                     nsamples;
        u32                     cb_color_base_last[8];
        struct radeon_bo        *cb_color_bo[8];
        u64                     cb_color_bo_mc[8];
-       u32                     cb_color_bo_offset[8];
+       u64                     cb_color_bo_offset[8];
        struct radeon_bo        *cb_color_frag_bo[8];
+       u64                     cb_color_frag_offset[8];
        struct radeon_bo        *cb_color_tile_bo[8];
+       u64                     cb_color_tile_offset[8];
+       u32                     cb_color_mask[8];
        u32                     cb_color_info[8];
-       u32                     cb_color_size_idx[8];
+       u32                     cb_color_view[8];
+       u32                     cb_color_size_idx[8]; /* unused */
        u32                     cb_target_mask;
-       u32                     cb_shader_mask;
+       u32                     cb_shader_mask;  /* unused */
+       bool                    is_resolve;
        u32                     cb_color_size[8];
        u32                     vgt_strmout_en;
        u32                     vgt_strmout_buffer_en;
+       struct radeon_bo        *vgt_strmout_bo[4];
+       u64                     vgt_strmout_bo_mc[4]; /* unused */
+       u32                     vgt_strmout_bo_offset[4];
+       u32                     vgt_strmout_size[4];
        u32                     db_depth_control;
        u32                     db_depth_info;
        u32                     db_depth_size_idx;
@@ -69,13 +74,20 @@ struct r600_cs_track {
        u32                     db_offset;
        struct radeon_bo        *db_bo;
        u64                     db_bo_mc;
+       bool                    sx_misc_kill_all_prims;
+       bool                    cb_dirty;
+       bool                    db_dirty;
+       bool                    streamout_dirty;
+       struct radeon_bo        *htile_bo;
+       u64                     htile_offset;
+       u32                     htile_surface;
 };
 
 #define FMT_8_BIT(fmt, vc)   [fmt] = { 1, 1, 1, vc, CHIP_R600 }
 #define FMT_16_BIT(fmt, vc)  [fmt] = { 1, 1, 2, vc, CHIP_R600 }
-#define FMT_24_BIT(fmt)      [fmt] = { 1, 1, 3,  0, CHIP_R600 }
+#define FMT_24_BIT(fmt)      [fmt] = { 1, 1, 4,  0, CHIP_R600 }
 #define FMT_32_BIT(fmt, vc)  [fmt] = { 1, 1, 4, vc, CHIP_R600 }
-#define FMT_48_BIT(fmt)      [fmt] = { 1, 1, 6,  0, CHIP_R600 }
+#define FMT_48_BIT(fmt)      [fmt] = { 1, 1, 8,  0, CHIP_R600 }
 #define FMT_64_BIT(fmt, vc)  [fmt] = { 1, 1, 8, vc, CHIP_R600 }
 #define FMT_96_BIT(fmt)      [fmt] = { 1, 1, 12, 0, CHIP_R600 }
 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
@@ -107,7 +119,7 @@ static const struct gpu_formats color_formats_table[] = {
 
        /* 24-bit */
        FMT_24_BIT(V_038004_FMT_8_8_8),
-                                              
+
        /* 32-bit */
        FMT_32_BIT(V_038004_COLOR_32, 1),
        FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
@@ -162,22 +174,22 @@ static const struct gpu_formats color_formats_table[] = {
        [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
 };
 
-static inline bool fmt_is_valid_color(u32 format)
+bool r600_fmt_is_valid_color(u32 format)
 {
        if (format >= ARRAY_SIZE(color_formats_table))
                return false;
-       
+
        if (color_formats_table[format].valid_color)
                return true;
 
        return false;
 }
 
-static inline bool fmt_is_valid_texture(u32 format, enum radeon_family family)
+bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
 {
        if (format >= ARRAY_SIZE(color_formats_table))
                return false;
-       
+
        if (family < color_formats_table[format].min_family)
                return false;
 
@@ -187,7 +199,7 @@ static inline bool fmt_is_valid_texture(u32 format, enum radeon_family family)
        return false;
 }
 
-static inline int fmt_get_blocksize(u32 format)
+int r600_fmt_get_blocksize(u32 format)
 {
        if (format >= ARRAY_SIZE(color_formats_table))
                return 0;
@@ -195,7 +207,7 @@ static inline int fmt_get_blocksize(u32 format)
        return color_formats_table[format].blocksize;
 }
 
-static inline int fmt_get_nblocksx(u32 format, u32 w)
+int r600_fmt_get_nblocksx(u32 format, u32 w)
 {
        unsigned bw;
 
@@ -209,7 +221,7 @@ static inline int fmt_get_nblocksx(u32 format, u32 w)
        return (w + bw - 1) / bw;
 }
 
-static inline int fmt_get_nblocksy(u32 format, u32 h)
+int r600_fmt_get_nblocksy(u32 format, u32 h)
 {
        unsigned bh;
 
@@ -223,25 +235,6 @@ static inline int fmt_get_nblocksy(u32 format, u32 h)
        return (h + bh - 1) / bh;
 }
 
-static inline int r600_bpe_from_format(u32 *bpe, u32 format)
-{
-       unsigned res;
-
-       if (format >= ARRAY_SIZE(color_formats_table))
-               goto fail;
-
-       res = color_formats_table[format].blocksize;
-       if (res == 0)
-               goto fail;
-
-       *bpe = res;
-       return 0;
-
-fail:
-       *bpe = 16;
-       return -EINVAL;
-}
-
 struct array_mode_checker {
        int array_mode;
        u32 group_size;
@@ -252,7 +245,7 @@ struct array_mode_checker {
 };
 
 /* returns alignment in pixels for pitch/height/depth and bytes for base */
-static inline int r600_get_array_mode_alignment(struct array_mode_checker *values,
+static int r600_get_array_mode_alignment(struct array_mode_checker *values,
                                                u32 *pitch_align,
                                                u32 *height_align,
                                                u32 *depth_align,
@@ -275,7 +268,7 @@ static inline int r600_get_array_mode_alignment(struct array_mode_checker *value
                break;
        case ARRAY_LINEAR_ALIGNED:
                *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
-               *height_align = tile_height;
+               *height_align = 1;
                *depth_align = 1;
                *base_align = values->group_size;
                break;
@@ -288,10 +281,9 @@ static inline int r600_get_array_mode_alignment(struct array_mode_checker *value
                *base_align = values->group_size;
                break;
        case ARRAY_2D_TILED_THIN1:
-               *pitch_align = max((u32)macro_tile_width,
-                                 (u32)(((values->group_size / tile_height) /
-                                        (values->blocksize * values->nsamples)) *
-                                       values->nbanks)) * tile_width;
+               *pitch_align = max((u32)macro_tile_width * tile_width,
+                               (u32)((values->group_size * values->nbanks) /
+                               (values->blocksize * values->nsamples * tile_width)));
                *height_align = macro_tile_height * tile_height;
                *depth_align = 1;
                *base_align = max(macro_tile_bytes,
@@ -315,12 +307,22 @@ static void r600_cs_track_init(struct r600_cs_track *track)
                track->cb_color_size[i] = 0;
                track->cb_color_size_idx[i] = 0;
                track->cb_color_info[i] = 0;
+               track->cb_color_view[i] = 0xFFFFFFFF;
                track->cb_color_bo[i] = NULL;
                track->cb_color_bo_offset[i] = 0xFFFFFFFF;
                track->cb_color_bo_mc[i] = 0xFFFFFFFF;
+               track->cb_color_frag_bo[i] = NULL;
+               track->cb_color_frag_offset[i] = 0xFFFFFFFF;
+               track->cb_color_tile_bo[i] = NULL;
+               track->cb_color_tile_offset[i] = 0xFFFFFFFF;
+               track->cb_color_mask[i] = 0xFFFFFFFF;
        }
+       track->is_resolve = false;
+       track->nsamples = 16;
+       track->log_nsamples = 4;
        track->cb_target_mask = 0xFFFFFFFF;
        track->cb_shader_mask = 0xFFFFFFFF;
+       track->cb_dirty = true;
        track->db_bo = NULL;
        track->db_bo_mc = 0xFFFFFFFF;
        /* assume the biggest format and that htile is enabled */
@@ -329,25 +331,37 @@ static void r600_cs_track_init(struct r600_cs_track *track)
        track->db_depth_size = 0xFFFFFFFF;
        track->db_depth_size_idx = 0;
        track->db_depth_control = 0xFFFFFFFF;
+       track->db_dirty = true;
+       track->htile_bo = NULL;
+       track->htile_offset = 0xFFFFFFFF;
+       track->htile_surface = 0;
+
+       for (i = 0; i < 4; i++) {
+               track->vgt_strmout_size[i] = 0;
+               track->vgt_strmout_bo[i] = NULL;
+               track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
+               track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
+       }
+       track->streamout_dirty = true;
+       track->sx_misc_kill_all_prims = false;
 }
 
-static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
+static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
 {
        struct r600_cs_track *track = p->track;
        u32 slice_tile_max, size, tmp;
        u32 height, height_align, pitch, pitch_align, depth_align;
        u64 base_offset, base_align;
        struct array_mode_checker array_check;
-       volatile u32 *ib = p->ib->ptr;
+       volatile u32 *ib = p->ib.ptr;
        unsigned array_mode;
        u32 format;
-       if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
-               dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
-               return -EINVAL;
-       }
+       /* When resolve is used, the second colorbuffer has always 1 sample. */
+       unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
+
        size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
        format = G_0280A0_FORMAT(track->cb_color_info[i]);
-       if (!fmt_is_valid_color(format)) {
+       if (!r600_fmt_is_valid_color(format)) {
                dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
                         __func__, __LINE__, format,
                        i, track->cb_color_info[i]);
@@ -367,8 +381,8 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
        array_check.group_size = track->group_size;
        array_check.nbanks = track->nbanks;
        array_check.npipes = track->npipes;
-       array_check.nsamples = track->nsamples;
-       array_check.blocksize = fmt_get_blocksize(format);
+       array_check.nsamples = nsamples;
+       array_check.blocksize = r600_fmt_get_blocksize(format);
        if (r600_get_array_mode_alignment(&array_check,
                                          &pitch_align, &height_align, &depth_align, &base_align)) {
                dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
@@ -412,7 +426,19 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
        }
 
        /* check offset */
-       tmp = fmt_get_nblocksy(format, height) * fmt_get_nblocksx(format, pitch) * fmt_get_blocksize(format);
+       tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
+             r600_fmt_get_blocksize(format) * nsamples;
+       switch (array_mode) {
+       default:
+       case V_0280A0_ARRAY_LINEAR_GENERAL:
+       case V_0280A0_ARRAY_LINEAR_ALIGNED:
+               tmp += track->cb_color_view[i] & 0xFF;
+               break;
+       case V_0280A0_ARRAY_1D_TILED_THIN1:
+       case V_0280A0_ARRAY_2D_TILED_THIN1:
+               tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
+               break;
+       }
        if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
                if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
                        /* the initial DDX does bad things with the CB size occasionally */
@@ -422,10 +448,13 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
                         * broken userspace.
                         */
                } else {
-                       dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big\n", __func__, i,
-                                array_mode,
+                       dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
+                                __func__, i, array_mode,
                                 track->cb_color_bo_offset[i], tmp,
-                                radeon_bo_size(track->cb_color_bo[i]));
+                                radeon_bo_size(track->cb_color_bo[i]),
+                                pitch, height, r600_fmt_get_nblocksx(format, pitch),
+                                r600_fmt_get_nblocksy(format, height),
+                                r600_fmt_get_blocksize(format));
                        return -EINVAL;
                }
        }
@@ -436,325 +465,343 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
        tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
                S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
        ib[track->cb_color_size_idx[i]] = tmp;
+
+       /* FMASK/CMASK */
+       switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
+       case V_0280A0_TILE_DISABLE:
+               break;
+       case V_0280A0_FRAG_ENABLE:
+               if (track->nsamples > 1) {
+                       uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
+                       /* the tile size is 8x8, but the size is in units of bits.
+                        * for bytes, do just * 8. */
+                       uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
+
+                       if (bytes + track->cb_color_frag_offset[i] >
+                           radeon_bo_size(track->cb_color_frag_bo[i])) {
+                               dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
+                                        "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
+                                        __func__, tile_max, bytes,
+                                        track->cb_color_frag_offset[i],
+                                        radeon_bo_size(track->cb_color_frag_bo[i]));
+                               return -EINVAL;
+                       }
+               }
+               /* fall through */
+       case V_0280A0_CLEAR_ENABLE:
+       {
+               uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
+               /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
+                * (128*128) / (8*8) / 2 = 128 bytes per block. */
+               uint32_t bytes = (block_max + 1) * 128;
+
+               if (bytes + track->cb_color_tile_offset[i] >
+                   radeon_bo_size(track->cb_color_tile_bo[i])) {
+                       dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
+                                "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
+                                __func__, block_max, bytes,
+                                track->cb_color_tile_offset[i],
+                                radeon_bo_size(track->cb_color_tile_bo[i]));
+                       return -EINVAL;
+               }
+               break;
+       }
+       default:
+               dev_warn(p->dev, "%s invalid tile mode\n", __func__);
+               return -EINVAL;
+       }
        return 0;
 }
 
-static int r600_cs_track_check(struct radeon_cs_parser *p)
+static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
 {
        struct r600_cs_track *track = p->track;
-       u32 tmp;
-       int r, i;
-       volatile u32 *ib = p->ib->ptr;
+       u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
+       u32 height_align, pitch_align, depth_align;
+       u32 pitch = 8192;
+       u32 height = 8192;
+       u64 base_offset, base_align;
+       struct array_mode_checker array_check;
+       int array_mode;
+       volatile u32 *ib = p->ib.ptr;
 
-       /* on legacy kernel we don't perform advanced check */
-       if (p->rdev == NULL)
-               return 0;
-       /* we don't support out buffer yet */
-       if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
-               dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
+
+       if (track->db_bo == NULL) {
+               dev_warn(p->dev, "z/stencil with no depth buffer\n");
                return -EINVAL;
        }
-       /* check that we have a cb for each enabled target, we don't check
-        * shader_mask because it seems mesa isn't always setting it :(
-        */
-       tmp = track->cb_target_mask;
-       for (i = 0; i < 8; i++) {
-               if ((tmp >> (i * 4)) & 0xF) {
-                       /* at least one component is enabled */
-                       if (track->cb_color_bo[i] == NULL) {
-                               dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
-                                       __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
-                               return -EINVAL;
-                       }
-                       /* perform rewrite of CB_COLOR[0-7]_SIZE */
-                       r = r600_cs_track_validate_cb(p, i);
-                       if (r)
-                               return r;
-               }
+       switch (G_028010_FORMAT(track->db_depth_info)) {
+       case V_028010_DEPTH_16:
+               bpe = 2;
+               break;
+       case V_028010_DEPTH_X8_24:
+       case V_028010_DEPTH_8_24:
+       case V_028010_DEPTH_X8_24_FLOAT:
+       case V_028010_DEPTH_8_24_FLOAT:
+       case V_028010_DEPTH_32_FLOAT:
+               bpe = 4;
+               break;
+       case V_028010_DEPTH_X24_8_32_FLOAT:
+               bpe = 8;
+               break;
+       default:
+               dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
+               return -EINVAL;
        }
-       /* Check depth buffer */
-       if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
-               G_028800_Z_ENABLE(track->db_depth_control)) {
-               u32 nviews, bpe, ntiles, size, slice_tile_max;
-               u32 height, height_align, pitch, pitch_align, depth_align;
-               u64 base_offset, base_align;
-               struct array_mode_checker array_check;
-               int array_mode;
-
-               if (track->db_bo == NULL) {
-                       dev_warn(p->dev, "z/stencil with no depth buffer\n");
+       if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
+               if (!track->db_depth_size_idx) {
+                       dev_warn(p->dev, "z/stencil buffer size not set\n");
                        return -EINVAL;
                }
-               if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
-                       dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
+               tmp = radeon_bo_size(track->db_bo) - track->db_offset;
+               tmp = (tmp / bpe) >> 6;
+               if (!tmp) {
+                       dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
+                                       track->db_depth_size, bpe, track->db_offset,
+                                       radeon_bo_size(track->db_bo));
                        return -EINVAL;
                }
-               switch (G_028010_FORMAT(track->db_depth_info)) {
-               case V_028010_DEPTH_16:
-                       bpe = 2;
-                       break;
-               case V_028010_DEPTH_X8_24:
-               case V_028010_DEPTH_8_24:
-               case V_028010_DEPTH_X8_24_FLOAT:
-               case V_028010_DEPTH_8_24_FLOAT:
-               case V_028010_DEPTH_32_FLOAT:
-                       bpe = 4;
+               ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
+       } else {
+               size = radeon_bo_size(track->db_bo);
+               /* pitch in pixels */
+               pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
+               slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
+               slice_tile_max *= 64;
+               height = slice_tile_max / pitch;
+               if (height > 8192)
+                       height = 8192;
+               base_offset = track->db_bo_mc + track->db_offset;
+               array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
+               array_check.array_mode = array_mode;
+               array_check.group_size = track->group_size;
+               array_check.nbanks = track->nbanks;
+               array_check.npipes = track->npipes;
+               array_check.nsamples = track->nsamples;
+               array_check.blocksize = bpe;
+               if (r600_get_array_mode_alignment(&array_check,
+                                       &pitch_align, &height_align, &depth_align, &base_align)) {
+                       dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
+                                       G_028010_ARRAY_MODE(track->db_depth_info),
+                                       track->db_depth_info);
+                       return -EINVAL;
+               }
+               switch (array_mode) {
+               case V_028010_ARRAY_1D_TILED_THIN1:
+                       /* don't break userspace */
+                       height &= ~0x7;
                        break;
-               case V_028010_DEPTH_X24_8_32_FLOAT:
-                       bpe = 8;
+               case V_028010_ARRAY_2D_TILED_THIN1:
                        break;
                default:
-                       dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
+                       dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
+                                       G_028010_ARRAY_MODE(track->db_depth_info),
+                                       track->db_depth_info);
+                       return -EINVAL;
+               }
+
+               if (!IS_ALIGNED(pitch, pitch_align)) {
+                       dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
+                                       __func__, __LINE__, pitch, pitch_align, array_mode);
+                       return -EINVAL;
+               }
+               if (!IS_ALIGNED(height, height_align)) {
+                       dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
+                                       __func__, __LINE__, height, height_align, array_mode);
+                       return -EINVAL;
+               }
+               if (!IS_ALIGNED(base_offset, base_align)) {
+                       dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,
+                                       base_offset, base_align, array_mode);
+                       return -EINVAL;
+               }
+
+               ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
+               nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
+               tmp = ntiles * bpe * 64 * nviews * track->nsamples;
+               if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
+                       dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
+                                       array_mode,
+                                       track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
+                                       radeon_bo_size(track->db_bo));
+                       return -EINVAL;
+               }
+       }
+
+       /* hyperz */
+       if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
+               unsigned long size;
+               unsigned nbx, nby;
+
+               if (track->htile_bo == NULL) {
+                       dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
+                                __func__, __LINE__, track->db_depth_info);
                        return -EINVAL;
                }
                if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
-                       if (!track->db_depth_size_idx) {
-                               dev_warn(p->dev, "z/stencil buffer size not set\n");
-                               return -EINVAL;
-                       }
-                       tmp = radeon_bo_size(track->db_bo) - track->db_offset;
-                       tmp = (tmp / bpe) >> 6;
-                       if (!tmp) {
-                               dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
-                                               track->db_depth_size, bpe, track->db_offset,
-                                               radeon_bo_size(track->db_bo));
-                               return -EINVAL;
-                       }
-                       ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
+                       dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
+                                __func__, __LINE__, track->db_depth_size);
+                       return -EINVAL;
+               }
+
+               nbx = pitch;
+               nby = height;
+               if (G_028D24_LINEAR(track->htile_surface)) {
+                       /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
+                       nbx = round_up(nbx, 16 * 8);
+                       /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
+                       nby = round_up(nby, track->npipes * 8);
                } else {
-                       size = radeon_bo_size(track->db_bo);
-                       /* pitch in pixels */
-                       pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
-                       slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
-                       slice_tile_max *= 64;
-                       height = slice_tile_max / pitch;
-                       if (height > 8192)
-                               height = 8192;
-                       base_offset = track->db_bo_mc + track->db_offset;
-                       array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
-                       array_check.array_mode = array_mode;
-                       array_check.group_size = track->group_size;
-                       array_check.nbanks = track->nbanks;
-                       array_check.npipes = track->npipes;
-                       array_check.nsamples = track->nsamples;
-                       array_check.blocksize = bpe;
-                       if (r600_get_array_mode_alignment(&array_check,
-                                                         &pitch_align, &height_align, &depth_align, &base_align)) {
-                               dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
-                                        G_028010_ARRAY_MODE(track->db_depth_info),
-                                        track->db_depth_info);
-                               return -EINVAL;
-                       }
-                       switch (array_mode) {
-                       case V_028010_ARRAY_1D_TILED_THIN1:
-                               /* don't break userspace */
-                               height &= ~0x7;
+                       /* always assume 8x8 htile */
+                       /* align is htile align * 8, htile align vary according to
+                        * number of pipe and tile width and nby
+                        */
+                       switch (track->npipes) {
+                       case 8:
+                               /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
+                               nbx = round_up(nbx, 64 * 8);
+                               nby = round_up(nby, 64 * 8);
+                               break;
+                       case 4:
+                               /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
+                               nbx = round_up(nbx, 64 * 8);
+                               nby = round_up(nby, 32 * 8);
                                break;
-                       case V_028010_ARRAY_2D_TILED_THIN1:
+                       case 2:
+                               /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
+                               nbx = round_up(nbx, 32 * 8);
+                               nby = round_up(nby, 32 * 8);
+                               break;
+                       case 1:
+                               /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
+                               nbx = round_up(nbx, 32 * 8);
+                               nby = round_up(nby, 16 * 8);
                                break;
                        default:
-                               dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
-                                        G_028010_ARRAY_MODE(track->db_depth_info),
-                                        track->db_depth_info);
-                               return -EINVAL;
-                       }
-
-                       if (!IS_ALIGNED(pitch, pitch_align)) {
-                               dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
-                                        __func__, __LINE__, pitch, pitch_align, array_mode);
-                               return -EINVAL;
-                       }
-                       if (!IS_ALIGNED(height, height_align)) {
-                               dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
-                                        __func__, __LINE__, height, height_align, array_mode);
-                               return -EINVAL;
-                       }
-                       if (!IS_ALIGNED(base_offset, base_align)) {
-                               dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i,
-                                        base_offset, base_align, array_mode);
-                               return -EINVAL;
-                       }
-
-                       ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
-                       nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
-                       tmp = ntiles * bpe * 64 * nviews;
-                       if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
-                               dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
-                                        array_mode,
-                                        track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
-                                        radeon_bo_size(track->db_bo));
+                               dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
+                                        __func__, __LINE__, track->npipes);
                                return -EINVAL;
                        }
                }
+               /* compute number of htile */
+               nbx = nbx >> 3;
+               nby = nby >> 3;
+               /* size must be aligned on npipes * 2K boundary */
+               size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
+               size += track->htile_offset;
+
+               if (size > radeon_bo_size(track->htile_bo)) {
+                       dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
+                                __func__, __LINE__, radeon_bo_size(track->htile_bo),
+                                size, nbx, nby);
+                       return -EINVAL;
+               }
        }
+
+       track->db_dirty = false;
        return 0;
 }
 
-/**
- * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
- * @parser:    parser structure holding parsing context.
- * @pkt:       where to store packet informations
- *
- * Assume that chunk_ib_index is properly set. Will return -EINVAL
- * if packet is bigger than remaining ib size. or if packets is unknown.
- **/
-int r600_cs_packet_parse(struct radeon_cs_parser *p,
-                       struct radeon_cs_packet *pkt,
-                       unsigned idx)
+static int r600_cs_track_check(struct radeon_cs_parser *p)
 {
-       struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
-       uint32_t header;
+       struct r600_cs_track *track = p->track;
+       u32 tmp;
+       int r, i;
 
-       if (idx >= ib_chunk->length_dw) {
-               DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
-                         idx, ib_chunk->length_dw);
-               return -EINVAL;
-       }
-       header = radeon_get_ib_value(p, idx);
-       pkt->idx = idx;
-       pkt->type = CP_PACKET_GET_TYPE(header);
-       pkt->count = CP_PACKET_GET_COUNT(header);
-       pkt->one_reg_wr = 0;
-       switch (pkt->type) {
-       case PACKET_TYPE0:
-               pkt->reg = CP_PACKET0_GET_REG(header);
-               break;
-       case PACKET_TYPE3:
-               pkt->opcode = CP_PACKET3_GET_OPCODE(header);
-               break;
-       case PACKET_TYPE2:
-               pkt->count = -1;
-               break;
-       default:
-               DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
-               return -EINVAL;
-       }
-       if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
-               DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
-                         pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
-               return -EINVAL;
+       /* on legacy kernel we don't perform advanced check */
+       if (p->rdev == NULL)
+               return 0;
+
+       /* check streamout */
+       if (track->streamout_dirty && track->vgt_strmout_en) {
+               for (i = 0; i < 4; i++) {
+                       if (track->vgt_strmout_buffer_en & (1 << i)) {
+                               if (track->vgt_strmout_bo[i]) {
+                                       u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
+                                               (u64)track->vgt_strmout_size[i];
+                                       if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
+                                               DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
+                                                         i, offset,
+                                                         radeon_bo_size(track->vgt_strmout_bo[i]));
+                                               return -EINVAL;
+                                       }
+                               } else {
+                                       dev_warn(p->dev, "No buffer for streamout %d\n", i);
+                                       return -EINVAL;
+                               }
+                       }
+               }
+               track->streamout_dirty = false;
        }
-       return 0;
-}
 
-/**
- * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
- * @parser:            parser structure holding parsing context.
- * @data:              pointer to relocation data
- * @offset_start:      starting offset
- * @offset_mask:       offset mask (to align start offset on)
- * @reloc:             reloc informations
- *
- * Check next packet is relocation packet3, do bo validation and compute
- * GPU offset using the provided start.
- **/
-static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
-                                       struct radeon_cs_reloc **cs_reloc)
-{
-       struct radeon_cs_chunk *relocs_chunk;
-       struct radeon_cs_packet p3reloc;
-       unsigned idx;
-       int r;
+       if (track->sx_misc_kill_all_prims)
+               return 0;
 
-       if (p->chunk_relocs_idx == -1) {
-               DRM_ERROR("No relocation chunk !\n");
-               return -EINVAL;
-       }
-       *cs_reloc = NULL;
-       relocs_chunk = &p->chunks[p->chunk_relocs_idx];
-       r = r600_cs_packet_parse(p, &p3reloc, p->idx);
-       if (r) {
-               return r;
-       }
-       p->idx += p3reloc.count + 2;
-       if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
-               DRM_ERROR("No packet3 for relocation for packet at %d.\n",
-                         p3reloc.idx);
-               return -EINVAL;
-       }
-       idx = radeon_get_ib_value(p, p3reloc.idx + 1);
-       if (idx >= relocs_chunk->length_dw) {
-               DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
-                         idx, relocs_chunk->length_dw);
-               return -EINVAL;
-       }
-       /* FIXME: we assume reloc size is 4 dwords */
-       *cs_reloc = p->relocs_ptr[(idx / 4)];
-       return 0;
-}
+       /* check that we have a cb for each enabled target, we don't check
+        * shader_mask because it seems mesa isn't always setting it :(
+        */
+       if (track->cb_dirty) {
+               tmp = track->cb_target_mask;
 
-/**
- * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
- * @parser:            parser structure holding parsing context.
- * @data:              pointer to relocation data
- * @offset_start:      starting offset
- * @offset_mask:       offset mask (to align start offset on)
- * @reloc:             reloc informations
- *
- * Check next packet is relocation packet3, do bo validation and compute
- * GPU offset using the provided start.
- **/
-static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
-                                       struct radeon_cs_reloc **cs_reloc)
-{
-       struct radeon_cs_chunk *relocs_chunk;
-       struct radeon_cs_packet p3reloc;
-       unsigned idx;
-       int r;
+               /* We must check both colorbuffers for RESOLVE. */
+               if (track->is_resolve) {
+                       tmp |= 0xff;
+               }
 
-       if (p->chunk_relocs_idx == -1) {
-               DRM_ERROR("No relocation chunk !\n");
-               return -EINVAL;
-       }
-       *cs_reloc = NULL;
-       relocs_chunk = &p->chunks[p->chunk_relocs_idx];
-       r = r600_cs_packet_parse(p, &p3reloc, p->idx);
-       if (r) {
-               return r;
-       }
-       p->idx += p3reloc.count + 2;
-       if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
-               DRM_ERROR("No packet3 for relocation for packet at %d.\n",
-                         p3reloc.idx);
-               return -EINVAL;
+               for (i = 0; i < 8; i++) {
+                       if ((tmp >> (i * 4)) & 0xF) {
+                               /* at least one component is enabled */
+                               if (track->cb_color_bo[i] == NULL) {
+                                       dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
+                                               __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
+                                       return -EINVAL;
+                               }
+                               /* perform rewrite of CB_COLOR[0-7]_SIZE */
+                               r = r600_cs_track_validate_cb(p, i);
+                               if (r)
+                                       return r;
+                       }
+               }
+               track->cb_dirty = false;
        }
-       idx = radeon_get_ib_value(p, p3reloc.idx + 1);
-       if (idx >= relocs_chunk->length_dw) {
-               DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
-                         idx, relocs_chunk->length_dw);
-               return -EINVAL;
+
+       /* Check depth buffer */
+       if (track->db_dirty &&
+           G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
+           (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
+            G_028800_Z_ENABLE(track->db_depth_control))) {
+               r = r600_cs_track_validate_db(p);
+               if (r)
+                       return r;
        }
-       *cs_reloc = p->relocs;
-       (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
-       (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
+
        return 0;
 }
 
 /**
- * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
+ * r600_cs_packet_parse_vline() - parse userspace VLINE packet
  * @parser:            parser structure holding parsing context.
  *
- * Check next packet is relocation packet3, do bo validation and compute
- * GPU offset using the provided start.
- **/
-static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
+ * This is an R600-specific function for parsing VLINE packets.
+ * Real work is done by r600_cs_common_vline_parse function.
+ * Here we just set up ASIC-specific register table and call
+ * the common implementation function.
+ */
+static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
 {
-       struct radeon_cs_packet p3reloc;
-       int r;
+       static uint32_t vline_start_end[2] = {AVIVO_D1MODE_VLINE_START_END,
+                                             AVIVO_D2MODE_VLINE_START_END};
+       static uint32_t vline_status[2] = {AVIVO_D1MODE_VLINE_STATUS,
+                                          AVIVO_D2MODE_VLINE_STATUS};
 
-       r = r600_cs_packet_parse(p, &p3reloc, p->idx);
-       if (r) {
-               return 0;
-       }
-       if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
-               return 0;
-       }
-       return 1;
+       return r600_cs_common_vline_parse(p, vline_start_end, vline_status);
 }
 
 /**
- * r600_cs_packet_next_vline() - parse userspace VLINE packet
+ * r600_cs_common_vline_parse() - common vline parser
  * @parser:            parser structure holding parsing context.
+ * @vline_start_end:    table of vline_start_end registers
+ * @vline_status:       table of vline_status registers
  *
  * Userspace sends a special sequence for VLINE waits.
  * PACKET0 - VLINE_START_END + value
@@ -764,9 +811,16 @@ static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
  * This function parses this and relocates the VLINE START END
  * and WAIT_REG_MEM packets to the correct crtc.
  * It also detects a switched off crtc and nulls out the
- * wait in that case.
+ * wait in that case. This function is common for all ASICs that
+ * are R600 and newer. The parsing algorithm is the same, and only
+ * differs in which registers are used.
+ *
+ * Caller is the ASIC-specific function which passes the parser
+ * context and ASIC-specific register table
  */
-static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
+int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
+                              uint32_t *vline_start_end,
+                              uint32_t *vline_status)
 {
        struct drm_mode_object *obj;
        struct drm_crtc *crtc;
@@ -777,15 +831,15 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
        uint32_t header, h_idx, reg, wait_reg_mem_info;
        volatile uint32_t *ib;
 
-       ib = p->ib->ptr;
+       ib = p->ib.ptr;
 
        /* parse the WAIT_REG_MEM */
-       r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
+       r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx);
        if (r)
                return r;
 
        /* check its a WAIT_REG_MEM */
-       if (wait_reg_mem.type != PACKET_TYPE3 ||
+       if (wait_reg_mem.type != RADEON_PACKET_TYPE3 ||
            wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
                DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
                return -EINVAL;
@@ -794,7 +848,12 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
        wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
        /* bit 4 is reg (0) or mem (1) */
        if (wait_reg_mem_info & 0x10) {
-               DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
+               DRM_ERROR("vline WAIT_REG_MEM waiting on MEM instead of REG\n");
+               return -EINVAL;
+       }
+       /* bit 8 is me (0) or pfp (1) */
+       if (wait_reg_mem_info & 0x100) {
+               DRM_ERROR("vline WAIT_REG_MEM waiting on PFP instead of ME\n");
                return -EINVAL;
        }
        /* waiting for value to be equal */
@@ -802,18 +861,18 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
                DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
                return -EINVAL;
        }
-       if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
+       if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) {
                DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
                return -EINVAL;
        }
 
-       if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
+       if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) {
                DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
                return -EINVAL;
        }
 
        /* jump over the NOP */
-       r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
+       r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
        if (r)
                return r;
 
@@ -823,7 +882,7 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
 
        header = radeon_get_ib_value(p, h_idx);
        crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
-       reg = CP_PACKET0_GET_REG(header);
+       reg = R600_CP_PACKET0_GET_REG(header);
 
        obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
        if (!obj) {
@@ -835,7 +894,7 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
        crtc_id = radeon_crtc->crtc_id;
 
        if (!crtc->enabled) {
-               /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
+               /* CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
                ib[h_idx + 2] = PACKET2(0);
                ib[h_idx + 3] = PACKET2(0);
                ib[h_idx + 4] = PACKET2(0);
@@ -843,20 +902,15 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
                ib[h_idx + 6] = PACKET2(0);
                ib[h_idx + 7] = PACKET2(0);
                ib[h_idx + 8] = PACKET2(0);
-       } else if (crtc_id == 1) {
-               switch (reg) {
-               case AVIVO_D1MODE_VLINE_START_END:
-                       header &= ~R600_CP_PACKET0_REG_MASK;
-                       header |= AVIVO_D2MODE_VLINE_START_END >> 2;
-                       break;
-               default:
-                       DRM_ERROR("unknown crtc reloc\n");
-                       return -EINVAL;
-               }
+       } else if (reg == vline_start_end[0]) {
+               header &= ~R600_CP_PACKET0_REG_MASK;
+               header |= vline_start_end[crtc_id] >> 2;
                ib[h_idx] = header;
-               ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
+               ib[h_idx + 4] = vline_status[crtc_id] >> 2;
+       } else {
+               DRM_ERROR("unknown crtc reloc\n");
+               return -EINVAL;
        }
-
        return 0;
 }
 
@@ -911,23 +965,22 @@ static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
  * if register is safe. If register is not flag as safe this function
  * will test it against a list of register needind special handling.
  */
-static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
+static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
 {
        struct r600_cs_track *track = (struct r600_cs_track *)p->track;
        struct radeon_cs_reloc *reloc;
-       u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
        u32 m, i, tmp, *ib;
        int r;
 
        i = (reg >> 7);
-       if (i > last_reg) {
+       if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
                dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
                return -EINVAL;
        }
        m = 1 << ((reg >> 2) & 31);
        if (!(r600_reg_safe_bm[i] & m))
                return 0;
-       ib = p->ib->ptr;
+       ib = p->ib.ptr;
        switch (reg) {
        /* force following reg to 0 in an attempt to disable out buffer
         * which will need us to better understand how it works to perform
@@ -959,10 +1012,12 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
                break;
        case R_028800_DB_DEPTH_CONTROL:
                track->db_depth_control = radeon_get_ib_value(p, idx);
+               track->db_dirty = true;
                break;
        case R_028010_DB_DEPTH_INFO:
-               if (r600_cs_packet_next_is_pkt3_nop(p)) {
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+               if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
+                   radeon_cs_packet_next_is_pkt3_nop(p)) {
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                         "0x%04X\n", reg);
@@ -978,31 +1033,80 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
                                ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
                                track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
                        }
-               } else
+               } else {
                        track->db_depth_info = radeon_get_ib_value(p, idx);
+               }
+               track->db_dirty = true;
                break;
        case R_028004_DB_DEPTH_VIEW:
                track->db_depth_view = radeon_get_ib_value(p, idx);
+               track->db_dirty = true;
                break;
        case R_028000_DB_DEPTH_SIZE:
                track->db_depth_size = radeon_get_ib_value(p, idx);
                track->db_depth_size_idx = idx;
+               track->db_dirty = true;
                break;
        case R_028AB0_VGT_STRMOUT_EN:
                track->vgt_strmout_en = radeon_get_ib_value(p, idx);
+               track->streamout_dirty = true;
                break;
        case R_028B20_VGT_STRMOUT_BUFFER_EN:
                track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
+               track->streamout_dirty = true;
+               break;
+       case VGT_STRMOUT_BUFFER_BASE_0:
+       case VGT_STRMOUT_BUFFER_BASE_1:
+       case VGT_STRMOUT_BUFFER_BASE_2:
+       case VGT_STRMOUT_BUFFER_BASE_3:
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
+               if (r) {
+                       dev_warn(p->dev, "bad SET_CONTEXT_REG "
+                                       "0x%04X\n", reg);
+                       return -EINVAL;
+               }
+               tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
+               track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
+               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               track->vgt_strmout_bo[tmp] = reloc->robj;
+               track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
+               track->streamout_dirty = true;
+               break;
+       case VGT_STRMOUT_BUFFER_SIZE_0:
+       case VGT_STRMOUT_BUFFER_SIZE_1:
+       case VGT_STRMOUT_BUFFER_SIZE_2:
+       case VGT_STRMOUT_BUFFER_SIZE_3:
+               tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
+               /* size in register is DWs, convert to bytes */
+               track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
+               track->streamout_dirty = true;
+               break;
+       case CP_COHER_BASE:
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
+               if (r) {
+                       dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
+                                       "0x%04X\n", reg);
+                       return -EINVAL;
+               }
+               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                break;
        case R_028238_CB_TARGET_MASK:
                track->cb_target_mask = radeon_get_ib_value(p, idx);
+               track->cb_dirty = true;
                break;
        case R_02823C_CB_SHADER_MASK:
                track->cb_shader_mask = radeon_get_ib_value(p, idx);
                break;
        case R_028C04_PA_SC_AA_CONFIG:
                tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
+               track->log_nsamples = tmp;
                track->nsamples = 1 << tmp;
+               track->cb_dirty = true;
+               break;
+       case R_028808_CB_COLOR_CONTROL:
+               tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
+               track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
+               track->cb_dirty = true;
                break;
        case R_0280A0_CB_COLOR0_INFO:
        case R_0280A4_CB_COLOR1_INFO:
@@ -1012,8 +1116,9 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
        case R_0280B4_CB_COLOR5_INFO:
        case R_0280B8_CB_COLOR6_INFO:
        case R_0280BC_CB_COLOR7_INFO:
-               if (r600_cs_packet_next_is_pkt3_nop(p)) {
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+               if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
+                    radeon_cs_packet_next_is_pkt3_nop(p)) {
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
                                return -EINVAL;
@@ -1031,6 +1136,19 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
                        tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
                        track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
                }
+               track->cb_dirty = true;
+               break;
+       case R_028080_CB_COLOR0_VIEW:
+       case R_028084_CB_COLOR1_VIEW:
+       case R_028088_CB_COLOR2_VIEW:
+       case R_02808C_CB_COLOR3_VIEW:
+       case R_028090_CB_COLOR4_VIEW:
+       case R_028094_CB_COLOR5_VIEW:
+       case R_028098_CB_COLOR6_VIEW:
+       case R_02809C_CB_COLOR7_VIEW:
+               tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
+               track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
+               track->cb_dirty = true;
                break;
        case R_028060_CB_COLOR0_SIZE:
        case R_028064_CB_COLOR1_SIZE:
@@ -1043,6 +1161,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
                tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
                track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
                track->cb_color_size_idx[tmp] = idx;
+               track->cb_dirty = true;
                break;
                /* This register were added late, there is userspace
                 * which does provide relocation for those but set
@@ -1062,21 +1181,26 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
        case R_0280F8_CB_COLOR6_FRAG:
        case R_0280FC_CB_COLOR7_FRAG:
                tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
-               if (!r600_cs_packet_next_is_pkt3_nop(p)) {
+               if (!radeon_cs_packet_next_is_pkt3_nop(p)) {
                        if (!track->cb_color_base_last[tmp]) {
                                dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
                                return -EINVAL;
                        }
-                       ib[idx] = track->cb_color_base_last[tmp];
                        track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
+                       track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
+                       ib[idx] = track->cb_color_base_last[tmp];
                } else {
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
                                return -EINVAL;
                        }
-                       ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                        track->cb_color_frag_bo[tmp] = reloc->robj;
+                       track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
+                       ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               }
+               if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
+                       track->cb_dirty = true;
                }
                break;
        case R_0280C0_CB_COLOR0_TILE:
@@ -1088,21 +1212,40 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
        case R_0280D8_CB_COLOR6_TILE:
        case R_0280DC_CB_COLOR7_TILE:
                tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
-               if (!r600_cs_packet_next_is_pkt3_nop(p)) {
+               if (!radeon_cs_packet_next_is_pkt3_nop(p)) {
                        if (!track->cb_color_base_last[tmp]) {
                                dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
                                return -EINVAL;
                        }
-                       ib[idx] = track->cb_color_base_last[tmp];
                        track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
+                       track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
+                       ib[idx] = track->cb_color_base_last[tmp];
                } else {
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
                                return -EINVAL;
                        }
-                       ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                        track->cb_color_tile_bo[tmp] = reloc->robj;
+                       track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
+                       ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               }
+               if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
+                       track->cb_dirty = true;
+               }
+               break;
+       case R_028100_CB_COLOR0_MASK:
+       case R_028104_CB_COLOR1_MASK:
+       case R_028108_CB_COLOR2_MASK:
+       case R_02810C_CB_COLOR3_MASK:
+       case R_028110_CB_COLOR4_MASK:
+       case R_028114_CB_COLOR5_MASK:
+       case R_028118_CB_COLOR6_MASK:
+       case R_02811C_CB_COLOR7_MASK:
+               tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
+               track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
+               if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
+                       track->cb_dirty = true;
                }
                break;
        case CB_COLOR0_BASE:
@@ -1113,7 +1256,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
        case CB_COLOR5_BASE:
        case CB_COLOR6_BASE:
        case CB_COLOR7_BASE:
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1125,9 +1268,10 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
                track->cb_color_base_last[tmp] = ib[idx];
                track->cb_color_bo[tmp] = reloc->robj;
                track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
+               track->cb_dirty = true;
                break;
        case DB_DEPTH_BASE:
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1137,8 +1281,26 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
                ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                track->db_bo = reloc->robj;
                track->db_bo_mc = reloc->lobj.gpu_offset;
+               track->db_dirty = true;
                break;
        case DB_HTILE_DATA_BASE:
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
+               if (r) {
+                       dev_warn(p->dev, "bad SET_CONTEXT_REG "
+                                       "0x%04X\n", reg);
+                       return -EINVAL;
+               }
+               track->htile_offset = radeon_get_ib_value(p, idx) << 8;
+               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               track->htile_bo = reloc->robj;
+               track->db_dirty = true;
+               break;
+       case DB_HTILE_SURFACE:
+               track->htile_surface = radeon_get_ib_value(p, idx);
+               /* force 8x8 htile width and height */
+               ib[idx] |= 3;
+               track->db_dirty = true;
+               break;
        case SQ_PGM_START_FS:
        case SQ_PGM_START_ES:
        case SQ_PGM_START_VS:
@@ -1192,7 +1354,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
        case SQ_ALU_CONST_CACHE_VS_13:
        case SQ_ALU_CONST_CACHE_VS_14:
        case SQ_ALU_CONST_CACHE_VS_15:
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
                                        "0x%04X\n", reg);
@@ -1201,7 +1363,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
                ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                break;
        case SX_MEMORY_EXPORT_BASE:
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONFIG_REG "
                                        "0x%04X\n", reg);
@@ -1209,6 +1371,9 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
                }
                ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                break;
+       case SX_MISC:
+               track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
+               break;
        default:
                dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
                return -EINVAL;
@@ -1216,7 +1381,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
        return 0;
 }
 
-static inline unsigned mip_minify(unsigned size, unsigned level)
+unsigned r600_mip_minify(unsigned size, unsigned level)
 {
        unsigned val;
 
@@ -1227,7 +1392,7 @@ static inline unsigned mip_minify(unsigned size, unsigned level)
 }
 
 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
-                             unsigned w0, unsigned h0, unsigned d0, unsigned format,
+                             unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,
                              unsigned block_align, unsigned height_align, unsigned base_align,
                              unsigned *l0_size, unsigned *mipmap_size)
 {
@@ -1238,24 +1403,24 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
        unsigned nlevels = llevel - blevel + 1;
 
        *l0_size = -1;
-       blocksize = fmt_get_blocksize(format);
+       blocksize = r600_fmt_get_blocksize(format);
 
-       w0 = mip_minify(w0, 0);
-       h0 = mip_minify(h0, 0);
-       d0 = mip_minify(d0, 0);
+       w0 = r600_mip_minify(w0, 0);
+       h0 = r600_mip_minify(h0, 0);
+       d0 = r600_mip_minify(d0, 0);
        for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
-               width = mip_minify(w0, i);
-               nbx = fmt_get_nblocksx(format, width);
+               width = r600_mip_minify(w0, i);
+               nbx = r600_fmt_get_nblocksx(format, width);
 
                nbx = round_up(nbx, block_align);
 
-               height = mip_minify(h0, i);
-               nby = fmt_get_nblocksy(format, height);
+               height = r600_mip_minify(h0, i);
+               nby = r600_fmt_get_nblocksy(format, height);
                nby = round_up(nby, height_align);
 
-               depth = mip_minify(d0, i);
+               depth = r600_mip_minify(d0, i);
 
-               size = nbx * nby * blocksize;
+               size = nbx * nby * blocksize * nsamples;
                if (nfaces)
                        size *= nfaces;
                else
@@ -1286,7 +1451,7 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
  * This function will check that the resource has valid field and that
  * the texture and mipmap bo object are big enough to cover this resource.
  */
-static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
+static int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
                                              struct radeon_bo *texture,
                                              struct radeon_bo *mipmap,
                                              u64 base_offset,
@@ -1294,13 +1459,14 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 i
                                              u32 tiling_flags)
 {
        struct r600_cs_track *track = p->track;
-       u32 nfaces, llevel, blevel, w0, h0, d0;
-       u32 word0, word1, l0_size, mipmap_size, word2, word3;
+       u32 dim, nfaces, llevel, blevel, w0, h0, d0;
+       u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
        u32 height_align, pitch, pitch_align, depth_align;
-       u32 array, barray, larray;
+       u32 barray, larray;
        u64 base_align;
        struct array_mode_checker array_check;
        u32 format;
+       bool is_array;
 
        /* on legacy kernel we don't perform advanced check */
        if (p->rdev == NULL)
@@ -1311,16 +1477,35 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 i
        mip_offset <<= 8;
 
        word0 = radeon_get_ib_value(p, idx + 0);
-       if (tiling_flags & RADEON_TILING_MACRO)
-               word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
-       else if (tiling_flags & RADEON_TILING_MICRO)
-               word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+       if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
+               if (tiling_flags & RADEON_TILING_MACRO)
+                       word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
+               else if (tiling_flags & RADEON_TILING_MICRO)
+                       word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+       }
        word1 = radeon_get_ib_value(p, idx + 1);
+       word2 = radeon_get_ib_value(p, idx + 2) << 8;
+       word3 = radeon_get_ib_value(p, idx + 3) << 8;
+       word4 = radeon_get_ib_value(p, idx + 4);
+       word5 = radeon_get_ib_value(p, idx + 5);
+       dim = G_038000_DIM(word0);
        w0 = G_038000_TEX_WIDTH(word0) + 1;
+       pitch = (G_038000_PITCH(word0) + 1) * 8;
        h0 = G_038004_TEX_HEIGHT(word1) + 1;
        d0 = G_038004_TEX_DEPTH(word1);
+       format = G_038004_DATA_FORMAT(word1);
+       blevel = G_038010_BASE_LEVEL(word4);
+       llevel = G_038014_LAST_LEVEL(word5);
+       /* pitch in texels */
+       array_check.array_mode = G_038000_TILE_MODE(word0);
+       array_check.group_size = track->group_size;
+       array_check.nbanks = track->nbanks;
+       array_check.npipes = track->npipes;
+       array_check.nsamples = 1;
+       array_check.blocksize = r600_fmt_get_blocksize(format);
        nfaces = 1;
-       switch (G_038000_DIM(word0)) {
+       is_array = false;
+       switch (dim) {
        case V_038000_SQ_TEX_DIM_1D:
        case V_038000_SQ_TEX_DIM_2D:
        case V_038000_SQ_TEX_DIM_3D:
@@ -1333,29 +1518,25 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 i
                break;
        case V_038000_SQ_TEX_DIM_1D_ARRAY:
        case V_038000_SQ_TEX_DIM_2D_ARRAY:
-               array = 1;
+               is_array = true;
                break;
-       case V_038000_SQ_TEX_DIM_2D_MSAA:
        case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
+               is_array = true;
+               /* fall through */
+       case V_038000_SQ_TEX_DIM_2D_MSAA:
+               array_check.nsamples = 1 << llevel;
+               llevel = 0;
+               break;
        default:
                dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
                return -EINVAL;
        }
-       format = G_038004_DATA_FORMAT(word1);
-       if (!fmt_is_valid_texture(format, p->family)) {
+       if (!r600_fmt_is_valid_texture(format, p->family)) {
                dev_warn(p->dev, "%s:%d texture invalid format %d\n",
                         __func__, __LINE__, format);
                return -EINVAL;
        }
 
-       /* pitch in texels */
-       pitch = (G_038000_PITCH(word0) + 1) * 8;
-       array_check.array_mode = G_038000_TILE_MODE(word0);
-       array_check.group_size = track->group_size;
-       array_check.nbanks = track->nbanks;
-       array_check.npipes = track->npipes;
-       array_check.nsamples = 1;
-       array_check.blocksize = fmt_get_blocksize(format);
        if (r600_get_array_mode_alignment(&array_check,
                                          &pitch_align, &height_align, &depth_align, &base_align)) {
                dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
@@ -1381,31 +1562,29 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 i
                return -EINVAL;
        }
 
-       word2 = radeon_get_ib_value(p, idx + 2) << 8;
-       word3 = radeon_get_ib_value(p, idx + 3) << 8;
-
-       word0 = radeon_get_ib_value(p, idx + 4);
-       word1 = radeon_get_ib_value(p, idx + 5);
-       blevel = G_038010_BASE_LEVEL(word0);
-       llevel = G_038014_LAST_LEVEL(word1);
-       if (array == 1) {
-               barray = G_038014_BASE_ARRAY(word1);
-               larray = G_038014_LAST_ARRAY(word1);
+       if (blevel > llevel) {
+               dev_warn(p->dev, "texture blevel %d > llevel %d\n",
+                        blevel, llevel);
+       }
+       if (is_array) {
+               barray = G_038014_BASE_ARRAY(word5);
+               larray = G_038014_LAST_ARRAY(word5);
 
                nfaces = larray - barray + 1;
        }
-       r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format,
+       r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,
                          pitch_align, height_align, base_align,
                          &l0_size, &mipmap_size);
        /* using get ib will give us the offset into the texture bo */
        if ((l0_size + word2) > radeon_bo_size(texture)) {
-               dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
-                       w0, h0, format, word2, l0_size, radeon_bo_size(texture));
+               dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
+                        w0, h0, pitch_align, height_align,
+                        array_check.array_mode, format, word2,
+                        l0_size, radeon_bo_size(texture));
                dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
                return -EINVAL;
        }
        /* using get ib will give us the offset into the mipmap bo */
-       word3 = radeon_get_ib_value(p, idx + 3) << 8;
        if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
                /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
                  w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
@@ -1413,6 +1592,22 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 i
        return 0;
 }
 
+static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
+{
+       u32 m, i;
+
+       i = (reg >> 7);
+       if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
+               dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
+               return false;
+       }
+       m = 1 << ((reg >> 2) & 31);
+       if (!(r600_reg_safe_bm[i] & m))
+               return true;
+       dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
+       return false;
+}
+
 static int r600_packet3_check(struct radeon_cs_parser *p,
                                struct radeon_cs_packet *pkt)
 {
@@ -1426,7 +1621,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
        u32 idx_value;
 
        track = (struct r600_cs_track *)p->track;
-       ib = p->ib->ptr;
+       ib = p->ib.ptr;
        idx = pkt->idx + 1;
        idx_value = radeon_get_ib_value(p, idx);
 
@@ -1435,6 +1630,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
        {
                int pred_op;
                int tmp;
+               uint64_t offset;
+
                if (pkt->count != 1) {
                        DRM_ERROR("bad SET PREDICATION\n");
                        return -EINVAL;
@@ -1452,14 +1649,18 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
 
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        DRM_ERROR("bad SET PREDICATION\n");
                        return -EINVAL;
                }
 
-               ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
-               ib[idx + 1] = tmp + (upper_32_bits(reloc->lobj.gpu_offset) & 0xff);
+               offset = reloc->lobj.gpu_offset +
+                        (idx_value & 0xfffffff0) +
+                        ((u64)(tmp & 0xff) << 32);
+
+               ib[idx + 0] = offset;
+               ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
        }
        break;
 
@@ -1483,23 +1684,32 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                }
                break;
        case PACKET3_DRAW_INDEX:
+       {
+               uint64_t offset;
                if (pkt->count != 3) {
                        DRM_ERROR("bad DRAW_INDEX\n");
                        return -EINVAL;
                }
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        DRM_ERROR("bad DRAW_INDEX\n");
                        return -EINVAL;
                }
-               ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
-               ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+
+               offset = reloc->lobj.gpu_offset +
+                        idx_value +
+                        ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
+
+               ib[idx+0] = offset;
+               ib[idx+1] = upper_32_bits(offset) & 0xff;
+
                r = r600_cs_track_check(p);
                if (r) {
                        dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
                        return r;
                }
                break;
+       }
        case PACKET3_DRAW_INDEX_AUTO:
                if (pkt->count != 1) {
                        DRM_ERROR("bad DRAW_INDEX_AUTO\n");
@@ -1530,15 +1740,97 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                }
                /* bit 4 is reg (0) or mem (1) */
                if (idx_value & 0x10) {
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       uint64_t offset;
+
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad WAIT_REG_MEM\n");
                                return -EINVAL;
                        }
-                       ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
-                       ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+
+                       offset = reloc->lobj.gpu_offset +
+                                (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
+                                ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
+
+                       ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
+                       ib[idx+2] = upper_32_bits(offset) & 0xff;
+               } else if (idx_value & 0x100) {
+                       DRM_ERROR("cannot use PFP on REG wait\n");
+                       return -EINVAL;
                }
                break;
+       case PACKET3_CP_DMA:
+       {
+               u32 command, size;
+               u64 offset, tmp;
+               if (pkt->count != 4) {
+                       DRM_ERROR("bad CP DMA\n");
+                       return -EINVAL;
+               }
+               command = radeon_get_ib_value(p, idx+4);
+               size = command & 0x1fffff;
+               if (command & PACKET3_CP_DMA_CMD_SAS) {
+                       /* src address space is register */
+                       DRM_ERROR("CP DMA SAS not supported\n");
+                       return -EINVAL;
+               } else {
+                       if (command & PACKET3_CP_DMA_CMD_SAIC) {
+                               DRM_ERROR("CP DMA SAIC only supported for registers\n");
+                               return -EINVAL;
+                       }
+                       /* src address space is memory */
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
+                       if (r) {
+                               DRM_ERROR("bad CP DMA SRC\n");
+                               return -EINVAL;
+                       }
+
+                       tmp = radeon_get_ib_value(p, idx) +
+                               ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
+
+                       offset = reloc->lobj.gpu_offset + tmp;
+
+                       if ((tmp + size) > radeon_bo_size(reloc->robj)) {
+                               dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",
+                                        tmp + size, radeon_bo_size(reloc->robj));
+                               return -EINVAL;
+                       }
+
+                       ib[idx] = offset;
+                       ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
+               }
+               if (command & PACKET3_CP_DMA_CMD_DAS) {
+                       /* dst address space is register */
+                       DRM_ERROR("CP DMA DAS not supported\n");
+                       return -EINVAL;
+               } else {
+                       /* dst address space is memory */
+                       if (command & PACKET3_CP_DMA_CMD_DAIC) {
+                               DRM_ERROR("CP DMA DAIC only supported for registers\n");
+                               return -EINVAL;
+                       }
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
+                       if (r) {
+                               DRM_ERROR("bad CP DMA DST\n");
+                               return -EINVAL;
+                       }
+
+                       tmp = radeon_get_ib_value(p, idx+2) +
+                               ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
+
+                       offset = reloc->lobj.gpu_offset + tmp;
+
+                       if ((tmp + size) > radeon_bo_size(reloc->robj)) {
+                               dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",
+                                        tmp + size, radeon_bo_size(reloc->robj));
+                               return -EINVAL;
+                       }
+
+                       ib[idx+2] = offset;
+                       ib[idx+3] = upper_32_bits(offset) & 0xff;
+               }
+               break;
+       }
        case PACKET3_SURFACE_SYNC:
                if (pkt->count != 3) {
                        DRM_ERROR("bad SURFACE_SYNC\n");
@@ -1547,7 +1839,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                /* 0xffffffff/0x0 is flush all cache flag */
                if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
                    radeon_get_ib_value(p, idx + 2) != 0) {
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad SURFACE_SYNC\n");
                                return -EINVAL;
@@ -1561,28 +1853,43 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
                if (pkt->count) {
-                       r = r600_cs_packet_next_reloc(p, &reloc);
+                       uint64_t offset;
+
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                        if (r) {
                                DRM_ERROR("bad EVENT_WRITE\n");
                                return -EINVAL;
                        }
-                       ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
-                       ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+                       offset = reloc->lobj.gpu_offset +
+                                (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
+                                ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
+
+                       ib[idx+1] = offset & 0xfffffff8;
+                       ib[idx+2] = upper_32_bits(offset) & 0xff;
                }
                break;
        case PACKET3_EVENT_WRITE_EOP:
+       {
+               uint64_t offset;
+
                if (pkt->count != 4) {
                        DRM_ERROR("bad EVENT_WRITE_EOP\n");
                        return -EINVAL;
                }
-               r = r600_cs_packet_next_reloc(p, &reloc);
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                if (r) {
                        DRM_ERROR("bad EVENT_WRITE\n");
                        return -EINVAL;
                }
-               ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
-               ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+
+               offset = reloc->lobj.gpu_offset +
+                        (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
+                        ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
+
+               ib[idx+1] = offset & 0xfffffffc;
+               ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
                break;
+       }
        case PACKET3_SET_CONFIG_REG:
                start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
                end_reg = 4 * pkt->count + start_reg - 4;
@@ -1635,19 +1942,21 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
                        case SQ_TEX_VTX_VALID_TEXTURE:
                                /* tex base */
-                               r = r600_cs_packet_next_reloc(p, &reloc);
+                               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                                if (r) {
                                        DRM_ERROR("bad SET_RESOURCE\n");
                                        return -EINVAL;
                                }
                                base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
-                               if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
-                                       ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
-                               else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
-                                       ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+                               if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
+                                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                                               ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
+                                       else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                                               ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+                               }
                                texture = reloc->robj;
                                /* tex mip base */
-                               r = r600_cs_packet_next_reloc(p, &reloc);
+                               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                                if (r) {
                                        DRM_ERROR("bad SET_RESOURCE\n");
                                        return -EINVAL;
@@ -1665,8 +1974,10 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                ib[idx+1+(i*7)+3] += mip_offset;
                                break;
                        case SQ_TEX_VTX_VALID_BUFFER:
+                       {
+                               uint64_t offset64;
                                /* vtx base */
-                               r = r600_cs_packet_next_reloc(p, &reloc);
+                               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
                                if (r) {
                                        DRM_ERROR("bad SET_RESOURCE\n");
                                        return -EINVAL;
@@ -1677,11 +1988,15 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                        /* force size to size of the buffer */
                                        dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
                                                 size + offset, radeon_bo_size(reloc->robj));
-                                       ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
+                                       ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
                                }
-                               ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
-                               ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+
+                               offset64 = reloc->lobj.gpu_offset + offset;
+                               ib[idx+1+(i*8)+0] = offset64;
+                               ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
+                                                   (upper_32_bits(offset64) & 0xff);
                                break;
+                       }
                        case SQ_TEX_VTX_INVALID_TEXTURE:
                        case SQ_TEX_VTX_INVALID_BUFFER:
                        default:
@@ -1746,6 +2061,49 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
                break;
+       case PACKET3_STRMOUT_BASE_UPDATE:
+               /* RS780 and RS880 also need this */
+               if (p->family < CHIP_RS780) {
+                       DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
+                       return -EINVAL;
+               }
+               if (pkt->count != 1) {
+                       DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
+                       return -EINVAL;
+               }
+               if (idx_value > 3) {
+                       DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
+                       return -EINVAL;
+               }
+               {
+                       u64 offset;
+
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
+                       if (r) {
+                               DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
+                               return -EINVAL;
+                       }
+
+                       if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
+                               DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
+                               return -EINVAL;
+                       }
+
+                       offset = radeon_get_ib_value(p, idx+1) << 8;
+                       if (offset != track->vgt_strmout_bo_offset[idx_value]) {
+                               DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
+                                         offset, track->vgt_strmout_bo_offset[idx_value]);
+                               return -EINVAL;
+                       }
+
+                       if ((offset + 4) > radeon_bo_size(reloc->robj)) {
+                               DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
+                                         offset + 4, radeon_bo_size(reloc->robj));
+                               return -EINVAL;
+                       }
+                       ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+               }
+               break;
        case PACKET3_SURFACE_BASE_UPDATE:
                if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
                        DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
@@ -1756,6 +2114,133 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
                break;
+       case PACKET3_STRMOUT_BUFFER_UPDATE:
+               if (pkt->count != 4) {
+                       DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
+                       return -EINVAL;
+               }
+               /* Updating memory at DST_ADDRESS. */
+               if (idx_value & 0x1) {
+                       u64 offset;
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
+                       if (r) {
+                               DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
+                               return -EINVAL;
+                       }
+                       offset = radeon_get_ib_value(p, idx+1);
+                       offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
+                       if ((offset + 4) > radeon_bo_size(reloc->robj)) {
+                               DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
+                                         offset + 4, radeon_bo_size(reloc->robj));
+                               return -EINVAL;
+                       }
+                       offset += reloc->lobj.gpu_offset;
+                       ib[idx+1] = offset;
+                       ib[idx+2] = upper_32_bits(offset) & 0xff;
+               }
+               /* Reading data from SRC_ADDRESS. */
+               if (((idx_value >> 1) & 0x3) == 2) {
+                       u64 offset;
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
+                       if (r) {
+                               DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
+                               return -EINVAL;
+                       }
+                       offset = radeon_get_ib_value(p, idx+3);
+                       offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
+                       if ((offset + 4) > radeon_bo_size(reloc->robj)) {
+                               DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
+                                         offset + 4, radeon_bo_size(reloc->robj));
+                               return -EINVAL;
+                       }
+                       offset += reloc->lobj.gpu_offset;
+                       ib[idx+3] = offset;
+                       ib[idx+4] = upper_32_bits(offset) & 0xff;
+               }
+               break;
+       case PACKET3_MEM_WRITE:
+       {
+               u64 offset;
+
+               if (pkt->count != 3) {
+                       DRM_ERROR("bad MEM_WRITE (invalid count)\n");
+                       return -EINVAL;
+               }
+               r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
+               if (r) {
+                       DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
+                       return -EINVAL;
+               }
+               offset = radeon_get_ib_value(p, idx+0);
+               offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
+               if (offset & 0x7) {
+                       DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
+                       return -EINVAL;
+               }
+               if ((offset + 8) > radeon_bo_size(reloc->robj)) {
+                       DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",
+                                 offset + 8, radeon_bo_size(reloc->robj));
+                       return -EINVAL;
+               }
+               offset += reloc->lobj.gpu_offset;
+               ib[idx+0] = offset;
+               ib[idx+1] = upper_32_bits(offset) & 0xff;
+               break;
+       }
+       case PACKET3_COPY_DW:
+               if (pkt->count != 4) {
+                       DRM_ERROR("bad COPY_DW (invalid count)\n");
+                       return -EINVAL;
+               }
+               if (idx_value & 0x1) {
+                       u64 offset;
+                       /* SRC is memory. */
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
+                       if (r) {
+                               DRM_ERROR("bad COPY_DW (missing src reloc)\n");
+                               return -EINVAL;
+                       }
+                       offset = radeon_get_ib_value(p, idx+1);
+                       offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
+                       if ((offset + 4) > radeon_bo_size(reloc->robj)) {
+                               DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
+                                         offset + 4, radeon_bo_size(reloc->robj));
+                               return -EINVAL;
+                       }
+                       offset += reloc->lobj.gpu_offset;
+                       ib[idx+1] = offset;
+                       ib[idx+2] = upper_32_bits(offset) & 0xff;
+               } else {
+                       /* SRC is a reg. */
+                       reg = radeon_get_ib_value(p, idx+1) << 2;
+                       if (!r600_is_safe_reg(p, reg, idx+1))
+                               return -EINVAL;
+               }
+               if (idx_value & 0x2) {
+                       u64 offset;
+                       /* DST is memory. */
+                       r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
+                       if (r) {
+                               DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
+                               return -EINVAL;
+                       }
+                       offset = radeon_get_ib_value(p, idx+3);
+                       offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
+                       if ((offset + 4) > radeon_bo_size(reloc->robj)) {
+                               DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
+                                         offset + 4, radeon_bo_size(reloc->robj));
+                               return -EINVAL;
+                       }
+                       offset += reloc->lobj.gpu_offset;
+                       ib[idx+3] = offset;
+                       ib[idx+4] = upper_32_bits(offset) & 0xff;
+               } else {
+                       /* DST is a reg. */
+                       reg = radeon_get_ib_value(p, idx+3) << 2;
+                       if (!r600_is_safe_reg(p, reg, idx+3))
+                               return -EINVAL;
+               }
+               break;
        case PACKET3_NOP:
                break;
        default:
@@ -1789,7 +2274,7 @@ int r600_cs_parse(struct radeon_cs_parser *p)
                p->track = track;
        }
        do {
-               r = r600_cs_packet_parse(p, &pkt, p->idx);
+               r = radeon_cs_packet_parse(p, &pkt, p->idx);
                if (r) {
                        kfree(p->track);
                        p->track = NULL;
@@ -1797,12 +2282,12 @@ int r600_cs_parse(struct radeon_cs_parser *p)
                }
                p->idx += pkt.count + 2;
                switch (pkt.type) {
-               case PACKET_TYPE0:
+               case RADEON_PACKET_TYPE0:
                        r = r600_cs_parse_packet0(p, &pkt);
                        break;
-               case PACKET_TYPE2:
+               case RADEON_PACKET_TYPE2:
                        break;
-               case PACKET_TYPE3:
+               case RADEON_PACKET_TYPE3:
                        r = r600_packet3_check(p, &pkt);
                        break;
                default:
@@ -1818,8 +2303,8 @@ int r600_cs_parse(struct radeon_cs_parser *p)
                }
        } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
 #if 0
-       for (r = 0; r < p->ib->length_dw; r++) {
-               printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
+       for (r = 0; r < p->ib.length_dw; r++) {
+               printk(KERN_INFO "%05d  0x%08X\n", r, p->ib.ptr[r]);
                mdelay(1);
        }
 #endif
@@ -1828,17 +2313,7 @@ int r600_cs_parse(struct radeon_cs_parser *p)
        return 0;
 }
 
-static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
-{
-       if (p->chunk_relocs_idx == -1) {
-               return 0;
-       }
-       p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
-       if (p->relocs == NULL) {
-               return -ENOMEM;
-       }
-       return 0;
-}
+#ifdef CONFIG_DRM_RADEON_UMS
 
 /**
  * cs_parser_fini() - clean parser states
@@ -1855,19 +2330,32 @@ static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
        kfree(parser->relocs);
        for (i = 0; i < parser->nchunks; i++) {
                kfree(parser->chunks[i].kdata);
-               kfree(parser->chunks[i].kpage[0]);
-               kfree(parser->chunks[i].kpage[1]);
+               if (parser->rdev && (parser->rdev->flags & RADEON_IS_AGP)) {
+                       kfree(parser->chunks[i].kpage[0]);
+                       kfree(parser->chunks[i].kpage[1]);
+               }
        }
        kfree(parser->chunks);
        kfree(parser->chunks_array);
 }
 
+static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
+{
+       if (p->chunk_relocs_idx == -1) {
+               return 0;
+       }
+       p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
+       if (p->relocs == NULL) {
+               return -ENOMEM;
+       }
+       return 0;
+}
+
 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
                        unsigned family, u32 *ib, int *l)
 {
        struct radeon_cs_parser parser;
        struct radeon_cs_chunk *ib_chunk;
-       struct radeon_ib fake_ib;
        struct r600_cs_track *track;
        int r;
 
@@ -1883,9 +2371,8 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
        parser.dev = &dev->pdev->dev;
        parser.rdev = NULL;
        parser.family = family;
-       parser.ib = &fake_ib;
        parser.track = track;
-       fake_ib.ptr = ib;
+       parser.ib.ptr = ib;
        r = radeon_cs_parser_init(&parser, data);
        if (r) {
                DRM_ERROR("Failed to initialize parser !\n");
@@ -1902,8 +2389,8 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
         * input memory (cached) and write to the IB (which can be
         * uncached). */
        ib_chunk = &parser.chunks[parser.chunk_ib_idx];
-       parser.ib->length_dw = ib_chunk->length_dw;
-       *l = parser.ib->length_dw;
+       parser.ib.length_dw = ib_chunk->length_dw;
+       *l = parser.ib.length_dw;
        r = r600_cs_parse(&parser);
        if (r) {
                DRM_ERROR("Invalid command stream !\n");
@@ -1922,5 +2409,213 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
 
 void r600_cs_legacy_init(void)
 {
-       r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
+       r600_nomm = 1;
+}
+
+#endif
+
+/*
+ *  DMA
+ */
+/**
+ * r600_dma_cs_next_reloc() - parse next reloc
+ * @p:         parser structure holding parsing context.
+ * @cs_reloc:          reloc informations
+ *
+ * Return the next reloc, do bo validation and compute
+ * GPU offset using the provided start.
+ **/
+int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
+                          struct radeon_cs_reloc **cs_reloc)
+{
+       struct radeon_cs_chunk *relocs_chunk;
+       unsigned idx;
+
+       *cs_reloc = NULL;
+       if (p->chunk_relocs_idx == -1) {
+               DRM_ERROR("No relocation chunk !\n");
+               return -EINVAL;
+       }
+       relocs_chunk = &p->chunks[p->chunk_relocs_idx];
+       idx = p->dma_reloc_idx;
+       if (idx >= p->nrelocs) {
+               DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
+                         idx, p->nrelocs);
+               return -EINVAL;
+       }
+       *cs_reloc = p->relocs_ptr[idx];
+       p->dma_reloc_idx++;
+       return 0;
+}
+
+#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
+#define GET_DMA_COUNT(h) ((h) & 0x0000ffff)
+#define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
+
+/**
+ * r600_dma_cs_parse() - parse the DMA IB
+ * @p:         parser structure holding parsing context.
+ *
+ * Parses the DMA IB from the CS ioctl and updates
+ * the GPU addresses based on the reloc information and
+ * checks for errors. (R6xx-R7xx)
+ * Returns 0 for success and an error on failure.
+ **/
+int r600_dma_cs_parse(struct radeon_cs_parser *p)
+{
+       struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
+       struct radeon_cs_reloc *src_reloc, *dst_reloc;
+       u32 header, cmd, count, tiled;
+       volatile u32 *ib = p->ib.ptr;
+       u32 idx, idx_value;
+       u64 src_offset, dst_offset;
+       int r;
+
+       do {
+               if (p->idx >= ib_chunk->length_dw) {
+                       DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
+                                 p->idx, ib_chunk->length_dw);
+                       return -EINVAL;
+               }
+               idx = p->idx;
+               header = radeon_get_ib_value(p, idx);
+               cmd = GET_DMA_CMD(header);
+               count = GET_DMA_COUNT(header);
+               tiled = GET_DMA_T(header);
+
+               switch (cmd) {
+               case DMA_PACKET_WRITE:
+                       r = r600_dma_cs_next_reloc(p, &dst_reloc);
+                       if (r) {
+                               DRM_ERROR("bad DMA_PACKET_WRITE\n");
+                               return -EINVAL;
+                       }
+                       if (tiled) {
+                               dst_offset = radeon_get_ib_value(p, idx+1);
+                               dst_offset <<= 8;
+
+                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
+                               p->idx += count + 5;
+                       } else {
+                               dst_offset = radeon_get_ib_value(p, idx+1);
+                               dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
+
+                               ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
+                               ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
+                               p->idx += count + 3;
+                       }
+                       if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
+                               dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n",
+                                        dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
+                               return -EINVAL;
+                       }
+                       break;
+               case DMA_PACKET_COPY:
+                       r = r600_dma_cs_next_reloc(p, &src_reloc);
+                       if (r) {
+                               DRM_ERROR("bad DMA_PACKET_COPY\n");
+                               return -EINVAL;
+                       }
+                       r = r600_dma_cs_next_reloc(p, &dst_reloc);
+                       if (r) {
+                               DRM_ERROR("bad DMA_PACKET_COPY\n");
+                               return -EINVAL;
+                       }
+                       if (tiled) {
+                               idx_value = radeon_get_ib_value(p, idx + 2);
+                               /* detile bit */
+                               if (idx_value & (1 << 31)) {
+                                       /* tiled src, linear dst */
+                                       src_offset = radeon_get_ib_value(p, idx+1);
+                                       src_offset <<= 8;
+                                       ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
+
+                                       dst_offset = radeon_get_ib_value(p, idx+5);
+                                       dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
+                                       ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
+                                       ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
+                               } else {
+                                       /* linear src, tiled dst */
+                                       src_offset = radeon_get_ib_value(p, idx+5);
+                                       src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
+                                       ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
+                                       ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+
+                                       dst_offset = radeon_get_ib_value(p, idx+1);
+                                       dst_offset <<= 8;
+                                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
+                               }
+                               p->idx += 7;
+                       } else {
+                               if (p->family >= CHIP_RV770) {
+                                       src_offset = radeon_get_ib_value(p, idx+2);
+                                       src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
+                                       dst_offset = radeon_get_ib_value(p, idx+1);
+                                       dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
+
+                                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
+                                       ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
+                                       ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                                       p->idx += 5;
+                               } else {
+                                       src_offset = radeon_get_ib_value(p, idx+2);
+                                       src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
+                                       dst_offset = radeon_get_ib_value(p, idx+1);
+                                       dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;
+
+                                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
+                                       ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
+                                       ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
+                                       ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16;
+                                       p->idx += 4;
+                               }
+                       }
+                       if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
+                               dev_warn(p->dev, "DMA copy src buffer too small (%llu %lu)\n",
+                                        src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
+                               return -EINVAL;
+                       }
+                       if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
+                               dev_warn(p->dev, "DMA write dst buffer too small (%llu %lu)\n",
+                                        dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
+                               return -EINVAL;
+                       }
+                       break;
+               case DMA_PACKET_CONSTANT_FILL:
+                       if (p->family < CHIP_RV770) {
+                               DRM_ERROR("Constant Fill is 7xx only !\n");
+                               return -EINVAL;
+                       }
+                       r = r600_dma_cs_next_reloc(p, &dst_reloc);
+                       if (r) {
+                               DRM_ERROR("bad DMA_PACKET_WRITE\n");
+                               return -EINVAL;
+                       }
+                       dst_offset = radeon_get_ib_value(p, idx+1);
+                       dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;
+                       if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
+                               dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",
+                                        dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
+                               return -EINVAL;
+                       }
+                       ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
+                       ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;
+                       p->idx += 4;
+                       break;
+               case DMA_PACKET_NOP:
+                       p->idx += 1;
+                       break;
+               default:
+                       DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
+                       return -EINVAL;
+               }
+       } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
+#if 0
+       for (r = 0; r < p->ib->length_dw; r++) {
+               printk(KERN_INFO "%05d  0x%08X\n", r, p->ib.ptr[r]);
+               mdelay(1);
+       }
+#endif
+       return 0;
 }