drm/nouveau: port all engines to new engine module format
[linux-3.10.git] / drivers / gpu / drm / nouveau / nv50_evo.c
index eea9620..d7d8080 100644 (file)
 
 #include "nouveau_drv.h"
 #include "nouveau_dma.h"
-#include "nouveau_ramht.h"
 #include "nv50_display.h"
 
+static u32
+nv50_evo_rd32(struct nouveau_object *object, u32 addr)
+{
+       void __iomem *iomem = object->oclass->ofuncs->rd08;
+       return ioread32_native(iomem + addr);
+}
+
+static void
+nv50_evo_wr32(struct nouveau_object *object, u32 addr, u32 data)
+{
+       void __iomem *iomem = object->oclass->ofuncs->rd08;
+       iowrite32_native(data, iomem + addr);
+}
+
 static void
 nv50_evo_channel_del(struct nouveau_channel **pevo)
 {
@@ -38,45 +51,52 @@ nv50_evo_channel_del(struct nouveau_channel **pevo)
                return;
        *pevo = NULL;
 
-       nouveau_gpuobj_channel_takedown(evo);
-       nouveau_bo_unmap(evo->pushbuf_bo);
-       nouveau_bo_ref(NULL, &evo->pushbuf_bo);
+       nouveau_bo_unmap(evo->push.buffer);
+       nouveau_bo_ref(NULL, &evo->push.buffer);
 
-       if (evo->user)
-               iounmap(evo->user);
+       if (evo->object)
+               iounmap(evo->object->oclass->ofuncs);
 
        kfree(evo);
 }
 
 int
-nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
-                   u32 tile_flags, u32 magic_flags, u32 offset, u32 limit,
-                   u32 flags5)
+nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 handle, u32 memtype,
+                   u64 base, u64 size, struct nouveau_gpuobj **pobj)
 {
-       struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
-       struct nv50_display *disp = nv50_display(evo->dev);
-       struct nouveau_gpuobj *obj = NULL;
-       int ret;
-
-       ret = nouveau_gpuobj_new(evo->dev, disp->master, 6*4, 32, 0, &obj);
-       if (ret)
-               return ret;
-       obj->engine = NVOBJ_ENGINE_DISPLAY;
-
-       nv_wo32(obj,  0, (tile_flags << 22) | (magic_flags << 16) | class);
-       nv_wo32(obj,  4, limit);
-       nv_wo32(obj,  8, offset);
-       nv_wo32(obj, 12, 0x00000000);
-       nv_wo32(obj, 16, 0x00000000);
-       nv_wo32(obj, 20, flags5);
-       dev_priv->engine.instmem.flush(evo->dev);
-
-       ret = nouveau_ramht_insert(evo, name, obj);
-       nouveau_gpuobj_ref(NULL, &obj);
-       if (ret) {
-               return ret;
+       struct drm_device *dev = evo->fence;
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
+       struct nv50_display *disp = nv50_display(dev);
+       u32 dmao = disp->dmao;
+       u32 hash = disp->hash;
+       u32 flags5;
+
+       if (dev_priv->chipset < 0xc0) {
+               /* not supported on 0x50, specified in format mthd */
+               if (dev_priv->chipset == 0x50)
+                       memtype = 0;
+               flags5 = 0x00010000;
+       } else {
+               if (memtype & 0x80000000)
+                       flags5 = 0x00000000; /* large pages */
+               else
+                       flags5 = 0x00020000;
        }
 
+       nv_wo32(disp->ramin, dmao + 0x00, 0x0019003d | (memtype << 22));
+       nv_wo32(disp->ramin, dmao + 0x04, lower_32_bits(base + size - 1));
+       nv_wo32(disp->ramin, dmao + 0x08, lower_32_bits(base));
+       nv_wo32(disp->ramin, dmao + 0x0c, upper_32_bits(base + size - 1) << 24 |
+                                         upper_32_bits(base));
+       nv_wo32(disp->ramin, dmao + 0x10, 0x00000000);
+       nv_wo32(disp->ramin, dmao + 0x14, flags5);
+
+       nv_wo32(disp->ramin, hash + 0x00, handle);
+       nv_wo32(disp->ramin, hash + 0x04, (evo->handle << 28) | (dmao << 10) |
+                                          evo->handle);
+
+       disp->dmao += 0x20;
+       disp->hash += 0x08;
        return 0;
 }
 
@@ -93,49 +113,52 @@ nv50_evo_channel_new(struct drm_device *dev, int chid,
                return -ENOMEM;
        *pevo = evo;
 
-       evo->id = chid;
-       evo->dev = dev;
+       evo->handle = chid;
+       evo->fence = dev;
        evo->user_get = 4;
        evo->user_put = 0;
 
-       ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
-                            false, true, &evo->pushbuf_bo);
+       ret = nouveau_bo_new(dev, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0, NULL,
+                            &evo->push.buffer);
        if (ret == 0)
-               ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM);
+               ret = nouveau_bo_pin(evo->push.buffer, TTM_PL_FLAG_VRAM);
        if (ret) {
                NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
                nv50_evo_channel_del(pevo);
                return ret;
        }
 
-       ret = nouveau_bo_map(evo->pushbuf_bo);
+       ret = nouveau_bo_map(evo->push.buffer);
        if (ret) {
                NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
                nv50_evo_channel_del(pevo);
                return ret;
        }
 
-       evo->user = ioremap(pci_resource_start(dev->pdev, 0) +
-                           NV50_PDISPLAY_USER(evo->id), PAGE_SIZE);
-       if (!evo->user) {
-               NV_ERROR(dev, "Error mapping EVO control regs.\n");
-               nv50_evo_channel_del(pevo);
-               return -ENOMEM;
-       }
-
-       /* bind primary evo channel's ramht to the channel */
-       if (disp->master && evo != disp->master)
-               nouveau_ramht_ref(disp->master->ramht, &evo->ramht, NULL);
-
+       evo->object = kzalloc(sizeof(*evo->object), GFP_KERNEL);
+#ifdef NOUVEAU_OBJECT_MAGIC
+       evo->object->_magic = NOUVEAU_OBJECT_MAGIC;
+#endif
+       evo->object->parent = nv_object(disp->ramin)->parent;
+       evo->object->engine = nv_object(disp->ramin)->engine;
+       evo->object->oclass =
+               kzalloc(sizeof(*evo->object->oclass), GFP_KERNEL);
+       evo->object->oclass->ofuncs =
+               kzalloc(sizeof(*evo->object->oclass->ofuncs), GFP_KERNEL);
+       evo->object->oclass->ofuncs->rd32 = nv50_evo_rd32;
+       evo->object->oclass->ofuncs->wr32 = nv50_evo_wr32;
+       evo->object->oclass->ofuncs->rd08 =
+               ioremap(pci_resource_start(dev->pdev, 0) +
+                       NV50_PDISPLAY_USER(evo->handle), PAGE_SIZE);
        return 0;
 }
 
 static int
 nv50_evo_channel_init(struct nouveau_channel *evo)
 {
-       struct drm_device *dev = evo->dev;
-       int id = evo->id, ret, i;
-       u64 pushbuf = evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT;
+       struct drm_device *dev = evo->fence;
+       int id = evo->handle, ret, i;
+       u64 pushbuf = evo->push.buffer->bo.offset;
        u32 tmp;
 
        tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
@@ -168,6 +191,7 @@ nv50_evo_channel_init(struct nouveau_channel *evo)
        nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
 
        evo->dma.max = (4096/4) - 2;
+       evo->dma.max &= ~7;
        evo->dma.put = 0;
        evo->dma.cur = evo->dma.put;
        evo->dma.free = evo->dma.max - evo->dma.cur;
@@ -185,8 +209,8 @@ nv50_evo_channel_init(struct nouveau_channel *evo)
 static void
 nv50_evo_channel_fini(struct nouveau_channel *evo)
 {
-       struct drm_device *dev = evo->dev;
-       int id = evo->id;
+       struct drm_device *dev = evo->fence;
+       int id = evo->handle;
 
        nv_mask(dev, 0x610028, 0x00010001 << id, 0x00000000);
        nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000);
@@ -198,115 +222,133 @@ nv50_evo_channel_fini(struct nouveau_channel *evo)
        }
 }
 
-static void
+void
 nv50_evo_destroy(struct drm_device *dev)
 {
        struct nv50_display *disp = nv50_display(dev);
-
-       nouveau_gpuobj_ref(NULL, &disp->ntfy);
+       int i;
+
+       for (i = 0; i < 2; i++) {
+               if (disp->crtc[i].sem.bo) {
+                       nouveau_bo_unmap(disp->crtc[i].sem.bo);
+                       nouveau_bo_ref(NULL, &disp->crtc[i].sem.bo);
+               }
+               nv50_evo_channel_del(&disp->crtc[i].sync);
+       }
        nv50_evo_channel_del(&disp->master);
+       nouveau_gpuobj_ref(NULL, &disp->ramin);
 }
 
-static int
+int
 nv50_evo_create(struct drm_device *dev)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nv50_display *disp = nv50_display(dev);
-       struct nouveau_gpuobj *ramht = NULL;
        struct nouveau_channel *evo;
-       int ret;
-
-       /* create primary evo channel, the one we use for modesetting
-        * purporses
-        */
-       ret = nv50_evo_channel_new(dev, 0, &disp->master);
-       if (ret)
-               return ret;
-       evo = disp->master;
+       int ret, i, j;
 
        /* setup object management on it, any other evo channel will
         * use this also as there's no per-channel support on the
         * hardware
         */
        ret = nouveau_gpuobj_new(dev, NULL, 32768, 65536,
-                                NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
+                                NVOBJ_FLAG_ZERO_ALLOC, &disp->ramin);
        if (ret) {
                NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
                goto err;
        }
 
-       ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
-       if (ret) {
-               NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
+       disp->hash = 0x0000;
+       disp->dmao = 0x1000;
+
+       /* create primary evo channel, the one we use for modesetting
+        * purporses
+        */
+       ret = nv50_evo_channel_new(dev, 0, &disp->master);
+       if (ret)
+               return ret;
+       evo = disp->master;
+
+       ret = nv50_evo_dmaobj_new(disp->master, NvEvoSync, 0x0000,
+                                 disp->ramin->addr + 0x2000, 0x1000, NULL);
+       if (ret)
                goto err;
-       }
 
-       ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
-       if (ret) {
-               NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
+       /* create some default objects for the scanout memtypes we support */
+       ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM, 0x0000,
+                                 0, nvfb_vram_size(dev), NULL);
+       if (ret)
                goto err;
-       }
 
-       ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
-       nouveau_gpuobj_ref(NULL, &ramht);
+       ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM_LP, 0x80000000,
+                                 0, nvfb_vram_size(dev), NULL);
        if (ret)
                goto err;
 
-       /* not sure exactly what this is..
-        *
-        * the first dword of the structure is used by nvidia to wait on
-        * full completion of an EVO "update" command.
-        *
-        * method 0x8c on the master evo channel will fill a lot more of
-        * this structure with some undefined info
-        */
-       ret = nouveau_gpuobj_new(dev, disp->master, 0x1000, 0,
-                                NVOBJ_FLAG_ZERO_ALLOC, &disp->ntfy);
+       ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB32, 0x80000000 |
+                                 (dev_priv->chipset < 0xc0 ? 0x7a : 0xfe),
+                                 0, nvfb_vram_size(dev), NULL);
        if (ret)
                goto err;
 
-       ret = nv50_evo_dmaobj_new(disp->master, 0x3d, NvEvoSync, 0, 0x19,
-                                 disp->ntfy->vinst, disp->ntfy->vinst +
-                                 disp->ntfy->size, 0x00010000);
+       ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB16, 0x80000000 |
+                                 (dev_priv->chipset < 0xc0 ? 0x70 : 0xfe),
+                                 0, nvfb_vram_size(dev), NULL);
        if (ret)
                goto err;
 
-       /* create some default objects for the scanout memtypes we support */
-       if (dev_priv->card_type >= NV_C0) {
-               ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0xfe, 0x19,
-                                         0, 0xffffffff, 0x00000000);
-               if (ret)
-                       goto err;
+       /* create "display sync" channels and other structures we need
+        * to implement page flipping
+        */
+       for (i = 0; i < 2; i++) {
+               struct nv50_display_crtc *dispc = &disp->crtc[i];
+               u64 offset;
 
-               ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
-                                         0, dev_priv->vram_size, 0x00020000);
+               ret = nv50_evo_channel_new(dev, 1 + i, &dispc->sync);
                if (ret)
                        goto err;
 
-               ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19,
-                                         0, dev_priv->vram_size, 0x00000000);
+               ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
+                                    0, 0x0000, NULL, &dispc->sem.bo);
+               if (!ret) {
+                       ret = nouveau_bo_pin(dispc->sem.bo, TTM_PL_FLAG_VRAM);
+                       if (!ret)
+                               ret = nouveau_bo_map(dispc->sem.bo);
+                       if (ret)
+                               nouveau_bo_ref(NULL, &dispc->sem.bo);
+                       offset = dispc->sem.bo->bo.offset;
+               }
+
                if (ret)
                        goto err;
-       } else {
-               ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
-                                         0, 0xffffffff, 0x00010000);
+
+               ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoSync, 0x0000,
+                                         offset, 4096, NULL);
                if (ret)
                        goto err;
 
-               ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19,
-                                         0, 0xffffffff, 0x00010000);
+               ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoVRAM_LP, 0x80000000,
+                                         0, nvfb_vram_size(dev), NULL);
                if (ret)
                        goto err;
 
-               ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
-                                         0, dev_priv->vram_size, 0x00010000);
+               ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB32, 0x80000000 |
+                                         (dev_priv->chipset < 0xc0 ?
+                                         0x7a : 0xfe),
+                                         0, nvfb_vram_size(dev), NULL);
                if (ret)
                        goto err;
 
-               ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19,
-                                         0, dev_priv->vram_size, 0x00010000);
+               ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB16, 0x80000000 |
+                                         (dev_priv->chipset < 0xc0 ?
+                                         0x70 : 0xfe),
+                                         0, nvfb_vram_size(dev), NULL);
                if (ret)
                        goto err;
+
+               for (j = 0; j < 4096; j += 4)
+                       nouveau_bo_wr32(dispc->sem.bo, j / 4, 0x74b1e000);
+               dispc->sem.offset = 0;
        }
 
        return 0;
@@ -320,23 +362,32 @@ int
 nv50_evo_init(struct drm_device *dev)
 {
        struct nv50_display *disp = nv50_display(dev);
-       int ret;
+       int ret, i;
+
+       ret = nv50_evo_channel_init(disp->master);
+       if (ret)
+               return ret;
 
-       if (!disp->master) {
-               ret = nv50_evo_create(dev);
+       for (i = 0; i < 2; i++) {
+               ret = nv50_evo_channel_init(disp->crtc[i].sync);
                if (ret)
                        return ret;
        }
 
-       return nv50_evo_channel_init(disp->master);
+       return 0;
 }
 
 void
 nv50_evo_fini(struct drm_device *dev)
 {
        struct nv50_display *disp = nv50_display(dev);
+       int i;
+
+       for (i = 0; i < 2; i++) {
+               if (disp->crtc[i].sync)
+                       nv50_evo_channel_fini(disp->crtc[i].sync);
+       }
 
        if (disp->master)
                nv50_evo_channel_fini(disp->master);
-       nv50_evo_destroy(dev);
 }