x86: Constify a few items
[linux-3.10.git] / arch / x86 / kernel / hpet.c
index 5c8da2c..da85a8e 100644 (file)
@@ -1,9 +1,11 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
-#include <linux/sysdev.h>
+#include <linux/export.h>
 #include <linux/delay.h>
 #include <linux/errno.h>
+#include <linux/i8253.h>
+#include <linux/slab.h>
 #include <linux/hpet.h>
 #include <linux/init.h>
 #include <linux/cpu.h>
 #include <linux/io.h>
 
 #include <asm/fixmap.h>
-#include <asm/i8253.h>
 #include <asm/hpet.h>
+#include <asm/time.h>
 
 #define HPET_MASK                      CLOCKSOURCE_MASK(32)
-#define HPET_SHIFT                     22
 
 /* FSEC = 10^-15
    NSEC = 10^-9 */
 #define HPET_DEV_FSB_CAP               0x1000
 #define HPET_DEV_PERI_CAP              0x2000
 
-#define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
+#define HPET_MIN_CYCLES                        128
+#define HPET_MIN_PROG_DELTA            (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
 
 /*
  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  */
 unsigned long                          hpet_address;
+u8                                     hpet_blockid; /* OS timer block num */
+u8                                     hpet_msi_disable;
+
 #ifdef CONFIG_PCI_MSI
 static unsigned long                   hpet_num_timers;
 #endif
@@ -47,12 +52,17 @@ struct hpet_dev {
        char                            name[10];
 };
 
-unsigned long hpet_readl(unsigned long a)
+inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
+{
+       return container_of(evtdev, struct hpet_dev, evt);
+}
+
+inline unsigned int hpet_readl(unsigned int a)
 {
        return readl(hpet_virt_address + a);
 }
 
-static inline void hpet_writel(unsigned long d, unsigned long a)
+static inline void hpet_writel(unsigned int d, unsigned int a)
 {
        writel(d, hpet_virt_address + a);
 }
@@ -65,7 +75,7 @@ static inline void hpet_set_mapping(void)
 {
        hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
 #ifdef CONFIG_X86_64
-       __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
+       __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
 #endif
 }
 
@@ -80,14 +90,22 @@ static inline void hpet_clear_mapping(void)
  */
 static int boot_hpet_disable;
 int hpet_force_user;
+static int hpet_verbose;
 
 static int __init hpet_setup(char *str)
 {
-       if (str) {
+       while (str) {
+               char *next = strchr(str, ',');
+
+               if (next)
+                       *next++ = 0;
                if (!strncmp("disable", str, 7))
                        boot_hpet_disable = 1;
                if (!strncmp("force", str, 5))
                        hpet_force_user = 1;
+               if (!strncmp("verbose", str, 7))
+                       hpet_verbose = 1;
+               str = next;
        }
        return 1;
 }
@@ -119,6 +137,43 @@ int is_hpet_enabled(void)
 }
 EXPORT_SYMBOL_GPL(is_hpet_enabled);
 
+static void _hpet_print_config(const char *function, int line)
+{
+       u32 i, timers, l, h;
+       printk(KERN_INFO "hpet: %s(%d):\n", function, line);
+       l = hpet_readl(HPET_ID);
+       h = hpet_readl(HPET_PERIOD);
+       timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
+       printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
+       l = hpet_readl(HPET_CFG);
+       h = hpet_readl(HPET_STATUS);
+       printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
+       l = hpet_readl(HPET_COUNTER);
+       h = hpet_readl(HPET_COUNTER+4);
+       printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
+
+       for (i = 0; i < timers; i++) {
+               l = hpet_readl(HPET_Tn_CFG(i));
+               h = hpet_readl(HPET_Tn_CFG(i)+4);
+               printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
+                      i, l, h);
+               l = hpet_readl(HPET_Tn_CMP(i));
+               h = hpet_readl(HPET_Tn_CMP(i)+4);
+               printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
+                      i, l, h);
+               l = hpet_readl(HPET_Tn_ROUTE(i));
+               h = hpet_readl(HPET_Tn_ROUTE(i)+4);
+               printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
+                      i, l, h);
+       }
+}
+
+#define hpet_print_config()                                    \
+do {                                                           \
+       if (hpet_verbose)                                       \
+               _hpet_print_config(__FUNCTION__, __LINE__);     \
+} while (0)
+
 /*
  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
  * timer 0 and timer 1 in case of RTC emulation.
@@ -127,7 +182,7 @@ EXPORT_SYMBOL_GPL(is_hpet_enabled);
 
 static void hpet_reserve_msi_timers(struct hpet_data *hd);
 
-static void hpet_reserve_platform_timers(unsigned long id)
+static void hpet_reserve_platform_timers(unsigned int id)
 {
        struct hpet __iomem *hpet = hpet_virt_address;
        struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
@@ -165,13 +220,13 @@ static void hpet_reserve_platform_timers(unsigned long id)
 
 }
 #else
-static void hpet_reserve_platform_timers(unsigned long id) { }
+static void hpet_reserve_platform_timers(unsigned int id) { }
 #endif
 
 /*
  * Common hpet info
  */
-static unsigned long hpet_period;
+static unsigned long hpet_freq;
 
 static void hpet_legacy_set_mode(enum clock_event_mode mode,
                          struct clock_event_device *evt);
@@ -186,37 +241,51 @@ static struct clock_event_device hpet_clockevent = {
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
        .set_mode       = hpet_legacy_set_mode,
        .set_next_event = hpet_legacy_next_event,
-       .shift          = 32,
        .irq            = 0,
        .rating         = 50,
 };
 
-static void hpet_start_counter(void)
+static void hpet_stop_counter(void)
 {
        unsigned long cfg = hpet_readl(HPET_CFG);
-
        cfg &= ~HPET_CFG_ENABLE;
        hpet_writel(cfg, HPET_CFG);
+}
+
+static void hpet_reset_counter(void)
+{
        hpet_writel(0, HPET_COUNTER);
        hpet_writel(0, HPET_COUNTER + 4);
+}
+
+static void hpet_start_counter(void)
+{
+       unsigned int cfg = hpet_readl(HPET_CFG);
        cfg |= HPET_CFG_ENABLE;
        hpet_writel(cfg, HPET_CFG);
 }
 
+static void hpet_restart_counter(void)
+{
+       hpet_stop_counter();
+       hpet_reset_counter();
+       hpet_start_counter();
+}
+
 static void hpet_resume_device(void)
 {
        force_hpet_resume();
 }
 
-static void hpet_restart_counter(void)
+static void hpet_resume_counter(struct clocksource *cs)
 {
        hpet_resume_device();
-       hpet_start_counter();
+       hpet_restart_counter();
 }
 
 static void hpet_enable_legacy_int(void)
 {
-       unsigned long cfg = hpet_readl(HPET_CFG);
+       unsigned int cfg = hpet_readl(HPET_CFG);
 
        cfg |= HPET_CFG_LEGACY;
        hpet_writel(cfg, HPET_CFG);
@@ -229,27 +298,12 @@ static void hpet_legacy_clockevent_register(void)
        hpet_enable_legacy_int();
 
        /*
-        * The mult factor is defined as (include/linux/clockchips.h)
-        *  mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
-        * hpet_period is in units of femtoseconds (per cycle), so
-        *  mult/2^shift = cyc/ns = 10^6/hpet_period
-        *  mult = (10^6 * 2^shift)/hpet_period
-        *  mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
-        */
-       hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
-                                     hpet_period, hpet_clockevent.shift);
-       /* Calculate the min / max delta */
-       hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
-                                                          &hpet_clockevent);
-       /* 5 usec minimum reprogramming delta. */
-       hpet_clockevent.min_delta_ns = 5000;
-
-       /*
         * Start hpet with the boot cpu mask and make it
         * global after the IO_APIC has been initialized.
         */
        hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
-       clockevents_register_device(&hpet_clockevent);
+       clockevents_config_and_register(&hpet_clockevent, hpet_freq,
+                                       HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
        global_clock_event = &hpet_clockevent;
        printk(KERN_DEBUG "hpet clockevent registered\n");
 }
@@ -259,29 +313,32 @@ static int hpet_setup_msi_irq(unsigned int irq);
 static void hpet_set_mode(enum clock_event_mode mode,
                          struct clock_event_device *evt, int timer)
 {
-       unsigned long cfg, cmp, now;
+       unsigned int cfg, cmp, now;
        uint64_t delta;
 
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
+               hpet_stop_counter();
                delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
                delta >>= evt->shift;
                now = hpet_readl(HPET_COUNTER);
-               cmp = now + (unsigned long) delta;
+               cmp = now + (unsigned int) delta;
                cfg = hpet_readl(HPET_Tn_CFG(timer));
-               /* Make sure we use edge triggered interrupts */
-               cfg &= ~HPET_TN_LEVEL;
                cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
                       HPET_TN_SETVAL | HPET_TN_32BIT;
                hpet_writel(cfg, HPET_Tn_CFG(timer));
-               /*
-                * The first write after writing TN_SETVAL to the
-                * config register sets the counter value, the second
-                * write sets the period.
-                */
                hpet_writel(cmp, HPET_Tn_CMP(timer));
                udelay(1);
-               hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer));
+               /*
+                * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
+                * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
+                * bit is automatically cleared after the first write.
+                * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
+                * Publication # 24674)
+                */
+               hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
+               hpet_start_counter();
+               hpet_print_config();
                break;
 
        case CLOCK_EVT_MODE_ONESHOT:
@@ -308,6 +365,7 @@ static void hpet_set_mode(enum clock_event_mode mode,
                        irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
                        enable_irq(hdev->irq);
                }
+               hpet_print_config();
                break;
        }
 }
@@ -316,19 +374,37 @@ static int hpet_next_event(unsigned long delta,
                           struct clock_event_device *evt, int timer)
 {
        u32 cnt;
+       s32 res;
 
        cnt = hpet_readl(HPET_COUNTER);
        cnt += (u32) delta;
        hpet_writel(cnt, HPET_Tn_CMP(timer));
 
        /*
-        * We need to read back the CMP register to make sure that
-        * what we wrote hit the chip before we compare it to the
-        * counter.
+        * HPETs are a complete disaster. The compare register is
+        * based on a equal comparison and neither provides a less
+        * than or equal functionality (which would require to take
+        * the wraparound into account) nor a simple count down event
+        * mode. Further the write to the comparator register is
+        * delayed internally up to two HPET clock cycles in certain
+        * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
+        * longer delays. We worked around that by reading back the
+        * compare register, but that required another workaround for
+        * ICH9,10 chips where the first readout after write can
+        * return the old stale value. We already had a minimum
+        * programming delta of 5us enforced, but a NMI or SMI hitting
+        * between the counter readout and the comparator write can
+        * move us behind that point easily. Now instead of reading
+        * the compare register back several times, we make the ETIME
+        * decision based on the following: Return ETIME if the
+        * counter value after the write is less than HPET_MIN_CYCLES
+        * away from the event or if the counter is already ahead of
+        * the event. The minimum programming delta for the generic
+        * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
         */
-       WARN_ON_ONCE((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt);
+       res = (s32)(cnt - hpet_readl(HPET_COUNTER));
 
-       return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
+       return res < HPET_MIN_CYCLES ? -ETIME : 0;
 }
 
 static void hpet_legacy_set_mode(enum clock_event_mode mode,
@@ -351,40 +427,36 @@ static int hpet_legacy_next_event(unsigned long delta,
 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
 static struct hpet_dev *hpet_devs;
 
-void hpet_msi_unmask(unsigned int irq)
+void hpet_msi_unmask(struct irq_data *data)
 {
-       struct hpet_dev *hdev = get_irq_data(irq);
-       unsigned long cfg;
+       struct hpet_dev *hdev = data->handler_data;
+       unsigned int cfg;
 
        /* unmask it */
        cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
-       cfg |= HPET_TN_FSB;
+       cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
        hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 }
 
-void hpet_msi_mask(unsigned int irq)
+void hpet_msi_mask(struct irq_data *data)
 {
-       unsigned long cfg;
-       struct hpet_dev *hdev = get_irq_data(irq);
+       struct hpet_dev *hdev = data->handler_data;
+       unsigned int cfg;
 
        /* mask it */
        cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
-       cfg &= ~HPET_TN_FSB;
+       cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
        hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 }
 
-void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
+void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
 {
-       struct hpet_dev *hdev = get_irq_data(irq);
-
        hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
        hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
 }
 
-void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
+void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
 {
-       struct hpet_dev *hdev = get_irq_data(irq);
-
        msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
        msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
        msg->address_hi = 0;
@@ -406,7 +478,7 @@ static int hpet_msi_next_event(unsigned long delta,
 
 static int hpet_setup_msi_irq(unsigned int irq)
 {
-       if (arch_setup_hpet_msi(irq)) {
+       if (x86_msi.setup_hpet_msi(irq, hpet_blockid)) {
                destroy_irq(irq);
                return -EINVAL;
        }
@@ -417,11 +489,11 @@ static int hpet_assign_irq(struct hpet_dev *dev)
 {
        unsigned int irq;
 
-       irq = create_irq();
+       irq = create_irq_nr(0, -1);
        if (!irq)
                return -EINVAL;
 
-       set_irq_data(irq, dev);
+       irq_set_handler_data(irq, dev);
 
        if (hpet_setup_msi_irq(irq))
                return -EINVAL;
@@ -449,7 +521,8 @@ static int hpet_setup_irq(struct hpet_dev *dev)
 {
 
        if (request_irq(dev->irq, hpet_interrupt_handler,
-                       IRQF_DISABLED|IRQF_NOBALANCING, dev->name, dev))
+                       IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
+                       dev->name, dev))
                return -1;
 
        disable_irq(dev->irq);
@@ -466,7 +539,6 @@ static int hpet_setup_irq(struct hpet_dev *dev)
 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
 {
        struct clock_event_device *evt = &hdev->evt;
-       uint64_t hpet_freq;
 
        WARN_ON(cpu != smp_processor_id());
        if (!(hdev->flags & HPET_DEV_VALID))
@@ -488,24 +560,10 @@ static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
 
        evt->set_mode = hpet_msi_set_mode;
        evt->set_next_event = hpet_msi_next_event;
-       evt->shift = 32;
-
-       /*
-        * The period is a femto seconds value. We need to calculate the
-        * scaled math multiplication factor for nanosecond to hpet tick
-        * conversion.
-        */
-       hpet_freq = 1000000000000000ULL;
-       do_div(hpet_freq, hpet_period);
-       evt->mult = div_sc((unsigned long) hpet_freq,
-                                     NSEC_PER_SEC, evt->shift);
-       /* Calculate the max delta */
-       evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
-       /* 5 usec minimum reprogramming delta. */
-       evt->min_delta_ns = 5000;
-
        evt->cpumask = cpumask_of(hdev->cpu);
-       clockevents_register_device(evt);
+
+       clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
+                                       0x7FFFFFFF);
 }
 
 #ifdef CONFIG_HPET
@@ -522,10 +580,16 @@ static void hpet_msi_capability_lookup(unsigned int start_timer)
        unsigned int num_timers_used = 0;
        int i;
 
+       if (hpet_msi_disable)
+               return;
+
+       if (boot_cpu_has(X86_FEATURE_ARAT))
+               return;
        id = hpet_readl(HPET_ID);
 
        num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
        num_timers++; /* Value read out starts from 0 */
+       hpet_print_config();
 
        hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
        if (!hpet_devs)
@@ -535,7 +599,7 @@ static void hpet_msi_capability_lookup(unsigned int start_timer)
 
        for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
                struct hpet_dev *hdev = &hpet_devs[num_timers_used];
-               unsigned long cfg = hpet_readl(HPET_Tn_CFG(i));
+               unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
 
                /* Only consider HPET timer with MSI support */
                if (!(cfg & HPET_TN_FSB_CAP))
@@ -630,7 +694,7 @@ static int hpet_cpuhp_notify(struct notifier_block *n,
 
        switch (action & 0xf) {
        case CPU_ONLINE:
-               INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work);
+               INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
                init_completion(&work.complete);
                /* FIXME: add schedule_work_on() */
                schedule_delayed_work_on(cpu, &work.work, 0);
@@ -676,28 +740,20 @@ static int hpet_cpuhp_notify(struct notifier_block *n,
 /*
  * Clock source related code
  */
-static cycle_t read_hpet(void)
+static cycle_t read_hpet(struct clocksource *cs)
 {
        return (cycle_t)hpet_readl(HPET_COUNTER);
 }
 
-#ifdef CONFIG_X86_64
-static cycle_t __vsyscall_fn vread_hpet(void)
-{
-       return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
-}
-#endif
-
 static struct clocksource clocksource_hpet = {
        .name           = "hpet",
        .rating         = 250,
        .read           = read_hpet,
        .mask           = HPET_MASK,
-       .shift          = HPET_SHIFT,
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-       .resume         = hpet_restart_counter,
+       .resume         = hpet_resume_counter,
 #ifdef CONFIG_X86_64
-       .vread          = vread_hpet,
+       .archdata       = { .vclock_mode = VCLOCK_HPET },
 #endif
 };
 
@@ -707,10 +763,10 @@ static int hpet_clocksource_register(void)
        cycle_t t1;
 
        /* Start the counter */
-       hpet_start_counter();
+       hpet_restart_counter();
 
        /* Verify whether hpet counter works */
-       t1 = read_hpet();
+       t1 = hpet_readl(HPET_COUNTER);
        rdtscll(start);
 
        /*
@@ -724,34 +780,26 @@ static int hpet_clocksource_register(void)
                rdtscll(now);
        } while ((now - start) < 200000UL);
 
-       if (t1 == read_hpet()) {
+       if (t1 == hpet_readl(HPET_COUNTER)) {
                printk(KERN_WARNING
                       "HPET counter not counting. HPET disabled\n");
                return -ENODEV;
        }
 
-       /*
-        * The definition of mult is (include/linux/clocksource.h)
-        * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
-        * so we first need to convert hpet_period to ns/cyc units:
-        *  mult/2^shift = ns/cyc = hpet_period/10^6
-        *  mult = (hpet_period * 2^shift)/10^6
-        *  mult = (hpet_period << shift)/FSEC_PER_NSEC
-        */
-       clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
-
-       clocksource_register(&clocksource_hpet);
-
+       clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
        return 0;
 }
 
+static u32 *hpet_boot_cfg;
+
 /**
  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
  */
 int __init hpet_enable(void)
 {
-       unsigned long id;
-       int i;
+       u32 hpet_period, cfg, id;
+       u64 freq;
+       unsigned int i, last;
 
        if (!is_hpet_capable())
                return 0;
@@ -789,29 +837,66 @@ int __init hpet_enable(void)
                goto out_nohpet;
 
        /*
+        * The period is a femto seconds value. Convert it to a
+        * frequency.
+        */
+       freq = FSEC_PER_SEC;
+       do_div(freq, hpet_period);
+       hpet_freq = freq;
+
+       /*
         * Read the HPET ID register to retrieve the IRQ routing
         * information and the number of channels
         */
        id = hpet_readl(HPET_ID);
+       hpet_print_config();
+
+       last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
 
 #ifdef CONFIG_HPET_EMULATE_RTC
        /*
         * The legacy routing mode needs at least two channels, tick timer
         * and the rtc emulation channel.
         */
-       if (!(id & HPET_ID_NUMBER))
+       if (!last)
                goto out_nohpet;
 #endif
 
+       cfg = hpet_readl(HPET_CFG);
+       hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
+                               GFP_KERNEL);
+       if (hpet_boot_cfg)
+               *hpet_boot_cfg = cfg;
+       else
+               pr_warn("HPET initial state will not be saved\n");
+       cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
+       hpet_writel(cfg, HPET_CFG);
+       if (cfg)
+               pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
+                       cfg);
+
+       for (i = 0; i <= last; ++i) {
+               cfg = hpet_readl(HPET_Tn_CFG(i));
+               if (hpet_boot_cfg)
+                       hpet_boot_cfg[i + 1] = cfg;
+               cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
+               hpet_writel(cfg, HPET_Tn_CFG(i));
+               cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
+                        | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
+                        | HPET_TN_FSB | HPET_TN_FSB_CAP);
+               if (cfg)
+                       pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
+                               cfg, i);
+       }
+       hpet_print_config();
+
        if (hpet_clocksource_register())
                goto out_nohpet;
 
        if (id & HPET_ID_LEGSUP) {
                hpet_legacy_clockevent_register();
-               hpet_msi_capability_lookup(2);
                return 1;
        }
-       hpet_msi_capability_lookup(0);
        return 0;
 
 out_nohpet:
@@ -844,7 +929,19 @@ static __init int hpet_late_init(void)
        if (!hpet_virt_address)
                return -ENODEV;
 
+       if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
+               hpet_msi_capability_lookup(2);
+       else
+               hpet_msi_capability_lookup(0);
+
        hpet_reserve_platform_timers(hpet_readl(HPET_ID));
+       hpet_print_config();
+
+       if (hpet_msi_disable)
+               return 0;
+
+       if (boot_cpu_has(X86_FEATURE_ARAT))
+               return 0;
 
        for_each_online_cpu(cpu) {
                hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
@@ -859,15 +956,29 @@ fs_initcall(hpet_late_init);
 
 void hpet_disable(void)
 {
-       if (is_hpet_capable()) {
-               unsigned long cfg = hpet_readl(HPET_CFG);
+       if (is_hpet_capable() && hpet_virt_address) {
+               unsigned int cfg = hpet_readl(HPET_CFG), id, last;
 
-               if (hpet_legacy_int_enabled) {
+               if (hpet_boot_cfg)
+                       cfg = *hpet_boot_cfg;
+               else if (hpet_legacy_int_enabled) {
                        cfg &= ~HPET_CFG_LEGACY;
                        hpet_legacy_int_enabled = 0;
                }
                cfg &= ~HPET_CFG_ENABLE;
                hpet_writel(cfg, HPET_CFG);
+
+               if (!hpet_boot_cfg)
+                       return;
+
+               id = hpet_readl(HPET_ID);
+               last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
+
+               for (id = 0; id <= last; ++id)
+                       hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
+
+               if (*hpet_boot_cfg & HPET_CFG_ENABLE)
+                       hpet_writel(*hpet_boot_cfg, HPET_CFG);
        }
 }
 
@@ -899,14 +1010,22 @@ static unsigned long hpet_rtc_flags;
 static int hpet_prev_update_sec;
 static struct rtc_time hpet_alarm_time;
 static unsigned long hpet_pie_count;
-static unsigned long hpet_t1_cmp;
-static unsigned long hpet_default_delta;
-static unsigned long hpet_pie_delta;
+static u32 hpet_t1_cmp;
+static u32 hpet_default_delta;
+static u32 hpet_pie_delta;
 static unsigned long hpet_pie_limit;
 
 static rtc_irq_handler irq_handler;
 
 /*
+ * Check that the hpet counter c1 is ahead of the c2
+ */
+static inline int hpet_cnt_ahead(u32 c1, u32 c2)
+{
+       return (s32)(c2 - c1) < 0;
+}
+
+/*
  * Registers a IRQ handler.
  */
 int hpet_register_irq_handler(rtc_irq_handler handler)
@@ -944,7 +1063,8 @@ EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
  */
 int hpet_rtc_timer_init(void)
 {
-       unsigned long cfg, cnt, delta, flags;
+       unsigned int cfg, cnt, delta;
+       unsigned long flags;
 
        if (!is_hpet_enabled())
                return 0;
@@ -954,7 +1074,7 @@ int hpet_rtc_timer_init(void)
 
                clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
                clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
-               hpet_default_delta = (unsigned long) clc;
+               hpet_default_delta = clc;
        }
 
        if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
@@ -979,6 +1099,14 @@ int hpet_rtc_timer_init(void)
 }
 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
 
+static void hpet_disable_rtc_channel(void)
+{
+       unsigned long cfg;
+       cfg = hpet_readl(HPET_T1_CFG);
+       cfg &= ~HPET_TN_ENABLE;
+       hpet_writel(cfg, HPET_T1_CFG);
+}
+
 /*
  * The functions below are called from rtc driver.
  * Return 0 if HPET is not being used.
@@ -990,6 +1118,9 @@ int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
                return 0;
 
        hpet_rtc_flags &= ~bit_mask;
+       if (unlikely(!hpet_rtc_flags))
+               hpet_disable_rtc_channel();
+
        return 1;
 }
 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
@@ -1040,7 +1171,8 @@ int hpet_set_periodic_freq(unsigned long freq)
                clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
                do_div(clc, freq);
                clc >>= hpet_clockevent.shift;
-               hpet_pie_delta = (unsigned long) clc;
+               hpet_pie_delta = clc;
+               hpet_pie_limit = 0;
        }
        return 1;
 }
@@ -1054,15 +1186,11 @@ EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
 
 static void hpet_rtc_timer_reinit(void)
 {
-       unsigned long cfg, delta;
+       unsigned int delta;
        int lost_ints = -1;
 
-       if (unlikely(!hpet_rtc_flags)) {
-               cfg = hpet_readl(HPET_T1_CFG);
-               cfg &= ~HPET_TN_ENABLE;
-               hpet_writel(cfg, HPET_T1_CFG);
-               return;
-       }
+       if (unlikely(!hpet_rtc_flags))
+               hpet_disable_rtc_channel();
 
        if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
                delta = hpet_default_delta;
@@ -1077,7 +1205,7 @@ static void hpet_rtc_timer_reinit(void)
                hpet_t1_cmp += delta;
                hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
                lost_ints++;
-       } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
+       } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
 
        if (lost_ints) {
                if (hpet_rtc_flags & RTC_PIE)