ARM: 7090/1: CACHE-L2X0: filter start address can be 0 and is often 0
[linux-3.10.git] / arch / arm / mm / tlb-v6.S
index ffe06a6..eca07f5 100644 (file)
@@ -88,9 +88,5 @@ ENTRY(v6wbi_flush_kern_tlb_range)
 
        __INIT
 
-       .type   v6wbi_tlb_fns, #object
-ENTRY(v6wbi_tlb_fns)
-       .long   v6wbi_flush_user_tlb_range
-       .long   v6wbi_flush_kern_tlb_range
-       .long   v6wbi_tlb_flags
-       .size   v6wbi_tlb_fns, . - v6wbi_tlb_fns
+       /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
+       define_tlb_functions v6wbi, v6wbi_tlb_flags