ARM: Add init_consistent_dma_size()
[linux-3.10.git] / arch / arm / mm / proc-arm925.S
index cb53435..51d494b 100644 (file)
@@ -77,7 +77,7 @@
 /*
  * This is the size at which it becomes more efficient to
  * clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
  */
 #define CACHE_DLIMIT   8192
 
@@ -92,15 +92,11 @@ ENTRY(cpu_arm925_proc_init)
  * cpu_arm925_proc_fin()
  */
 ENTRY(cpu_arm925_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm925_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm925_reset(loc)
@@ -149,6 +145,17 @@ ENTRY(cpu_arm925_do_idle)
        mov     pc, lr
 
 /*
+ *     flush_icache_all()
+ *
+ *     Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm925_flush_icache_all)
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+       mov     pc, lr
+ENDPROC(arm925_flush_icache_all)
+
+/*
  *     flush_user_cache_all()
  *
  *     Clean and invalidate all cache entries in a particular
@@ -251,15 +258,16 @@ ENTRY(arm925_coherent_user_range)
        mov     pc, lr
 
 /*
- *     flush_kern_dcache_page(void *page)
+ *     flush_kern_dcache_area(void *addr, size_t size)
  *
  *     Ensure no D cache aliasing occurs, either with itself or
  *     the I cache
  *
- *     - addr  - page aligned address
+ *     - addr  - kernel address
+ *     - size  - region size
  */
-ENTRY(arm925_flush_kern_dcache_page)
-       add     r1, r0, #PAGE_SZ
+ENTRY(arm925_flush_kern_dcache_area)
+       add     r1, r0, r1
 1:     mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
        add     r0, r0, #CACHE_DLINESIZE
        cmp     r0, r1
@@ -282,7 +290,7 @@ ENTRY(arm925_flush_kern_dcache_page)
  *
  * (same as v4wb)
  */
-ENTRY(arm925_dma_inv_range)
+arm925_dma_inv_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
        tst     r0, #CACHE_DLINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -307,7 +315,7 @@ ENTRY(arm925_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm925_dma_clean_range)
+arm925_dma_clean_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -340,16 +348,32 @@ ENTRY(arm925_dma_flush_range)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
 
-ENTRY(arm925_cache_fns)
-       .long   arm925_flush_kern_cache_all
-       .long   arm925_flush_user_cache_all
-       .long   arm925_flush_user_cache_range
-       .long   arm925_coherent_kern_range
-       .long   arm925_coherent_user_range
-       .long   arm925_flush_kern_dcache_page
-       .long   arm925_dma_inv_range
-       .long   arm925_dma_clean_range
-       .long   arm925_dma_flush_range
+/*
+ *     dma_map_area(start, size, dir)
+ *     - start - kernel virtual start address
+ *     - size  - size of region
+ *     - dir   - DMA direction
+ */
+ENTRY(arm925_dma_map_area)
+       add     r1, r1, r0
+       cmp     r2, #DMA_TO_DEVICE
+       beq     arm925_dma_clean_range
+       bcs     arm925_dma_inv_range
+       b       arm925_dma_flush_range
+ENDPROC(arm925_dma_map_area)
+
+/*
+ *     dma_unmap_area(start, size, dir)
+ *     - start - kernel virtual start address
+ *     - size  - size of region
+ *     - dir   - DMA direction
+ */
+ENTRY(arm925_dma_unmap_area)
+       mov     pc, lr
+ENDPROC(arm925_dma_unmap_area)
+
+       @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+       define_cache_functions arm925
 
 ENTRY(cpu_arm925_dcache_clean_area)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -407,7 +431,7 @@ ENTRY(cpu_arm925_set_pte_ext)
 #endif /* CONFIG_MMU */
        mov     pc, lr
 
-       __INIT
+       __CPUINIT
 
        .type   __arm925_setup, #function
 __arm925_setup:
@@ -454,49 +478,24 @@ arm925_crval:
        crval   clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
 
        __INITDATA
-
-/*
- * Purpose : Function pointers used to access above functions - all calls
- *          come through these
- */
-       .type   arm925_processor_functions, #object
-arm925_processor_functions:
-       .word   v4t_early_abort
-       .word   legacy_pabort
-       .word   cpu_arm925_proc_init
-       .word   cpu_arm925_proc_fin
-       .word   cpu_arm925_reset
-       .word   cpu_arm925_do_idle
-       .word   cpu_arm925_dcache_clean_area
-       .word   cpu_arm925_switch_mm
-       .word   cpu_arm925_set_pte_ext
-       .size   arm925_processor_functions, . - arm925_processor_functions
+       @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+       define_processor_functions arm925, dabort=v4t_early_abort, pabort=legacy_pabort
 
        .section ".rodata"
 
-       .type   cpu_arch_name, #object
-cpu_arch_name:
-       .asciz  "armv4t"
-       .size   cpu_arch_name, . - cpu_arch_name
-
-       .type   cpu_elf_name, #object
-cpu_elf_name:
-       .asciz  "v4"
-       .size   cpu_elf_name, . - cpu_elf_name
-
-       .type   cpu_arm925_name, #object
-cpu_arm925_name:
-       .asciz  "ARM925T"
-       .size   cpu_arm925_name, . - cpu_arm925_name
+       string  cpu_arch_name, "armv4t"
+       string  cpu_elf_name, "v4"
+       string  cpu_arm925_name, "ARM925T"
 
        .align
 
        .section ".proc.info.init", #alloc, #execinstr
 
-       .type   __arm925_proc_info,#object
-__arm925_proc_info:
-       .long   0x54029250
-       .long   0xfffffff0
+.macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
+       .type   __\name\()_proc_info,#object
+__\name\()_proc_info:
+       .long   \cpu_val
+       .long   \cpu_mask
        .long   PMD_TYPE_SECT | \
                PMD_BIT4 | \
                PMD_SECT_AP_WRITE | \
@@ -514,27 +513,8 @@ __arm925_proc_info:
        .long   v4wbi_tlb_fns
        .long   v4wb_user_fns
        .long   arm925_cache_fns
-       .size   __arm925_proc_info, . - __arm925_proc_info
+       .size   __\name\()_proc_info, . - __\name\()_proc_info
+.endm
 
-       .type   __arm915_proc_info,#object
-__arm915_proc_info:
-       .long   0x54029150
-       .long   0xfffffff0
-       .long   PMD_TYPE_SECT | \
-               PMD_BIT4 | \
-               PMD_SECT_AP_WRITE | \
-               PMD_SECT_AP_READ
-       .long   PMD_TYPE_SECT | \
-               PMD_BIT4 | \
-               PMD_SECT_AP_WRITE | \
-               PMD_SECT_AP_READ
-       b       __arm925_setup
-       .long   cpu_arch_name
-       .long   cpu_elf_name
-       .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
-       .long   cpu_arm925_name
-       .long   arm925_processor_functions
-       .long   v4wbi_tlb_fns
-       .long   v4wb_user_fns
-       .long   arm925_cache_fns
-       .size   __arm925_proc_info, . - __arm925_proc_info
+       arm925_proc_info arm925, 0x54029250, 0xfffffff0, cpu_arm925_name
+       arm925_proc_info arm915, 0x54029150, 0xfffffff0, cpu_arm925_name