ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / tegra_emc.h
index 723550f..afeb021 100644 (file)
 #define TEGRA_EMC_ISO_USE_CASES_MAX_NUM                8
 
 extern u8 tegra_emc_bw_efficiency;
+extern u8 tegra_emc_iso_share;
 
 enum {
        DRAM_OVER_TEMP_NONE = 0,
-       DRAM_OVER_TEMP_REFRESH,
+       DRAM_OVER_TEMP_REFRESH_X2,
+       DRAM_OVER_TEMP_REFRESH_X4,
+       DRAM_OVER_TEMP_THROTTLE, /* 4x Refresh + derating. */
 };
 
 enum emc_user_id {
-       EMC_USER_DC = 0,
+       EMC_USER_DC1 = 0,
+       EMC_USER_DC2,
        EMC_USER_VI,
        EMC_USER_MSENC,
        EMC_USER_2D,
        EMC_USER_3D,
        EMC_USER_BB,
-
+       EMC_USER_VDE,
+       EMC_USER_VI2,
+       EMC_USER_ISP1,
+       EMC_USER_ISP2,
        EMC_USER_NUM,
 };
 
 struct emc_iso_usage {
        u32 emc_usage_flags;
        u8 iso_usage_share;
+       u8 (*iso_share_calculator)(unsigned long iso_bw);
 };
 
 struct clk;
@@ -66,6 +74,7 @@ struct clk *tegra_emc_predict_parent(unsigned long rate, u32 *div_value);
 bool tegra_emc_is_parent_ready(unsigned long rate, struct clk **parent,
                unsigned long *parent_rate, unsigned long *backup_rate);
 void tegra_emc_timing_invalidate(void);
+void tegra_mc_divider_update(struct clk *emc);
 
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 int tegra_emc_backup(unsigned long rate);