/*
* arch/arm/mach-tegra/tegra12_clocks.c
*
- * Copyright (C) 2011-2013 NVIDIA Corporation. All rights reserved.
+ * Copyright (C) 2011-2014 NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <mach/mc.h>
#include "clock.h"
-#include "fuse.h"
#include "dvfs.h"
#include "iomap.h"
#include "pm.h"
#include "devices.h"
#include "tegra12_emc.h"
#include "tegra_cl_dvfs.h"
+#include "cpu-tegra.h"
#define RST_DEVICES_L 0x004
#define RST_DEVICES_H 0x008
#define PERIPH_CLK_SOURCE_I2S1 0x100
#define PERIPH_CLK_SOURCE_EMC 0x19c
+#define PERIPH_CLK_SOURCE_EMC_MC_SAME (1<<16)
+
#define PERIPH_CLK_SOURCE_LA 0x1f8
#define PERIPH_CLK_SOURCE_NUM1 \
((PERIPH_CLK_SOURCE_LA - PERIPH_CLK_SOURCE_I2S1) / 4)
#define PLLU_BASE_POST_DIV (1<<20)
/* PLLD */
+#define PLLD_BASE_DIVN_MASK (0x7FF<<8)
#define PLLD_BASE_CSI_CLKENABLE (1<<26)
#define PLLD_BASE_DSI_MUX_SHIFT 25
#define PLLD_BASE_DSI_MUX_MASK (1<<PLLD_BASE_DSI_MUX_SHIFT)
#define PLLCX_MISC_VCO_GAIN_MASK (0x3 << PLLCX_MISC_VCO_GAIN_SHIFT)
#define PLLCX_MISC_KOEF_LOW_RANGE \
- ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
+ ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x23 << PLLCX_MISC_KB_SHIFT))
#define PLLCX_MISC_DIV_LOW_RANGE \
((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
#define PLLCX_MISC_DIV_HIGH_RANGE \
((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
+#define PLLCX_FD_ULCK_FRM_SHIFT 12
+#define PLLCX_FD_ULCK_FRM_MASK (0x3 << PLLCX_FD_ULCK_FRM_SHIFT)
+#define PLLCX_FD_LCK_FRM_SHIFT 8
+#define PLLCX_FD_LCK_FRM_MASK (0x3 << PLLCX_FD_LCK_FRM_SHIFT)
+#define PLLCX_PD_ULCK_FRM_SHIFT 28
+#define PLLCX_PD_ULCK_FRM_MASK (0x3 << PLLCX_PD_ULCK_FRM_SHIFT)
+#define PLLCX_PD_LCK_FRM_SHIFT 24
+#define PLLCX_PD_LCK_FRM_MASK (0x3 << PLLCX_PD_LCK_FRM_SHIFT)
+#define PLLCX_PD_OUT_HYST_SHIFT 20
+#define PLLCX_PD_OUT_HYST_MASK (0x3 << PLLCX_PD_OUT_HYST_SHIFT)
+#define PLLCX_PD_IN_HYST_SHIFT 16
+#define PLLCX_PD_IN_HYST_MASK (0x3 << PLLCX_PD_IN_HYST_SHIFT)
#define PLLCX_MISC_DEFAULT_VALUE ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \
PLLCX_MISC_KOEF_LOW_RANGE | \
PLLCX_MISC_DIV_LOW_RANGE | \
PLLCX_MISC_RESET)
#define PLLCX_MISC1_DEFAULT_VALUE 0x000d2308
-#define PLLCX_MISC2_DEFAULT_VALUE 0x30211200
+#define PLLCX_MISC2_DEFAULT_VALUE ((0x2 << PLLCX_PD_ULCK_FRM_SHIFT) | \
+ (0x1 << PLLCX_PD_LCK_FRM_SHIFT) | \
+ (0x3 << PLLCX_PD_OUT_HYST_SHIFT) | \
+ (0x1 << PLLCX_PD_IN_HYST_SHIFT) | \
+ (0x2 << PLLCX_FD_ULCK_FRM_SHIFT) | \
+ (0x2 << PLLCX_FD_LCK_FRM_SHIFT))
#define PLLCX_MISC3_DEFAULT_VALUE 0x200
#define PLLCX_MISC1_IDDQ (0x1 << 27)
#define PLLE_AUX_PLLRE_SEL (1<<28)
#define PLLE_AUX_SEQ_STATE_SHIFT 26
#define PLLE_AUX_SEQ_STATE_MASK (0x3<<PLLE_AUX_SEQ_STATE_SHIFT)
+#define PLLE_AUX_SEQ_START_STATE (1<<25)
#define PLLE_AUX_SEQ_ENABLE (1<<24)
+#define PLLE_AUX_SS_SWCTL (1<<6)
#define PLLE_AUX_ENABLE_SWCTL (1<<4)
#define PLLE_AUX_USE_LOCKDET (1<<3)
#define PLLE_AUX_PLLP_SEL (1<<2)
/* USB PLLs PD HW controls */
#define XUSBIO_PLL_CFG0 0x51c
+#define XUSBIO_PLL_CFG0_SEQ_START_STATE (1<<25)
#define XUSBIO_PLL_CFG0_SEQ_ENABLE (1<<24)
#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1<<6)
#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1<<2)
#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1<<0)
#define PLLU_HW_PWRDN_CFG0 0x530
+#define PLLU_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
#define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
#define PLLU_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
#define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
goto abort;
}
- /* Disabling old parent scales old mode voltage rail */
- if (c->refcnt)
- clk_disable(c->parent);
- if (p_source_old) {
- clk_disable(p->parent);
- clk_disable(p_source_old);
- }
-
- clk_reparent(c, p);
-
/*
* Lock DFLL now (resume closed loop VDD_CPU control).
* G CPU operations are resumed on DFLL if it was the last G CPU
}
}
+ /* Disabling old parent scales old mode voltage rail */
+ if (c->refcnt)
+ clk_disable(c->parent);
+ if (p_source_old) {
+ clk_disable(p->parent);
+ clk_disable(p_source_old);
+ }
+
+ clk_reparent(c, p);
+
tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
return 0;
/* This special sbus round function is implemented because:
*
- * (a) fractional 1 : 1.5 divider can not be used to derive system bus clock
+ * (a) sbus complex clock source is selected automatically based on rate
*
* (b) since sbus is a shared bus, and its frequency is set to the highest
* enabled shared_bus_user clock, the target rate should be rounded up divider
round_rate = source_rate * 2 / (divider + 2);
if (round_rate > c->max_rate) {
- divider = max(2, (divider + 1));
+ divider += new_parent->flags & DIV_U71_INT ? 2 : 1;
+#if !DIVIDER_1_5_ALLOWED
+ divider = max(2, divider);
+#endif
round_rate = source_rate * 2 / (divider + 2);
}
static void usb_plls_hw_control_enable(u32 reg)
{
u32 val = clk_readl(reg);
- val |= USB_PLLS_USE_LOCKDET;
+ val |= USB_PLLS_USE_LOCKDET | USB_PLLS_SEQ_START_STATE;
val &= ~USB_PLLS_ENABLE_SWCTL;
val |= USB_PLLS_SEQ_START_STATE;
pll_writel_delay(val, reg);
static void tegra12_pll_clk_init(struct clk *c)
{
u32 val = clk_readl(c->reg + PLL_BASE);
+ u32 divn_mask = c->flags & PLLD ?
+ PLLD_BASE_DIVN_MASK : PLL_BASE_DIVN_MASK;
c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
c->mul = 1;
c->div = 1;
} else {
- c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+ c->mul = (val & divn_mask) >> PLL_BASE_DIVN_SHIFT;
c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
if (c->flags & PLLU)
c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
unsigned long input_rate;
const struct clk_pll_freq_table *sel;
struct clk_pll_freq_table cfg;
+ u32 divn_mask = c->flags & PLLD ?
+ PLLD_BASE_DIVN_MASK : PLL_BASE_DIVN_MASK;
pr_debug("%s: %s %lu\n", __func__, c->name, rate);
cfg.cpcon = get_pll_cpcon(c, cfg.n);
if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
- (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
+ (cfg.n > (divn_mask >> PLL_BASE_DIVN_SHIFT)) ||
(p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
(cfg.output_rate > c->u.pll.vco_max)) {
pr_err("%s: Failed to set %s out-of-table rate %lu\n",
c->div = sel->m * sel->p;
old_base = val = clk_readl(c->reg + PLL_BASE);
- val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
+ val &= ~(PLL_BASE_DIVM_MASK | divn_mask |
((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
(sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
val &= ~PLLE_BASE_LOCK_OVERRIDE;
clk_writel(val, c->reg + PLL_BASE);
- val = clk_readl(PLLE_AUX);
- val |= PLLE_AUX_ENABLE_SWCTL;
- val &= ~PLLE_AUX_SEQ_ENABLE;
- pll_writel_delay(val, PLLE_AUX);
-
val = clk_readl(c->reg + PLL_MISC(c));
val |= PLLE_MISC_LOCK_ENABLE;
val |= PLLE_MISC_IDDQ_SW_CTRL;
clk_writel(val, c->reg + PLL_MISC(c));
val = clk_readl(PLLE_AUX);
- val |= PLLE_AUX_USE_LOCKDET;
- val &= ~PLLE_AUX_ENABLE_SWCTL;
+ val |= PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE;
+ val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
pll_writel_delay(val, PLLE_AUX);
val |= PLLE_AUX_SEQ_ENABLE;
pll_writel_delay(val, PLLE_AUX);
if (!c->parent || !c->parent->dvfs || !dfll)
return -ENOSYS;
+ ret = tegra_cpu_reg_mode_force_normal(true);
+ if (ret) {
+ pr_err("%s: Failed to force regulator normal mode\n", __func__);
+ return ret;
+ }
+
clk_lock_save(c, &c_flags);
if (dfll->state == UNINITIALIZED) {
pr_err("%s: DFLL is not initialized\n", __func__);
clk_unlock_restore(c, &c_flags);
+ tegra_cpu_reg_mode_force_normal(false);
return -ENOSYS;
}
if (c->parent->u.cpu.mode == MODE_LP) {
pr_err("%s: DFLL is not used on LP CPU\n", __func__);
clk_unlock_restore(c, &c_flags);
+ tegra_cpu_reg_mode_force_normal(false);
return -ENOSYS;
}
}
clk_unlock_restore(c->parent, &p_flags);
clk_unlock_restore(c, &c_flags);
- tegra_recalculate_cpu_edp_limits();
+ tegra_update_cpu_edp_limits();
return ret;
}
{
tegra12_periph_clk_init(c);
tegra_emc_dram_type_init(c);
- c->max_rate = clk_get_rate(c->parent);
}
static long tegra12_emc_clk_round_updown(struct clk *c, unsigned long rate,
static int tegra12_clk_emc_bus_update(struct clk *bus)
{
struct clk *p = NULL;
- unsigned long rate, parent_rate, backup_rate;
+ unsigned long rate, old_rate, parent_rate, backup_rate;
if (detach_shared_bus)
return 0;
rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
- if (rate == clk_get_rate_locked(bus))
+ old_rate = clk_get_rate_locked(bus);
+ if (rate == old_rate)
return 0;
if (!tegra_emc_is_parent_ready(rate, &p, &parent_rate, &backup_rate)) {
if (bus->parent == p) {
/* need backup to re-lock current parent */
- if (IS_ERR_VALUE(backup_rate) ||
- clk_set_rate_locked(bus, backup_rate)) {
- pr_err("%s: Failed to backup %s for rate %lu\n",
+ int ret;
+ if (IS_ERR_VALUE(backup_rate)) {
+ pr_err("%s: No backup for %s rate %lu\n",
__func__, bus->name, rate);
return -EINVAL;
}
- if (p->refcnt) {
- pr_err("%s: %s has other than emc child\n",
- __func__, p->name);
+ /* set volatge for backup rate if going up */
+ if (backup_rate > old_rate) {
+ ret = tegra_dvfs_set_rate(bus, backup_rate);
+ if (ret) {
+ pr_err("%s: dvfs failed on %s rate %lu\n",
+ __func__, bus->name, backup_rate);
+ return -EINVAL;
+ }
+ }
+
+ trace_clock_set_rate(bus->name, backup_rate, 0);
+ ret = bus->ops->set_rate(bus, backup_rate);
+ if (ret) {
+ pr_err("%s: Failed to backup %s for rate %lu\n",
+ __func__, bus->name, rate);
return -EINVAL;
}
+ clk_rate_change_notify(bus, backup_rate);
+ }
+ if (p->refcnt) {
+ pr_err("%s: %s has other than emc child\n",
+ __func__, p->name);
+ return -EINVAL;
}
+
if (clk_set_rate(p, parent_rate)) {
pr_err("%s: Failed to set %s rate %lu\n",
__func__, p->name, parent_rate);
.shared_bus_update = &tegra12_clk_emc_bus_update,
};
+void tegra_mc_divider_update(struct clk *emc)
+{
+ emc->child_bus->div = (clk_readl(emc->reg) &
+ PERIPH_CLK_SOURCE_EMC_MC_SAME) ? 1 : 2;
+}
+
+static void tegra12_mc_clk_init(struct clk *c)
+{
+ c->state = ON;
+ if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
+ c->state = OFF;
+
+ c->parent->child_bus = c;
+ tegra_mc_divider_update(c->parent);
+ c->mul = 1;
+}
+
+static struct clk_ops tegra_mc_clk_ops = {
+ .init = &tegra12_mc_clk_init,
+ .enable = &tegra12_periph_clk_enable,
+ .disable = &tegra12_periph_clk_disable,
+};
+
/* Clock doubler ops (non-atomic shared register access) */
static DEFINE_SPINLOCK(doubler_lock);
/* update min now, since no dvfs table was available during init
(skip placeholder entries set to 1 kHz) */
if (!c->min_rate) {
- for (i = 0; i < (c->dvfs->num_freqs - 1); i++) {
+ for (i = 0; i < c->dvfs->num_freqs; i++) {
if (c->dvfs->freqs[i] > 1 * c->dvfs->freqs_mult) {
c->min_rate = c->dvfs->freqs[i];
break;
static struct clk tegra_pll_c_out1 = {
.name = "pll_c_out1",
.ops = &tegra_pll_div_ops,
+#ifdef CONFIG_TEGRA_DUAL_CBUS
+ .flags = DIV_U71,
+#else
.flags = DIV_U71 | PERIPH_ON_CBUS,
+#endif
.parent = &tegra_pll_c,
.reg = 0x84,
.reg_shift = 0,
.ops = &tegra_pllm_ops,
.reg = 0x90,
.parent = &tegra_pll_ref,
- .max_rate = 1066000000,
+ .max_rate = 1200000000,
.u.pll = {
.input_min = 12000000,
.input_max = 500000000,
.cf_min = 12000000,
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
.vco_min = 500000000,
- .vco_max = 1066000000,
+ .vco_max = 1200000000,
.freq_table = tegra_pll_m_freq_table,
.lock_delay = 300,
.misc1 = 0x98 - 0x90,
static struct clk tegra_pll_m_out1 = {
.name = "pll_m_out1",
.ops = &tegra_pll_div_ops,
- .flags = DIV_U71,
+ .flags = DIV_U71 | DIV_U71_INT,
.parent = &tegra_pll_m,
.reg = 0x94,
.reg_shift = 0,
- .max_rate = 1066000000,
+ .max_rate = 1200000000,
};
static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
static struct clk tegra_pll_p_out2 = {
.name = "pll_p_out2",
.ops = &tegra_pll_div_ops,
- .flags = DIV_U71 | DIV_U71_FIXED,
+ .flags = DIV_U71 | DIV_U71_FIXED | DIV_U71_INT,
.parent = &tegra_pll_p,
.reg = 0xa4,
.reg_shift = 16,
{ 19200000, 216000000, 720, 16, 4, 12},
{ 26000000, 216000000, 864, 26, 4, 12},
- { 12000000, 594000000, 594, 12, 1, 12},
+ { 12000000, 594000000, 99, 2, 1, 8},
{ 13000000, 594000000, 594, 13, 1, 12},
{ 16800000, 594000000, 495, 14, 1, 12},
{ 19200000, 594000000, 495, 16, 1, 12},
.ops = &tegra_pll_div_ops,
.flags = DIV_2 | PLLD,
.parent = &tegra_pll_d,
- .max_rate = 500000000,
+ .max_rate = 750000000,
};
static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
.ops = &tegra_pll_div_ops,
.flags = DIV_2 | PLLX,
.parent = &tegra_pll_x,
- .max_rate = 700000000,
+ .max_rate = 1500000000UL,
};
static struct clk tegra_dfll_cpu = {
};
static struct clk_pll_freq_table tegra_plldp_freq_table[] = {
- { 12000000, 600000000, 100, 1, 2},
- { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
- { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
- { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
- { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
+ { 12000000, 270000000, 90, 1, 4},
+ { 13000000, 270000000, 83, 1, 4}, /* actual: 269.8 MHz */
+ { 16800000, 270000000, 96, 1, 6}, /* actual: 268.8 MHz */
+ { 19200000, 270000000, 84, 1, 6}, /* actual: 268.8 MHz */
+ { 26000000, 270000000, 83, 2, 4}, /* actual: 269.8 MHz */
{ 0, 0, 0, 0, 0, 0 },
};
.inputs = mux_sclk,
.reg = 0x28,
.ops = &tegra_super_ops,
- .max_rate = 420000000,
+ .max_rate = 408000000,
.min_rate = 12000000,
};
.parent = &tegra_clk_cclk_g,
.ops = &tegra_cpu_ops,
.max_rate = 3000000000UL,
+ .min_rate = 3187500,
.u.cpu = {
.main = &tegra_pll_x,
.backup = &tegra_pll_p_out4,
.parent = &tegra_clk_cclk_lp,
.ops = &tegra_cpu_ops,
.max_rate = 1350000000,
+ .min_rate = 3187500,
.u.cpu = {
.main = &tegra_pll_x,
.backup = &tegra_pll_p_out4,
.name = "cop",
.parent = &tegra_clk_sclk,
.ops = &tegra_cop_ops,
- .max_rate = 336000000,
+ .max_rate = 408000000,
};
static struct clk tegra_clk_hclk = {
.reg = 0x30,
.reg_shift = 4,
.ops = &tegra_bus_ops,
- .max_rate = 336000000,
+ .max_rate = 408000000,
.min_rate = 12000000,
};
.reg = 0x30,
.reg_shift = 0,
.ops = &tegra_bus_ops,
- .max_rate = 168000000,
+ .max_rate = 204000000,
.min_rate = 12000000,
};
.name = "emc",
.ops = &tegra_emc_clk_ops,
.reg = 0x19c,
- .max_rate = 1066000000,
+ .max_rate = 1200000000,
.min_rate = 12750000,
.inputs = mux_pllm_pllc_pllp_clkm,
.flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
.rate_change_nh = &emc_rate_change_nh,
};
+static struct clk tegra_clk_mc = {
+ .name = "mc",
+ .ops = &tegra_mc_clk_ops,
+ .max_rate = 533000000,
+ .parent = &tegra_clk_emc,
+ .flags = PERIPH_NO_RESET,
+ .u.periph = {
+ .clk_num = 32,
+ },
+};
+
static struct raw_notifier_head host1x_rate_change_nh;
static struct clk tegra_clk_host1x = {
.rate_change_nh = &host1x_rate_change_nh,
};
+static struct raw_notifier_head mselect_rate_change_nh;
+
+static struct clk tegra_clk_mselect = {
+ .name = "mselect",
+ .lookup = {
+ .dev_id = "mselect",
+ },
+ .ops = &tegra_1xbus_clk_ops,
+ .reg = 0x3b4,
+ .inputs = mux_pllp_clkm,
+ .flags = MUX | DIV_U71 | DIV_U71_INT,
+ .max_rate = 408000000,
+ .min_rate = 12000000,
+ .u.periph = {
+ .clk_num = 99,
+ .pll_low = &tegra_pll_p,
+ .pll_high = &tegra_pll_p,
+ .threshold = 408000000,
+ },
+ .rate_change_nh = &mselect_rate_change_nh,
+};
+
#ifdef CONFIG_TEGRA_DUAL_CBUS
static struct raw_notifier_head c2bus_rate_change_nh;
.min_rate = 12000000,
};
+#define RATE_GRANULARITY 100000 /* 0.1 MHz */
+#if defined(CONFIG_TEGRA_CLOCK_DEBUG_FUNC)
+static int gbus_round_pass_thru;
+void tegra_gbus_round_pass_thru_enable(bool enable)
+{
+ if (enable)
+ gbus_round_pass_thru = 1;
+ else
+ gbus_round_pass_thru = 0;
+}
+EXPORT_SYMBOL(tegra_gbus_round_pass_thru_enable);
+#else
+#define gbus_round_pass_thru 0
+#endif
+
static void tegra12_clk_gbus_init(struct clk *c)
{
unsigned long rate;
return;
c->u.export_clk.ops->init(c->u.export_clk.ops->data, &rate, &enabled);
- c->div = clk_get_rate(c->parent) / 1000000;
- c->mul = rate / 1000000;
+ c->div = clk_get_rate(c->parent) / RATE_GRANULARITY;
+ c->mul = rate / RATE_GRANULARITY;
c->state = enabled ? ON : OFF;
}
ret = c->u.export_clk.ops->set_rate(c->u.export_clk.ops->data, &rate);
if (!ret)
- c->mul = rate / 1000000;
+ c->mul = rate / RATE_GRANULARITY;
return ret;
}
+static long tegra12_clk_gbus_round_updown(struct clk *c, unsigned long rate,
+ bool up)
+{
+ return gbus_round_pass_thru ? rate :
+ tegra12_clk_cbus_round_updown(c, rate, up);
+}
+
+static long tegra12_clk_gbus_round_rate(struct clk *c, unsigned long rate)
+{
+ return tegra12_clk_gbus_round_updown(c, rate, true);
+}
+
static struct clk_ops tegra_clk_gbus_ops = {
.init = tegra12_clk_gbus_init,
.enable = tegra12_clk_gbus_enable,
.disable = tegra12_clk_gbus_disable,
.set_rate = tegra12_clk_gbus_set_rate,
- .round_rate = tegra12_clk_cbus_round_rate, /* re-use */
- .round_rate_updown = tegra12_clk_cbus_round_updown, /* re-use */
+ .round_rate = tegra12_clk_gbus_round_rate,
+ .round_rate_updown = tegra12_clk_gbus_round_updown,
.shared_bus_update = tegra12_clk_shared_connector_update, /* re-use */
};
.name = "gbus",
.ops = &tegra_clk_gbus_ops,
.parent = &tegra_clk_gpu,
- .max_rate = 1000000000,
+ .max_rate = 1032000000,
.shared_bus_flags = SHARED_BUS_RETENTION,
.rate_change_nh = &gbus_rate_change_nh,
};
PERIPH_CLK("adx1", "adx1", NULL, 180, 0x670, 24580000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 24600000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("amx1", "amx1", NULL, 185, 0x674, 24600000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("afc0", "tegra124-afc.0", NULL, 186, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
+ PERIPH_CLK("afc1", "tegra124-afc.1", NULL, 187, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
+ PERIPH_CLK("afc2", "tegra124-afc.2", NULL, 188, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
+ PERIPH_CLK("afc3", "tegra124-afc.3", NULL, 189, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
+ PERIPH_CLK("afc4", "tegra124-afc.4", NULL, 190, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
+ PERIPH_CLK("afc5", "tegra124-afc.5", NULL, 191, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sdmmc1_ddr", "sdhci-tegra.0", "ddr", 14, 0x150, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sdmmc3_ddr", "sdhci-tegra.2", "ddr", 69, 0x1bc, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sdmmc4_ddr", "sdhci-tegra.3", "ddr", 15, 0x164, 102000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("se", "se", NULL, 127, 0x42c, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
- PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 102000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs", "ref", 155, 0x62c, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs", "soc", 155, 0x630, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
PERIPH_CLK("soc_therm", "soc_therm", NULL, 78, 0x644, 136000000, mux_pllm_pllc_pllp_plla_v2, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("dds", "dds", NULL, 150, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("dp2", "dp2", NULL, 152, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
+ SHARED_SCLK("automotive.hclk", "automotive", "hclk", &tegra_clk_ahb, NULL, 0, 0),
+ SHARED_SCLK("automotive.pclk", "automotive", "pclk", &tegra_clk_apb, NULL, 0, 0),
+
SHARED_SCLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_SCLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_SCLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_ahb, NULL, 0, 0),
SHARED_SCLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_ahb, NULL, 0, 0),
SHARED_SCLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_ahb, NULL, 0, 0),
SHARED_SCLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_ahb, NULL, 0, 0),
- SHARED_SCLK("sdmmc3.sclk", "sdhci-tegra.2", "sclk", &tegra_clk_apb, NULL, 0, 0),
- SHARED_SCLK("sdmmc4.sclk", "sdhci-tegra.3", "sclk", &tegra_clk_apb, NULL, 0, 0),
SHARED_SCLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_SCLK("camera.sclk", "vi", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_SCLK("automotive.sclk", "automotive", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_SCLK("via.sclk", "tegra_vi.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_SCLK("vib.sclk", "tegra_vi.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_SCLK("ispa.sclk", "tegra_isp.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_SCLK("ispb.sclk", "tegra_isp.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_SCLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_SCLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
+ SHARED_SCLK("cap.vcore.sclk", "cap.vcore.sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
SHARED_SCLK("cap.throttle.sclk", "cap_throttle", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
SHARED_SCLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_SCLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
SHARED_SCLK("sbc1.sclk", "tegra12-spi.0", "sclk", &tegra_clk_apb, NULL, 0, 0),
SHARED_SCLK("sbc2.sclk", "tegra12-spi.1", "sclk", &tegra_clk_apb, NULL, 0, 0),
SHARED_SCLK("sbc3.sclk", "tegra12-spi.2", "sclk", &tegra_clk_apb, NULL, 0, 0),
+ SHARED_SCLK("sbc4.sclk", "tegra12-spi.3", "sclk", &tegra_clk_apb, NULL, 0, 0),
+ SHARED_SCLK("sbc5.sclk", "tegra12-spi.4", "sclk", &tegra_clk_apb, NULL, 0, 0),
+ SHARED_SCLK("sbc6.sclk", "tegra12-spi.5", "sclk", &tegra_clk_apb, NULL, 0, 0),
SHARED_EMC_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("mon_cpu.emc", "tegra_mon", "cpu_emc",
SHARED_EMC_CLK("sdmmc4.emc", "sdhci-tegra.3","emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
+ SHARED_EMC_CLK("cap.vcore.emc", "cap.vcore.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
SHARED_EMC_CLK("cap.throttle.emc", "cap_throttle", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING_BUT_ISO, 0),
- SHARED_EMC_CLK("3d.emc", "tegra_gk20a", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_3D)),
+ SHARED_EMC_CLK("3d.emc", "tegra_gk20a.0", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_3D)),
SHARED_EMC_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, BIT(EMC_USER_MSENC)),
SHARED_EMC_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
- SHARED_EMC_CLK("via.emc", "tegra_vi", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI)),
+ SHARED_EMC_CLK("via.emc", "tegra_vi.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI)),
SHARED_EMC_CLK("vib.emc", "tegra_vi.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI2)),
- SHARED_EMC_CLK("ispa.emc", "tegra_isp", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_ISP1)),
+ SHARED_EMC_CLK("ispa.emc", "tegra_isp.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_ISP1)),
SHARED_EMC_CLK("ispb.emc", "tegra_isp.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_ISP2)),
SHARED_EMC_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE, 0),
- SHARED_EMC_CLK("edp.emc", "edp.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
- SHARED_EMC_CLK("vic.emc", "tegra_vic03", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("vic.emc", "tegra_vic03.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("battery.emc", "battery_edp", "emc", &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
#ifdef CONFIG_TEGRA_DUAL_CBUS
DUAL_CBUS_CLK("msenc.cbus", "tegra_msenc", "msenc", &tegra_clk_c2bus, "msenc", 0, 0),
DUAL_CBUS_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_c2bus, "vde", 0, 0),
DUAL_CBUS_CLK("se.cbus", "tegra12-se", NULL, &tegra_clk_c2bus, "se", 0, 0),
SHARED_LIMIT("cap.c2bus", "cap.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("cap.vcore.c2bus", "cap.vcore.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
SHARED_LIMIT("cap.throttle.c2bus", "cap_throttle", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
SHARED_LIMIT("floor.c2bus", "floor.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0),
SHARED_CLK("override.c2bus", "override.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_OVERRIDE),
- SHARED_LIMIT("edp.c2bus", "edp.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
- DUAL_CBUS_CLK("vic03.cbus", "tegra_vic03", "vic03", &tegra_clk_c3bus, "vic03", 0, 0),
+ DUAL_CBUS_CLK("vic03.cbus", "tegra_vic03.0", "vic03", &tegra_clk_c3bus, "vic03", 0, 0),
DUAL_CBUS_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_c3bus, "tsec", 0, 0),
SHARED_LIMIT("cap.c3bus", "cap.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("cap.vcore.c3bus", "cap.vcore.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
SHARED_LIMIT("cap.throttle.c3bus", "cap_throttle", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
SHARED_LIMIT("floor.c3bus", "floor.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, 0),
SHARED_CLK("override.c3bus", "override.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_OVERRIDE),
#else
- SHARED_CLK("vic03.cbus", "tegra_vic03", "vic03", &tegra_clk_cbus, "vic03", 0, 0),
+ SHARED_CLK("vic03.cbus", "tegra_vic03.0", "vic03", &tegra_clk_cbus, "vic03", 0, 0),
SHARED_CLK("msenc.cbus","tegra_msenc", "msenc",&tegra_clk_cbus, "msenc", 0, 0),
SHARED_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_cbus, "tsec", 0, 0),
SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0),
SHARED_CLK("se.cbus", "tegra12-se", NULL, &tegra_clk_cbus, "se", 0, 0),
SHARED_LIMIT("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("cap.vcore.cbus", "cap.vcore.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
SHARED_LIMIT("cap.throttle.cbus", "cap_throttle", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
SHARED_LIMIT("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0),
SHARED_CLK("override.cbus", "override.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_OVERRIDE),
- SHARED_LIMIT("edp.cbus", "edp.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
#endif
SHARED_CLK("gk20a.gbus", "tegra_gk20a", "gpu", &tegra_clk_gbus, NULL, 0, 0),
SHARED_LIMIT("cap.gbus", "cap.gbus", NULL, &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("edp.gbus", "edp.gbus", NULL, &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("battery.gbus", "battery_edp", "gpu", &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
SHARED_LIMIT("cap.throttle.gbus", "cap_throttle", NULL, &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
- SHARED_LIMIT("cap.profile.gbus", "profile.gbus", "cap", &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("cap.profile.gbus", "profile.gbus", "cap", &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
SHARED_CLK("override.gbus", "override.gbus", NULL, &tegra_clk_gbus, NULL, 0, SHARED_OVERRIDE),
SHARED_LIMIT("floor.gbus", "floor.gbus", NULL, &tegra_clk_gbus, NULL, 0, 0),
SHARED_LIMIT("floor.profile.gbus", "profile.gbus", "floor", &tegra_clk_gbus, NULL, 0, 0),
SHARED_CLK("nv.host1x", "tegra_host1x", "host1x", &tegra_clk_host1x, NULL, 0, 0),
SHARED_CLK("vi.host1x", "tegra_vi", "host1x", &tegra_clk_host1x, NULL, 0, 0),
SHARED_LIMIT("cap.host1x", "cap.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("cap.vcore.host1x", "cap.vcore.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_CEILING),
SHARED_LIMIT("floor.host1x", "floor.host1x", NULL, &tegra_clk_host1x, NULL, 0, 0),
SHARED_CLK("override.host1x", "override.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_OVERRIDE),
+
+ SHARED_CLK("cpu.mselect", "cpu", "mselect", &tegra_clk_mselect, NULL, 0, 0),
+ SHARED_CLK("pcie.mselect", "tegra_pcie", "mselect", &tegra_clk_mselect, NULL, 0, 0),
+ SHARED_CLK("automotive.mselect", "automotive", "mselect", &tegra_clk_mselect, NULL, 0, 0),
+ SHARED_LIMIT("cap.vcore.mselect", "cap.vcore.mselect", NULL, &tegra_clk_mselect, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("override.mselect", "override.mselect", NULL, &tegra_clk_mselect, NULL, 0, SHARED_OVERRIDE),
};
/* VI, ISP buses */
CLK_DUPLICATE("uartb", "serial8250.1", NULL),
CLK_DUPLICATE("uartc", "serial8250.2", NULL),
CLK_DUPLICATE("uartd", "serial8250.3", NULL),
+ CLK_DUPLICATE("usbd", XUSB_ID, "utmip-pad"),
CLK_DUPLICATE("usbd", "utmip-pad", NULL),
CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
CLK_DUPLICATE("usbd", "tegra-otg", NULL),
CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
- CLK_DUPLICATE("cl_dvfs_ref", "tegra14-i2c.4", NULL),
- CLK_DUPLICATE("cl_dvfs_soc", "tegra14-i2c.4", NULL),
+ CLK_DUPLICATE("cl_dvfs_ref", "tegra12-i2c.4", NULL),
+ CLK_DUPLICATE("cl_dvfs_soc", "tegra12-i2c.4", NULL),
CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL),
CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL),
CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL),
CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
CLK_DUPLICATE("actmon", "tegra_host1x", "actmon"),
- CLK_DUPLICATE("gpu_ref", "tegra_gk20a", "PLLG_ref"),
- CLK_DUPLICATE("gbus", "tegra_gk20a", "PLLG_out"),
- CLK_DUPLICATE("pll_p_out5", "tegra_gk20a", "pwr"),
- CLK_DUPLICATE("ispa.isp.c4bus", "tegra_isp", "isp"),
+ CLK_DUPLICATE("gpu_ref", "tegra_gk20a.0", "PLLG_ref"),
+ CLK_DUPLICATE("gbus", "tegra_gk20a.0", "PLLG_out"),
+ CLK_DUPLICATE("pll_p_out5", "tegra_gk20a.0", "pwr"),
+ CLK_DUPLICATE("ispa.isp.c4bus", "tegra_isp.0", "isp"),
CLK_DUPLICATE("ispb.isp.c4bus", "tegra_isp.1", "isp"),
- CLK_DUPLICATE("via.vi.c4bus", "tegra_vi", "vi"),
+ CLK_DUPLICATE("via.vi.c4bus", "tegra_vi.0", "vi"),
CLK_DUPLICATE("vib.vi.c4bus", "tegra_vi.1", "vi"),
- CLK_DUPLICATE("csi", "tegra_vi", "csi"),
+ CLK_DUPLICATE("csi", "tegra_vi.0", "csi"),
CLK_DUPLICATE("csi", "tegra_vi.1", "csi"),
- CLK_DUPLICATE("csus", "tegra_vi", "csus"),
+ CLK_DUPLICATE("csus", "tegra_vi.0", "csus"),
CLK_DUPLICATE("vim2_clk", "tegra_vi.1", "vim2_clk"),
- CLK_DUPLICATE("cilab", "tegra_vi", "cilab"),
+ CLK_DUPLICATE("cilab", "tegra_vi.0", "cilab"),
CLK_DUPLICATE("cilcd", "tegra_vi.1", "cilcd"),
CLK_DUPLICATE("cile", "tegra_vi.1", "cile"),
CLK_DUPLICATE("i2s0", NULL, "i2s0"),
CLK_DUPLICATE("dam2", NULL, "dam2"),
CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
CLK_DUPLICATE("mclk", NULL, "default_mclk"),
+ CLK_DUPLICATE("amx", NULL, "amx"),
+ CLK_DUPLICATE("amx1", NULL, "amx1"),
+ CLK_DUPLICATE("adx", NULL, "adx"),
+ CLK_DUPLICATE("adx1", NULL, "adx1"),
+ CLK_DUPLICATE("afc0", NULL, "afc0"),
+ CLK_DUPLICATE("afc1", NULL, "afc1"),
+ CLK_DUPLICATE("afc2", NULL, "afc2"),
+ CLK_DUPLICATE("afc3", NULL, "afc3"),
+ CLK_DUPLICATE("afc4", NULL, "afc4"),
+ CLK_DUPLICATE("afc5", NULL, "afc5"),
+ CLK_DUPLICATE("amx", "tegra124-amx.0", NULL),
+ CLK_DUPLICATE("amx1", "tegra124-amx.1", NULL),
+ CLK_DUPLICATE("adx", "tegra124-adx.0", NULL),
+ CLK_DUPLICATE("adx1", "tegra124-adx.1", NULL),
+ CLK_DUPLICATE("amx", "tegra30-ahub-apbif", "amx"),
+ CLK_DUPLICATE("amx1", "tegra30-ahub-apbif", "amx1"),
+ CLK_DUPLICATE("adx", "tegra30-ahub-apbif", "adx"),
+ CLK_DUPLICATE("adx1", "tegra30-ahub-apbif", "adx1"),
+ CLK_DUPLICATE("d_audio", "tegra30-ahub-xbar", "d_audio"),
+ CLK_DUPLICATE("apbif", "tegra30-ahub-apbif", "apbif"),
+ CLK_DUPLICATE("afc0", "tegra30-ahub-apbif", "afc0"),
+ CLK_DUPLICATE("afc1", "tegra30-ahub-apbif", "afc1"),
+ CLK_DUPLICATE("afc2", "tegra30-ahub-apbif", "afc2"),
+ CLK_DUPLICATE("afc3", "tegra30-ahub-apbif", "afc3"),
+ CLK_DUPLICATE("afc4", "tegra30-ahub-apbif", "afc4"),
+ CLK_DUPLICATE("afc5", "tegra30-ahub-apbif", "afc5"),
};
struct clk *tegra_ptr_clks[] = {
&tegra_clk_ahb,
&tegra_clk_apb,
&tegra_clk_emc,
+ &tegra_clk_mc,
&tegra_clk_host1x,
+ &tegra_clk_mselect,
#ifdef CONFIG_TEGRA_DUAL_CBUS
&tegra_clk_c2bus,
&tegra_clk_c3bus,
return NULL;
}
g_vmin_freq = cpu_clk_g->dvfs->freqs[0] / 1000;
- if (g_vmin_freq <= lp_backup_freq) {
+ if (g_vmin_freq < lp_backup_freq) {
WARN(1, "%s: cannot make cpufreq table: LP CPU backup rate"
" exceeds G CPU rate at Vmin\n", __func__);
return NULL;
}
+ /* Avoid duplicate frequency if g_vim_freq is already part of table */
+ if (g_vmin_freq == lp_backup_freq)
+ g_vmin_done = true;
/* Start with backup frequencies */
i = 0;
unsigned long mselect_rate;
if (!mselect) {
- mselect = tegra_get_clock_by_name("mselect");
+ mselect = tegra_get_clock_by_name("cpu.mselect");
if (!mselect)
return -ENODEV;
}
cpu rate is in kHz, mselect rate is in Hz */
mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000;
mselect_rate = min(mselect_rate, 102000000UL);
-
- if (mselect_rate != clk_get_rate(mselect))
- return clk_set_rate(mselect, mselect_rate);
-
- return 0;
+ return clk_set_rate(mselect, mselect_rate);
}
#endif
tegra12_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */
tegra12_plle_clk_resume(&tegra_pll_e); /* Restore plle parent as pll_re_vco */
tegra12_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */
+ tegra12_mc_holdoff_enable();
}
static struct syscore_ops tegra_clk_syscore_ops = {
tegra12_init_one_clock(&tegra_xusb_coupled_clks[i]);
}
+#ifdef CONFIG_TEGRA_PREINIT_CLOCKS
+
+#define CLK_RSTENB_DEV_V_0_AUDIO_BIT (1 << 10)
+#define CLK_RSTENB_DEV_V_0_3D2_BIT (1 << 2)
+
+#define CLK_RSTENB_DEV_L_0_HOST1X_BIT (1 << 28)
+#define CLK_RSTENB_DEV_L_0_DISP1_BIT (1 << 27)
+#define CLK_RSTENB_DEV_L_0_3D_BIT (1 << 24)
+#define CLK_RSTENB_DEV_L_0_ISP_BIT (1 << 23)
+#define CLK_RSTENB_DEV_L_0_2D_BIT (1 << 21)
+#define CLK_RSTENB_DEV_L_0_VI_BIT (1 << 20)
+#define CLK_RSTENB_DEV_L_0_EPP_BIT (1 << 19)
+
+#define CLK_RSTENB_DEV_H_0_VDE_BIT (1 << 29)
+#define CLK_RSTENB_DEV_H_0_MPE_BIT (1 << 28)
+
+#define CLK_RSTENB_DEV_U_0_CSITE_BIT (1 << 9)
+
+#define CLK_RSTENB_DEV_X_0_HDMI_AUDIO_BIT (1 << 16)
+
+#define HOST1X_CLK_REG_OFFSET 0x180
+#define HOST1X_CLK_SRC_SHIFT 30
+#define HOST1X_CLK_SRC_MASK (0x3 << HOST1X_CLK_SRC_SHIFT)
+#define HOST1X_CLK_SRC_PLLM_OUT0 0
+#define HOST1X_CLK_SRC_PLLC_OUT0 1
+#define HOST1X_CLK_SRC_PLLP_OUT0 2
+#define HOST1X_CLK_SRC_PLLA_OUT0 3
+#define HOST1X_CLK_SRC_DEFAULT (\
+ HOST1X_CLK_SRC_PLLP_OUT0 << HOST1X_CLK_SRC_SHIFT)
+#define HOST1X_CLK_IDLE_DIV_SHIFT 8
+#define HOST1X_CLK_IDLE_DIV_MASK (0xff << HOST1X_CLK_IDLE_DIV_SHIFT)
+#define HOST1X_CLK_IDLE_DIV_DEFAULT (0 << HOST1X_CLK_IDLE_DIV_SHIFT)
+#define HOST1X_CLK_DIV_SHIFT 0
+#define HOST1X_CLK_DIV_MASK (0xff << HOST1X_CLK_DIV_SHIFT)
+#define HOST1X_CLK_DIV_DEFAULT (3 << HOST1X_CLK_DIV_SHIFT)
+
+#define VCLK_SRC_SHIFT 30
+#define VCLK_SRC_MASK (0x3 << VCLK_SRC_SHIFT)
+#define VCLK_SRC_PLLM_OUT0 0
+#define VCLK_SRC_PLLC_OUT0 1
+#define VCLK_SRC_PLLP_OUT0 2
+#define VCLK_SRC_PLLA_OUT0 3
+#define VCLK_SRC_DEFAULT (VCLK_SRC_PLLM_OUT0 << VCLK_SRC_SHIFT)
+#define VCLK_IDLE_DIV_SHIFT 8
+#define VCLK_IDLE_DIV_MASK (0xff << VCLK_IDLE_DIV_SHIFT)
+#define VCLK_IDLE_DIV_DEFAULT (0 << VCLK_IDLE_DIV_SHIFT)
+#define VCLK_DIV_SHIFT 0
+#define VCLK_DIV_MASK (0xff << VCLK_DIV_SHIFT)
+#define VCLK_DIV_DEFAULT (0xa << VCLK_DIV_SHIFT)
+
+#define ISP_CLK_REG_OFFSET 0x144
+#define VI_CLK_REG_OFFSET 0x148
+#define VI_SENSOR_CLK_REG_OFFSET 0x1a8
+#define VI_SENSOR2_CLK_REG_OFFSET 0x658
+#define VI_CLK_DIV_DEFAULT (0x12 << VCLK_DIV_SHIFT)
+#define G3D_CLK_REG_OFFSET 0x158
+#define G2D_CLK_REG_OFFSET 0x15c
+#define EPP_CLK_REG_OFFSET 0x16c
+#define MPE_CLK_REG_OFFSET 0x170
+#define VDE_CLK_REG_OFFSET 0x170
+#define G3D2_CLK_REG_OFFSET 0x3b0
+#define HDMI_AUDIO_CLK_REG_OFFSET 0x668
+#define HDMI_AUDIO_CLK_DIV_DEFAULT (0x12 << VCLK_DIV_SHIFT)
+#define CSITE_CLK_REG_OFFSET 0x1d4
+#define CSITE_CLK_DIV_DEFAULT (0x4 << VCLK_DIV_SHIFT)
+
+static void __init clk_setbit(u32 reg, u32 bit)
+{
+ u32 val = clk_readl(reg);
+
+ if ((val & bit) == bit)
+ return;
+ val |= bit;
+ clk_writel(val, reg);
+ udelay(2);
+}
+
+static void __init clk_clrbit(u32 reg, u32 bit)
+{
+ u32 val = clk_readl(reg);
+
+ if ((val & bit) == 0)
+ return;
+ val &= ~bit;
+ clk_writel(val, reg);
+ udelay(2);
+}
+
+static void __init clk_setbits(u32 reg, u32 bits, u32 mask)
+{
+ u32 val = clk_readl(reg);
+
+ if ((val & mask) == bits)
+ return;
+ val &= ~mask;
+ val |= bits;
+ clk_writel(val, reg);
+ udelay(2);
+}
+
+static void __init vclk_init(int tag, u32 src, u32 rebit)
+{
+ u32 rst, enb;
+
+ switch (tag) {
+ case 'L':
+ rst = RST_DEVICES_L;
+ enb = CLK_OUT_ENB_L;
+ break;
+ case 'H':
+ rst = RST_DEVICES_H;
+ enb = CLK_OUT_ENB_H;
+ break;
+ case 'U':
+ rst = RST_DEVICES_U;
+ enb = CLK_OUT_ENB_U;
+ break;
+ case 'V':
+ rst = RST_DEVICES_V;
+ enb = CLK_OUT_ENB_V;
+ break;
+ case 'W':
+ rst = RST_DEVICES_W;
+ enb = CLK_OUT_ENB_W;
+ break;
+ case 'X':
+ rst = RST_DEVICES_X;
+ enb = CLK_OUT_ENB_X;
+ break;
+ default:
+ /* Quietly ignore. */
+ return;
+ }
+
+ clk_setbit(rst, rebit);
+ clk_clrbit(enb, rebit);
+
+ clk_setbits(src, VCLK_SRC_DEFAULT, VCLK_SRC_MASK);
+ clk_setbits(src, VCLK_DIV_DEFAULT, VCLK_DIV_MASK);
+
+ clk_clrbit(rst, rebit);
+}
+
+static int __init tegra_soc_preinit_clocks(void)
+{
+ /*
+ * Make sure host1x clock configuration has:
+ * HOST1X_CLK_SRC : PLLP_OUT0.
+ * HOST1X_CLK_DIVISOR: >2 to start from safe enough frequency.
+ */
+ clk_setbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_HOST1X_BIT);
+ clk_setbit(CLK_OUT_ENB_L, CLK_RSTENB_DEV_L_0_HOST1X_BIT);
+ clk_setbits(HOST1X_CLK_REG_OFFSET,
+ HOST1X_CLK_DIV_DEFAULT, HOST1X_CLK_DIV_MASK);
+ clk_setbits(HOST1X_CLK_REG_OFFSET,
+ HOST1X_CLK_IDLE_DIV_DEFAULT, HOST1X_CLK_IDLE_DIV_MASK);
+ clk_setbits(HOST1X_CLK_REG_OFFSET,
+ HOST1X_CLK_SRC_DEFAULT, HOST1X_CLK_SRC_MASK);
+ clk_clrbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_HOST1X_BIT);
+
+ /*
+ * Make sure vi clock configuration has:
+ * VI_CLK_DIVISOR: 0x12
+ * VI_SENSOR_CLK_DIVISOR: 0x12
+ * VI_SENSOR2_CLK_DIVISOR: 0x12
+ */
+ clk_setbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_VI_BIT);
+ clk_setbit(CLK_OUT_ENB_L, CLK_RSTENB_DEV_L_0_VI_BIT);
+ clk_setbits(VI_CLK_REG_OFFSET,
+ VCLK_SRC_DEFAULT, VCLK_SRC_MASK);
+ clk_setbits(VI_CLK_REG_OFFSET, VI_CLK_DIV_DEFAULT, VCLK_DIV_MASK);
+ clk_setbits(VI_SENSOR_CLK_REG_OFFSET, VCLK_SRC_DEFAULT, VCLK_SRC_MASK);
+ clk_setbits(VI_SENSOR_CLK_REG_OFFSET,
+ VI_CLK_DIV_DEFAULT, VCLK_DIV_MASK);
+ clk_setbits(VI_SENSOR2_CLK_REG_OFFSET, VCLK_SRC_DEFAULT, VCLK_SRC_MASK);
+ clk_setbits(VI_SENSOR2_CLK_REG_OFFSET,
+ VI_CLK_DIV_DEFAULT, VCLK_DIV_MASK);
+ clk_clrbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_VI_BIT);
+
+ /*
+ * Make sure hdmi_audio clock configuration has:
+ * HDMI_AUDIO_CLK_DIVISOR: 0x12
+ */
+ clk_setbit(RST_DEVICES_X, CLK_RSTENB_DEV_X_0_HDMI_AUDIO_BIT);
+ clk_setbit(CLK_OUT_ENB_X, CLK_RSTENB_DEV_X_0_HDMI_AUDIO_BIT);
+ clk_setbits(HDMI_AUDIO_CLK_REG_OFFSET,
+ HDMI_AUDIO_CLK_DIV_DEFAULT, VCLK_DIV_MASK);
+ clk_clrbit(RST_DEVICES_X, CLK_RSTENB_DEV_X_0_HDMI_AUDIO_BIT);
+
+ /*
+ * Make sure csite clock configuration has:
+ * CSITE_CLK_DIVISOR: 0x4
+ */
+ clk_setbit(RST_DEVICES_U, CLK_RSTENB_DEV_U_0_CSITE_BIT);
+ clk_setbit(CLK_OUT_ENB_U, CLK_RSTENB_DEV_U_0_CSITE_BIT);
+ clk_setbits(CSITE_CLK_REG_OFFSET, CSITE_CLK_DIV_DEFAULT, VCLK_DIV_MASK);
+ clk_clrbit(RST_DEVICES_U, CLK_RSTENB_DEV_U_0_CSITE_BIT);
+
+ /* Pre-initialize Video clocks. */
+ vclk_init('L', G3D_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_3D_BIT);
+ vclk_init('L', G2D_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_2D_BIT);
+ vclk_init('L', ISP_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_ISP_BIT);
+ vclk_init('L', EPP_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_EPP_BIT);
+ vclk_init('H', VDE_CLK_REG_OFFSET, CLK_RSTENB_DEV_H_0_VDE_BIT);
+ vclk_init('H', MPE_CLK_REG_OFFSET, CLK_RSTENB_DEV_H_0_MPE_BIT);
+ vclk_init('V', G3D2_CLK_REG_OFFSET, CLK_RSTENB_DEV_V_0_3D2_BIT);
+
+ return 0;
+}
+#endif /* CONFIG_TEGRA_PREINIT_CLOCKS */
+
void __init tegra12x_init_clocks(void)
{
int i;
struct clk *c;
+
+#ifdef CONFIG_TEGRA_PREINIT_CLOCKS
+ tegra_soc_preinit_clocks();
+#endif /* CONFIG_TEGRA_PREINIT_CLOCKS */
+
for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
tegra12_init_one_clock(tegra_ptr_clks[i]);
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&tegra_clk_syscore_ops);
#endif
+
+}
+
+static int __init tegra12x_clk_late_init(void)
+{
+ clk_disable(&tegra_pll_re_vco);
+ return 0;
}
+late_initcall(tegra12x_clk_late_init);
Code Review / linux-3.10.git / blobdiff