#include <linux/cpufreq.h>
#include <linux/syscore_ops.h>
#include <linux/platform_device.h>
+#include <linux/tegra-soc.h>
#include <asm/clkdev.h>
#include <mach/edp.h>
-#include <mach/hardware.h>
#include <mach/mc.h>
#include "clock.h"
#include "tegra12_emc.h"
#include "tegra_cl_dvfs.h"
-/* FIXME: Disable for initial Si bringup */
-#undef USE_PLLE_SS
-#define USE_PLLE_SS 0
-
#define RST_DEVICES_L 0x004
#define RST_DEVICES_H 0x008
#define RST_DEVICES_U 0x00C
((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
#define SPARE_REG 0x55c
+#define SPARE_REG_CLK_M_DIVISOR_SHIFT 2
+#define SPARE_REG_CLK_M_DIVISOR_MASK (3 << SPARE_REG_CLK_M_DIVISOR_SHIFT)
+
#define PERIPH_CLK_SOURCE_XUSB_HOST 0x600
#define PERIPH_CLK_SOURCE_VIC 0x678
#define PERIPH_CLK_SOURCE_NUM4 \
((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
#define PLLCX_MISC_DIV_LOW_RANGE \
- ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
-#define PLLCX_MISC_DIV_HIGH_RANGE \
((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
+#define PLLCX_MISC_DIV_HIGH_RANGE \
+ ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
#define PLLCX_MISC_DEFAULT_VALUE ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \
PLLCX_MISC_KOEF_LOW_RANGE | \
#define PLLC_MISC1_DYNRAMP_DONE (0x1 << 0)
/* PLLM */
-#define PLLM_BASE_DIVP_MASK (0x1 << PLL_BASE_DIVP_SHIFT)
+#define PLLM_BASE_DIVP_MASK (0xF << PLL_BASE_DIVP_SHIFT)
#define PLLM_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
#define PLLM_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
-#define PLLM_PDIV_MAX 1
+
+/* PLLM has 4-bit PDIV, but entry 15 is not allowed in h/w,
+ and s/w usage is limited to 5 */
+#define PLLM_PDIV_MAX 14
+#define PLLM_SW_PDIV_MAX 5
#define PLLM_MISC_FSM_SW_OVERRIDE (0x1 << 10)
#define PLLM_MISC_IDDQ (0x1 << 5)
#define PMC_PLLM_WB0_OVERRIDE 0x1dc
#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
-#define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK (0x1 << 27)
+#define PMC_PLLM_WB0_OVERRIDE_2_DIVP_SHIFT 27
+#define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK (0xF << 27)
/* PLLSS */
#define PLLSS_CFG(c) ((c)->u.pll.misc1 + 0)
#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP (1 << 1)
#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP (1 << 3)
#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP (1 << 5)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN (1 << 24)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP (1 << 25)
#define UTMIP_PLL_CFG1 0x484
#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
#define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
#define PLLE_SS_INC_SHIFT 16
#define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
+#define PLLE_SS_CNTL_INVERT (0x1 << 15)
+#define PLLE_SS_CNTL_CENTER (0x1 << 14)
#define PLLE_SS_CNTL_SSC_BYP (0x1 << 12)
#define PLLE_SS_CNTL_INTERP_RESET (0x1 << 11)
#define PLLE_SS_CNTL_BYPASS_SS (0x1 << 10)
#define USB_PLLS_USE_LOCKDET (1<<6)
#define USB_PLLS_ENABLE_SWCTL ((1<<2) | (1<<0))
+/* XUSB PLL PAD controls */
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0 0x40
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_PWR_OVRD (1<<3)
+#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_IDDQ (1<<0)
+
+
/* DFLL */
#define DFLL_BASE 0x2f4
#define DFLL_BASE_RESET (1<<0)
#define ROUND_DIVIDER_DOWN 1
#define DIVIDER_1_5_ALLOWED 0
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
+#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
+#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
+
+#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
+#define CPU_RESET(cpu) (0x111001ul << (cpu))
+
/* PLLP default fixed rate in h/w controlled mode */
#define PLLP_DEFAULT_FIXED_RATE 408000000
static bool tegra12_is_dyn_ramp(struct clk *c,
unsigned long rate, bool from_vco_min);
static void tegra12_pllp_init_dependencies(unsigned long pllp_rate);
-static unsigned long tegra12_clk_shared_bus_update(
- struct clk *bus, struct clk **bus_top, struct clk **bus_slow);
+static unsigned long tegra12_clk_shared_bus_update(struct clk *bus,
+ struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap);
+static unsigned long tegra12_clk_cap_shared_bus(struct clk *bus,
+ unsigned long rate, unsigned long ceiling);
static bool detach_shared_bus;
module_param(detach_shared_bus, bool, 0644);
+/* Defines default range for dynamic frequency lock loop (DFLL)
+ to be used as CPU clock source:
+ "0" - DFLL is not used,
+ "1" - DFLL is used as a source for all CPU rates
+ "2" - DFLL is used only for high rates above crossover with PLL dvfs curve
+*/
static int use_dfll;
/**
static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
+static void __iomem *reg_xusb_padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
-#define MISC_GP_HIDREV 0x804
#define MISC_GP_TRANSACTOR_SCRATCH_0 0x864
#define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE (0x1 << 1)
#define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE (0x1 << 2)
__raw_writel(value,(void *)((u32)reg_pmc_base + (reg)))
#define pmc_readl(reg) \
__raw_readl((void *)((u32)reg_pmc_base + (reg)))
-#define chipid_readl() \
- __raw_readl((void *)((u32)misc_gp_base + MISC_GP_HIDREV))
+#define xusb_padctl_writel(value, reg) \
+ __raw_writel(value, reg_xusb_padctl_base + (reg))
+#define xusb_padctl_readl(reg) \
+ __raw_readl(reg_xusb_padctl_base + (reg))
#define clk_writel_delay(value, reg) \
do { \
- __raw_writel((value), (void *)((u32)reg_clk_base + (reg))); \
+ __raw_writel((value), reg_clk_base + (reg)); \
+ __raw_readl(reg_clk_base + (reg)); \
udelay(2); \
} while (0)
#define pll_writel_delay(value, reg) \
do { \
- __raw_writel((value), (void *)((u32)reg_clk_base + (reg))); \
+ __raw_writel((value), reg_clk_base + (reg)); \
+ __raw_readl(reg_clk_base + (reg)); \
udelay(1); \
} while (0)
u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
+ u32 spare = clk_readl(SPARE_REG);
+ u32 divisor = (spare & SPARE_REG_CLK_M_DIVISOR_MASK)
+ >> SPARE_REG_CLK_M_DIVISOR_SHIFT;
+ u32 spare_update = spare & ~SPARE_REG_CLK_M_DIVISOR_MASK;
+
c->rate = tegra_clk_measure_input_freq();
switch (c->rate) {
case 12000000:
auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+ BUG_ON(divisor != 0);
break;
case 13000000:
auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+ BUG_ON(divisor != 0);
break;
case 19200000:
auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+ BUG_ON(divisor != 0);
break;
case 26000000:
auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+ BUG_ON(divisor != 0);
break;
case 16800000:
auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+ BUG_ON(divisor != 0);
break;
case 38400000:
auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
+ BUG_ON(divisor != 1);
+ spare_update |= (1 << SPARE_REG_CLK_M_DIVISOR_SHIFT);
break;
case 48000000:
auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
+ BUG_ON(divisor != 3);
+ spare_update |= (3 << SPARE_REG_CLK_M_DIVISOR_SHIFT);
break;
case 115200: /* fake 13M for QT */
case 230400: /* fake 13M for QT */
auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
c->rate = 13000000;
BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+ BUG_ON(divisor != 0);
break;
default:
pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
BUG();
}
+
clk_writel(auto_clock_control, OSC_CTRL);
+ clk_writel(spare_update, SPARE_REG);
+
return c->rate;
}
c->mul = 2;
c->div = 2;
- /* Make sure 7.1 divider is 1:1, clear s/w skipper control */
- /* FIXME: set? preserve? thermal h/w skipper control */
+ /*
+ * Make sure 7.1 divider is 1:1; clear h/w skipper control -
+ * it will be enabled by soctherm later
+ */
val = clk_readl(c->reg + SUPER_CLK_DIVIDER);
BUG_ON(val & SUPER_CLOCK_DIV_U71_MASK);
val = 0;
/* On SILICON allow CPU rate change only if cpu regulator is connected.
Ignore regulator connection on FPGA and SIMULATION platforms. */
-#ifdef CONFIG_TEGRA_SILICON_PLATFORM
- if (c->dvfs) {
+ if (c->dvfs && tegra_platform_is_silicon()) {
if (!c->dvfs->dvfs_rail)
return -ENOSYS;
- else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate)) {
+ else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate) &&
+ (c->boot_rate < rate)) {
WARN(1, "Increasing CPU rate while regulator is not"
" ready is not allowed\n");
return -ENOSYS;
}
}
-#endif
if (has_dfll && c->dvfs && c->dvfs->dvfs_rail) {
if (tegra_dvfs_is_dfll_range(c->dvfs, rate))
return tegra12_cpu_clk_dfll_on(c, rate, old_rate);
};
/* bus clock functions */
+static DEFINE_SPINLOCK(bus_clk_lock);
+
+static int bus_set_div(struct clk *c, int div)
+{
+ u32 val;
+ unsigned long flags;
+
+ if (!div || (div > (BUS_CLK_DIV_MASK + 1)))
+ return -EINVAL;
+
+ spin_lock_irqsave(&bus_clk_lock, flags);
+ val = clk_readl(c->reg);
+ val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
+ val |= (div - 1) << c->reg_shift;
+ clk_writel(val, c->reg);
+ c->div = div;
+ spin_unlock_irqrestore(&bus_clk_lock, flags);
+
+ return 0;
+}
+
static void tegra12_bus_clk_init(struct clk *c)
{
u32 val = clk_readl(c->reg);
static int tegra12_bus_clk_set_rate(struct clk *c, unsigned long rate)
{
- u32 val = clk_readl(c->reg);
unsigned long parent_rate = clk_get_rate(c->parent);
int i;
if (tegra_platform_is_qt())
return 0;
for (i = 1; i <= 4; i++) {
- if (rate >= parent_rate / i) {
- val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
- val |= (i - 1) << c->reg_shift;
- clk_writel(val, c->reg);
- c->div = i;
- c->mul = 1;
- return 0;
- }
+ if (rate >= parent_rate / i)
+ return bus_set_div(c, i);
}
return -EINVAL;
}
* recursive calls. Lost 1Hz is added in tegra12_sbus_cmplx_set_rate before
* actually setting divider rate.
*/
-static long tegra12_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
+static long tegra12_sbus_cmplx_round_updown(struct clk *c, unsigned long rate,
+ bool up)
{
int divider;
unsigned long source_rate, round_rate;
source_rate = clk_get_rate(new_parent->parent);
divider = clk_div71_get_divider(source_rate, rate,
- new_parent->flags, ROUND_DIVIDER_DOWN);
+ new_parent->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
if (divider < 0)
- return divider;
+ return c->min_rate;
if (divider == 1)
divider = 0;
return round_rate;
}
+static long tegra12_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
+{
+ return tegra12_sbus_cmplx_round_updown(c, rate, true);
+}
+
+/*
+ * FIXME: This limitation may have been relaxed on Tegra12.
+ * This issue has to be visited again once the new limitation is clarified.
+ *
+ * Limitations on SCLK/HCLK/PCLK dividers:
+ * (A) H/w limitation:
+ * if SCLK >= 60MHz, SCLK:PCLK >= 2
+ * (B) S/w policy limitation, in addition to (A):
+ * if any APB bus shared user request is enabled, HCLK:PCLK >= 2
+ * Reason for (B): assuming APB bus shared user has requested X < 60MHz,
+ * HCLK = PCLK = X, and new AHB user is coming on-line requesting Y >= 60MHz,
+ * we can consider 2 paths depending on order of changing HCLK rate and
+ * HCLK:PCLK ratio
+ * (i) HCLK:PCLK = X:X => Y:Y* => Y:Y/2, (*) violates rule (A)
+ * (ii) HCLK:PCLK = X:X => X:X/2* => Y:Y/2, (*) under-clocks APB user
+ * In this case we can not guarantee safe transition from HCLK:PCLK = 1:1
+ * below 60MHz to HCLK rate above 60MHz without under-clocking APB user.
+ * Hence, policy (B).
+ *
+ * Note: when there are no request from APB users, path (ii) can be used to
+ * increase HCLK above 60MHz, and HCLK:PCLK = 1:1 is allowed.
+ */
+
+#define SCLK_PCLK_UNITY_RATIO_RATE_MAX 60000000
+#define BUS_AHB_DIV_MAX (BUS_CLK_DIV_MASK + 1UL)
+#define BUS_APB_DIV_MAX (BUS_CLK_DIV_MASK + 1UL)
+
static int tegra12_sbus_cmplx_set_rate(struct clk *c, unsigned long rate)
{
int ret;
struct clk *new_parent;
- /* - select the appropriate sclk parent
- - keep hclk at the same rate as sclk
- - set pclk at 1:2 rate of hclk unless pclk minimum is violated,
- in the latter case switch to 1:1 ratio */
+ /*
+ * Configure SCLK/HCLK/PCLK guranteed safe combination:
+ * - select the appropriate sclk parent
+ * - keep hclk at the same rate as sclk
+ * - set pclk at 1:2 rate of hclk
+ */
+ bus_set_div(c->u.system.pclk, 2);
+ bus_set_div(c->u.system.hclk, 1);
+ c->child_bus->child_bus->div = 2;
+ c->child_bus->div = 1;
- if (rate >= c->u.system.pclk->min_rate * 2) {
- ret = clk_set_div(c->u.system.pclk, 2);
- if (ret) {
- pr_err("Failed to set 1 : 2 pclk divider\n");
- return ret;
- }
- }
+ if (rate == clk_get_rate_locked(c))
+ return 0;
new_parent = (rate <= c->u.system.threshold) ?
c->u.system.sclk_low : c->u.system.sclk_high;
}
}
- if (rate < c->u.system.pclk->min_rate * 2) {
- ret = clk_set_div(c->u.system.pclk, 1);
- if (ret) {
- pr_err("Failed to set 1 : 1 pclk divider\n");
- return ret;
- }
- }
-
return 0;
}
static int tegra12_clk_sbus_update(struct clk *bus)
{
- unsigned long rate, old_rate;
+ int ret, div;
+ bool p_requested;
+ unsigned long s_rate, h_rate, p_rate, ceiling;
+ struct clk *ahb, *apb;
if (detach_shared_bus)
return 0;
- rate = tegra12_clk_shared_bus_update(bus, NULL, NULL);
- rate = clk_round_rate_locked(bus, rate);
+ s_rate = tegra12_clk_shared_bus_update(bus, &ahb, &apb, &ceiling);
+ if (bus->override_rate)
+ return clk_set_rate_locked(bus, s_rate);
+
+ ahb = bus->child_bus;
+ apb = ahb->child_bus;
+ h_rate = ahb->u.shared_bus_user.rate;
+ p_rate = apb->u.shared_bus_user.rate;
+ p_requested = apb->refcnt > 1;
+
+ /* Propagate ratio requirements up from PCLK to SCLK */
+ if (p_requested)
+ h_rate = max(h_rate, p_rate * 2);
+ s_rate = max(s_rate, h_rate);
+ if (s_rate >= SCLK_PCLK_UNITY_RATIO_RATE_MAX)
+ s_rate = max(s_rate, p_rate * 2);
+
+ /* Propagate cap requirements down from SCLK to PCLK */
+ s_rate = tegra12_clk_cap_shared_bus(bus, s_rate, ceiling);
+ if (s_rate >= SCLK_PCLK_UNITY_RATIO_RATE_MAX)
+ p_rate = min(p_rate, s_rate / 2);
+ h_rate = min(h_rate, s_rate);
+ if (p_requested)
+ p_rate = min(p_rate, h_rate / 2);
+
+
+ /* Set new sclk rate in safe 1:1:2, rounded "up" configuration */
+ ret = clk_set_rate_locked(bus, s_rate);
+ if (ret)
+ return ret;
- old_rate = clk_get_rate_locked(bus);
- if (rate == old_rate)
- return 0;
+ /* Finally settle new bus divider values */
+ s_rate = clk_get_rate_locked(bus);
+ div = min(s_rate / h_rate, BUS_AHB_DIV_MAX);
+ if (div != 1) {
+ bus_set_div(bus->u.system.hclk, div);
+ ahb->div = div;
+ }
- return clk_set_rate_locked(bus, rate);
+ h_rate = clk_get_rate(bus->u.system.hclk);
+ div = min(h_rate / p_rate, BUS_APB_DIV_MAX);
+ if (div != 2) {
+ bus_set_div(bus->u.system.pclk, div);
+ apb->div = div;
+ }
+
+ return 0;
}
static struct clk_ops tegra_sbus_cmplx_ops = {
.init = tegra12_sbus_cmplx_init,
.set_rate = tegra12_sbus_cmplx_set_rate,
.round_rate = tegra12_sbus_cmplx_round_rate,
+ .round_rate_updown = tegra12_sbus_cmplx_round_updown,
.shared_bus_update = tegra12_clk_sbus_update,
};
static int tegra12_pll_clk_wait_for_lock(
struct clk *c, u32 lock_reg, u32 lock_bits)
{
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
#if USE_PLL_LOCK_BITS
int i;
+ u32 val = 0;
+
for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) {
udelay(PLL_PRE_LOCK_DELAY);
- if ((clk_readl(lock_reg) & lock_bits) == lock_bits) {
+ val = clk_readl(lock_reg);
+ if ((val & lock_bits) == lock_bits) {
udelay(PLL_POST_LOCK_DELAY);
return 0;
}
}
- pr_err("Timed out waiting for lock bit on pll %s\n", c->name);
- return -1;
+
+ /* PLLCX lock bits may fluctuate after the lock - do detailed reporting
+ at debug level (phase lock bit happens to uniquely identify PLLCX) */
+ if (lock_bits & PLLCX_BASE_PHASE_LOCK) {
+ pr_debug("Timed out waiting %s locks: %s %s not set\n", c->name,
+ val & PLL_BASE_LOCK ? "" : "frequency_lock",
+ val & PLLCX_BASE_PHASE_LOCK ? "" : "phase_lock");
+ pr_debug("base = 0x%x\n", val);
+ pr_debug("misc = 0x%x\n", clk_readl(c->reg + PLL_MISC(c)));
+ pr_debug("misc1 = 0x%x\n", clk_readl(c->reg + PLL_MISCN(c, 1)));
+ pr_debug("misc2 = 0x%x\n", clk_readl(c->reg + PLL_MISCN(c, 2)));
+ pr_debug("misc3 = 0x%x\n", clk_readl(c->reg + PLL_MISCN(c, 3)));
+ return -ETIMEDOUT;
+ } else {
+ pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+ c->name, lock_reg, val);
+ return -ETIMEDOUT;
+ }
#endif
udelay(c->u.pll.lock_delay);
-#endif
return 0;
}
utmi_parameters[i].active_delay_count);
/* Remove power downs from UTMIP PLL control bits */
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP;
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
+ reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
clk_writel(reg, UTMIP_PLL_CFG2);
ports are assigned to USB2 */
reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
- reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
+ reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
udelay(1);
val = clk_readl(c->reg + PLL_BASE);
val &= ~PLLU_BASE_OVERRIDE;
clk_writel(val, c->reg + PLL_BASE);
+
+ /* Set XUSB PLL pad pwr override and iddq */
+ val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
+ val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_PWR_OVRD;
+ val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_IDDQ;
+ xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
}
}
clk_writel(val, c->reg);
}
+/* Special comparison frequency selection for PLLD at 12MHz refrence rate */
+unsigned long get_pll_cfreq_special(struct clk *c, unsigned long input_rate,
+ unsigned long rate, unsigned long *vco)
+{
+ if (!(c->flags & PLLD) || (input_rate != 12000000))
+ return 0;
+
+ *vco = c->u.pll.vco_min;
+
+ if (rate <= 250000000)
+ return 4000000;
+ else if (rate <= 500000000)
+ return 2000000;
+ else
+ return 1000000;
+}
+
+/* Common comparison frequency selection */
+unsigned long get_pll_cfreq_common(struct clk *c, unsigned long input_rate,
+ unsigned long rate, unsigned long *vco)
+{
+ unsigned long cfreq = 0;
+
+ switch (input_rate) {
+ case 12000000:
+ case 26000000:
+ cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
+ break;
+ case 13000000:
+ cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
+ break;
+ case 16800000:
+ case 19200000:
+ cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
+ break;
+ default:
+ if (c->parent->flags & DIV_U71_FIXED) {
+ /* PLLP_OUT1 rate is not in PLLA table */
+ pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
+ __func__, c->name, input_rate, rate);
+ cfreq = input_rate/(input_rate/1000000);
+ break;
+ }
+ pr_err("%s: Unexpected reference rate %lu\n",
+ __func__, input_rate);
+ BUG();
+ }
+
+ /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */
+ *vco = max(200 * cfreq, c->u.pll.vco_min);
+ return cfreq;
+}
+
+static u8 get_pll_cpcon(struct clk *c, u16 n)
+{
+ if (c->flags & PLLD) {
+ if (n >= 1000)
+ return 15;
+ else if (n >= 600)
+ return 12;
+ else if (n >= 300)
+ return 8;
+ else if (n >= 50)
+ return 3;
+ else
+ return 2;
+ }
+ return c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
+}
+
static int tegra12_pll_clk_set_rate(struct clk *c, unsigned long rate)
{
u32 val, p_div, old_base;
BUG_ON(c->flags & PLLU);
sel = &cfg;
- switch (input_rate) {
- case 12000000:
- case 26000000:
- cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
- break;
- case 13000000:
- cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
- break;
- case 16800000:
- case 19200000:
- cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
- break;
- default:
- if (c->parent->flags & DIV_U71_FIXED) {
- /* PLLP_OUT1 rate is not in PLLA table */
- pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
- __func__, c->name, input_rate, rate);
- cfreq = input_rate/(input_rate/1000000);
- break;
- }
- pr_err("%s: Unexpected reference rate %lu\n",
- __func__, input_rate);
- BUG();
- }
+ /* If available, use pll specific algorithm to select comparison
+ frequency, and vco target */
+ cfreq = get_pll_cfreq_special(c, input_rate, rate, &vco);
+ if (!cfreq)
+ cfreq = get_pll_cfreq_common(c, input_rate, rate, &vco);
- /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */
- vco = max(200 * cfreq, c->u.pll.vco_min);
for (cfg.output_rate = rate; cfg.output_rate < vco; p_div++)
cfg.output_rate <<= 1;
cfg.p = 0x1 << p_div;
cfg.m = input_rate / cfreq;
cfg.n = cfg.output_rate / cfreq;
- cfg.cpcon = c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
+ cfg.cpcon = get_pll_cpcon(c, cfg.n);
if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
(cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
static void pllcx_set_defaults(struct clk *c, unsigned long input_rate, u32 n)
{
u32 misc1val = PLLCX_MISC1_DEFAULT_VALUE;
- if (c->state == ON) {
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
- BUG();
-#endif
- } else {
+ if (c->state == ON)
+ BUG_ON(!tegra_platform_is_linsim());
+ else
misc1val |= PLLCX_MISC1_IDDQ;
- }
clk_writel(PLLCX_MISC_DEFAULT_VALUE, c->reg + PLL_MISC(c));
clk_writel(misc1val, c->reg + PLL_MISCN(c, 1));
* and no enabled module clocks should use it as a source during clock
* init.
*/
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
- BUG_ON(c->state == ON);
-#endif
+ BUG_ON(c->state == ON && !tegra_platform_is_linsim());
/*
* Most of PLLCX register fields are shadowed, and can not be read
* directly from PLL h/w. Hence, actual PLLCX boot state is unknown.
/* Only s/w dyn ramp control is supported */
val = clk_readl(PLLX_HW_CTRL_CFG);
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
- BUG_ON(!(val & PLLX_HW_CTRL_CFG_SWCTRL));
-#endif
+ BUG_ON(!(val & PLLX_HW_CTRL_CFG_SWCTRL) && !tegra_platform_is_linsim());
pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b);
val = step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
/* Check/set IDDQ */
val = clk_readl(c->reg + PLL_MISCN(c, 3));
if (c->state == ON) {
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
- BUG_ON(val & PLLX_MISC3_IDDQ);
-#endif
+ BUG_ON(val & PLLX_MISC3_IDDQ && !tegra_platform_is_linsim());
} else {
val |= PLLX_MISC3_IDDQ;
clk_writel(val, c->reg + PLL_MISCN(c, 3));
clk_writel(val, c->reg + PLL_MISC(c));
if (c->state == ON) {
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
- BUG_ON(val & PLLC_MISC_IDDQ);
-#endif
+ BUG_ON(val & PLLC_MISC_IDDQ && !tegra_platform_is_linsim());
} else {
val |= PLLC_MISC_IDDQ;
clk_writel(val, c->reg + PLL_MISC(c));
/* FIXME: pllm suspend/resume */
+/* non-monotonic mapping below is not a typo */
+static u8 pllm_p[PLLM_PDIV_MAX + 1] = {
+/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
+/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
+
static u32 pllm_round_p_to_pdiv(u32 p, u32 *pdiv)
{
- if (!p || (p > 2))
+ if (!p || (p > PLLM_SW_PDIV_MAX + 1))
return -EINVAL;
if (pdiv)
if (c->state != ON)
val |= PLLM_MISC_IDDQ;
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
else
- BUG_ON(val & PLLM_MISC_IDDQ);
-#endif
+ BUG_ON(val & PLLM_MISC_IDDQ && !tegra_platform_is_linsim());
clk_writel(val, c->reg + PLL_MISC(c));
}
c->u.pll.vco_min =
DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
c->min_rate =
- DIV_ROUND_UP(c->u.pll.vco_min, 2);
+ DIV_ROUND_UP(c->u.pll.vco_min, pllm_p[PLLM_SW_PDIV_MAX]);
val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
c->state = (val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE) ? ON : OFF;
+
+ /* Tegra12 has bad default value of PMC_PLLM_WB0_OVERRIDE.
+ * If bootloader does not initialize PLLM, kernel has to
+ * initialize the register with sane value. */
+ if (c->state == OFF) {
+ val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
+ m = (val & PLLM_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+ if (m != PLL_FIXED_MDIV(c, input_rate)) {
+ /* Copy DIVM and DIVN from PLLM_BASE */
+ pr_info("%s: Fixing DIVM and DIVN\n", __func__);
+ val = clk_readl(c->reg + PLL_BASE);
+ val &= (PLLM_BASE_DIVM_MASK
+ | PLLM_BASE_DIVN_MASK);
+ pmc_writel(val, PMC_PLLM_WB0_OVERRIDE);
+ }
+ }
+
val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2);
- p = (val & PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) ? 2 : 1;
+ p = (val & PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) >>
+ PMC_PLLM_WB0_OVERRIDE_2_DIVP_SHIFT;
val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
} else {
val = clk_readl(c->reg + PLL_BASE);
c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
- p = (val & PLLM_BASE_DIVP_MASK) ? 2 : 1;
+ p = (val & PLLM_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT;
}
m = (val & PLLM_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
-#ifdef CONFIG_TEGRA_SILICON_PLATFORM
- BUG_ON(m != PLL_FIXED_MDIV(c, input_rate));
-#endif
- c->div = m * p;
+ BUG_ON(m != PLL_FIXED_MDIV(c, input_rate)
+ && tegra_platform_is_silicon());
+ c->div = m * pllm_p[p];
c->mul = (val & PLLM_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
pllm_set_defaults(c, input_rate);
val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2);
- val = pdiv ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) :
- (val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK);
+ val &= ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK;
+ val |= pdiv << PMC_PLLM_WB0_OVERRIDE_2_DIVP_SHIFT;
pmc_writel(val, PMC_PLLM_WB0_OVERRIDE_2);
val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
PLLM_BASE_DIVP_MASK);
val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
(sel->n << PLL_BASE_DIVN_SHIFT) |
- (pdiv ? PLLM_BASE_DIVP_MASK : 0);
+ (pdiv << PLL_BASE_DIVP_SHIFT);
clk_writel(val, c->reg + PLL_BASE);
}
val = clk_readl(c->reg + PLL_BASE);
if (c->state != ON)
val |= PLLSS_BASE_IDDQ;
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
else
- BUG_ON(val & PLLSS_BASE_IDDQ);
-#endif
+ BUG_ON(val & PLLSS_BASE_IDDQ && !tegra_platform_is_linsim());
val &= ~PLLSS_BASE_LOCK_OVERRIDE;
clk_writel(val, c->reg + PLL_BASE);
}
c->min_rate =
DIV_ROUND_UP(c->u.pll.vco_min, pllss_p[PLLSS_SW_PDIV_MAX]);
+ /* Assuming bootloader does not initialize these PLLs */
+ n = (val & PLLSS_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+ BUG_ON(n > 1);
+
+ /* Reset default value of those PLLs are not safe.
+ For example, they cause problem in LP0 resume.
+ Replace them here with the safe value. */
+ m = PLL_FIXED_MDIV(c, input_rate);
+ n = c->u.pll.vco_min / input_rate * m;
+ p_div = PLLSS_SW_PDIV_MAX;
+ val &= ~PLLSS_BASE_DIVM_MASK;
+ val &= ~PLLSS_BASE_DIVN_MASK;
+ val &= ~PLLSS_BASE_DIVP_MASK;
+ val |= m << PLL_BASE_DIVM_SHIFT;
+ val |= n << PLL_BASE_DIVN_SHIFT;
+ val |= p_div << PLL_BASE_DIVP_SHIFT;
+ clk_writel(val, c->reg + PLL_BASE);
+
c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
m = (val & PLLSS_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
| (sel->n << PLL_BASE_DIVN_SHIFT)
| (pdiv << PLL_BASE_DIVP_SHIFT);
- /* FIXME: hack for bringup */
- pr_info("%s: val=%08x m=%d n=%d pdiv=%d input_rate=%lu\n",
- c->name, val, sel->m, sel->n, pdiv, input_rate);
-
if (val == old_base)
return 0;
if (c->state != ON)
val |= PLLRE_MISC_IDDQ;
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
else
- BUG_ON(val & PLLRE_MISC_IDDQ);
-#endif
+ BUG_ON(val & PLLRE_MISC_IDDQ && !tegra_platform_is_linsim());
clk_writel(val, c->reg + PLL_MISC(c));
}
val = clk_readl(c->reg + PLL_MISC(c));
val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
pll_writel_delay(val, c->reg + PLL_MISC(c));
+
+ /* Set XUSB PLL pad pwr override and iddq */
+ val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
+ val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_PWR_OVRD;
+ val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_IDDQ;
+ xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
+
}
static int tegra12_plle_clk_enable(struct clk *c)
c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
#if USE_PLLE_SS
val = clk_readl(PLLE_SS_CTRL);
+ val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
val &= ~PLLE_SS_COEFFICIENTS_MASK;
val |= PLLE_SS_COEFFICIENTS_VAL;
clk_writel(val, PLLE_SS_CTRL);
val |= PLLE_AUX_SEQ_ENABLE;
pll_writel_delay(val, PLLE_AUX);
#endif
+
+ /* clear XUSB PLL pad pwr override and iddq */
+ val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
+ val &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_PWR_OVRD;
+ val &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_IDDQ;
+ xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
+
/* enable hw control of xusb brick pll */
usb_plls_hw_control_enable(XUSBIO_PLL_CFG0);
if (!ret) {
c->state = OFF;
c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device);
-
- use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
+ if (tegra_platform_is_silicon())
+ use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll);
tegra_cl_dvfs_debug_init(c);
- pr_info("Tegra CPU DFLL is initialized\n");
+ pr_info("Tegra CPU DFLL is initialized with use_dfll = %d\n", use_dfll);
}
#endif
}
static void tegra12_pll_div_clk_init(struct clk *c)
{
if (c->flags & DIV_U71) {
- u32 divu71;
- u32 val = clk_readl(c->reg);
+ u32 val, divu71;
+ if (c->parent->state == OFF)
+ c->ops->disable(c);
+
+ val = clk_readl(c->reg);
val >>= c->reg_shift;
c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
if (!(val & PLL_OUT_RESET_DISABLE))
{
if (c->u.periph.src_mask)
return c->u.periph.src_mask;
- else if (c->flags & MUX8)
- return 7 << 29;
else if (c->flags & MUX_PWM)
return 3 << 28;
else if (c->flags & MUX_CLK_OUT)
else if (c->flags & PLLD)
return PLLD_BASE_DSI_MUX_MASK;
else
- return 3 << 30;
+ return 7 << 29;
}
static inline u32 periph_clk_source_shift(struct clk *c)
{
if (c->u.periph.src_shift)
return c->u.periph.src_shift;
- else if (c->flags & MUX8)
- return 29;
else if (c->flags & MUX_PWM)
return 28;
else if (c->flags & MUX_CLK_OUT)
else if (c->flags & PLLD)
return PLLD_BASE_DSI_MUX_SHIFT;
else
- return 30;
+ return 29;
}
static void tegra12_periph_clk_init(struct clk *c)
c->parent = mux->input;
} else {
if (c->flags & PLLU) {
- /* for xusb_hs clock enforce PLLU source during init */
- val &= periph_clk_source_mask(c);
- val |= c->inputs[0].value << periph_clk_source_shift(c);
+ /* for xusb_hs clock enforce SS div2 source */
+ val &= ~periph_clk_source_mask(c);
clk_writel_delay(val, c->reg);
}
c->parent = c->inputs[0].input;
}
+ /* if peripheral is left under reset - enforce safe rate */
+ if (!(c->flags & PERIPH_NO_RESET) &&
+ (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))) {
+ tegra_periph_clk_safe_rate_init(c);
+ val = clk_readl(c->reg);
+ }
+
if (c->flags & DIV_U71) {
u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
if (c->flags & DIV_U71_IDLE) {
clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) {
if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) {
- udelay(5); /* reset propagation delay */
+ udelay(RESET_PROPAGATION_DELAY);
clk_writel(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_RST_CLR_REG(c));
}
}
* flush the write operation in apb bus. This will avoid the
* peripheral access after disabling clock*/
if (c->flags & PERIPH_ON_APB)
- val = chipid_readl();
+ val = tegra_read_chipid();
clk_writel_delay(
PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
* will avoid the peripheral access after disabling
* clock */
if (c->flags & PERIPH_ON_APB)
- val = chipid_readl();
+ val = tegra_read_chipid();
clk_writel(PERIPH_CLK_TO_BIT(c),
PERIPH_CLK_TO_RST_SET_REG(c));
.reset = &tegra12_periph_clk_reset,
};
+/* 1x shared bus ops */
+static long _1x_round_updown(struct clk *c, struct clk *src,
+ unsigned long rate, bool up)
+{
+ int divider;
+ unsigned long source_rate, round_rate;
+
+ source_rate = clk_get_rate(src);
+
+ divider = clk_div71_get_divider(source_rate, rate + (up ? -1 : 1),
+ c->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
+
+ if (divider < 0)
+ return c->min_rate;
+
+ round_rate = source_rate * 2 / (divider + 2);
+
+ if (round_rate > c->max_rate) {
+ divider += c->flags & DIV_U71_INT ? 2 : 1;
+#if !DIVIDER_1_5_ALLOWED
+ divider = max(2, divider);
+#endif
+ round_rate = source_rate * 2 / (divider + 2);
+ }
+ return round_rate;
+}
+
+static long tegra12_1xbus_round_updown(struct clk *c, unsigned long rate,
+ bool up)
+{
+ unsigned long pll_low_rate, pll_high_rate;
+
+ rate = max(rate, c->min_rate);
+
+ pll_low_rate = _1x_round_updown(c, c->u.periph.pll_low, rate, up);
+ if (rate <= c->u.periph.threshold) {
+ c->u.periph.pll_selected = c->u.periph.pll_low;
+ return pll_low_rate;
+ }
+
+ pll_high_rate = _1x_round_updown(c, c->u.periph.pll_high, rate, up);
+ if (pll_high_rate <= c->u.periph.threshold) {
+ c->u.periph.pll_selected = c->u.periph.pll_low;
+ return pll_low_rate; /* prevent oscillation across threshold */
+ }
+
+ if (up) {
+ /* rounding up: both plls may hit max, and round down */
+ if (pll_high_rate < rate) {
+ if (pll_low_rate < pll_high_rate) {
+ c->u.periph.pll_selected = c->u.periph.pll_high;
+ return pll_high_rate;
+ }
+ } else {
+ if ((pll_low_rate < rate) ||
+ (pll_low_rate > pll_high_rate)) {
+ c->u.periph.pll_selected = c->u.periph.pll_high;
+ return pll_high_rate;
+ }
+ }
+ } else if (pll_low_rate < pll_high_rate) {
+ /* rounding down: to get here both plls able to round down */
+ c->u.periph.pll_selected = c->u.periph.pll_high;
+ return pll_high_rate;
+ }
+ c->u.periph.pll_selected = c->u.periph.pll_low;
+ return pll_low_rate;
+}
+
+static long tegra12_1xbus_round_rate(struct clk *c, unsigned long rate)
+{
+ return tegra12_1xbus_round_updown(c, rate, true);
+}
+
+static int tegra12_1xbus_set_rate(struct clk *c, unsigned long rate)
+{
+ /* Compensate rate truncating during rounding */
+ return tegra12_periph_clk_set_rate(c, rate + 1);
+}
+
+static int tegra12_clk_1xbus_update(struct clk *c)
+{
+ int ret;
+ struct clk *new_parent;
+ unsigned long rate, old_rate;
+
+ if (detach_shared_bus)
+ return 0;
+
+ rate = tegra12_clk_shared_bus_update(c, NULL, NULL, NULL);
+
+ old_rate = clk_get_rate_locked(c);
+ pr_debug("\n1xbus %s: rate %lu on parent %s: new request %lu\n",
+ c->name, old_rate, c->parent->name, rate);
+ if (rate == old_rate)
+ return 0;
+
+ if (!c->u.periph.min_div_low || !c->u.periph.min_div_high) {
+ unsigned long r, m = c->max_rate;
+ r = clk_get_rate(c->u.periph.pll_low);
+ c->u.periph.min_div_low = DIV_ROUND_UP(r, m) * c->mul;
+ r = clk_get_rate(c->u.periph.pll_high);
+ c->u.periph.min_div_high = DIV_ROUND_UP(r, m) * c->mul;
+ }
+
+ new_parent = c->u.periph.pll_selected;
+
+ /*
+ * The transition procedure below is guaranteed to switch to the target
+ * parent/rate without violation of max clock limits. It would attempt
+ * to switch without dip in bus rate if it is possible, but this cannot
+ * be guaranteed (example: switch from 408 MHz : 1 to 624 MHz : 2 with
+ * maximum bus limit 408 MHz will be executed as 408 => 204 => 312 MHz,
+ * and there is no way to avoid rate dip in this case).
+ */
+ if (new_parent != c->parent) {
+ int interim_div = 0;
+ /* Switching to pll_high may over-clock bus if current divider
+ is too small - increase divider to safe value */
+ if ((new_parent == c->u.periph.pll_high) &&
+ (c->div < c->u.periph.min_div_high))
+ interim_div = c->u.periph.min_div_high;
+
+ /* Switching to pll_low may dip down rate if current divider
+ is too big - decrease divider as much as we can */
+ if ((new_parent == c->u.periph.pll_low) &&
+ (c->div > c->u.periph.min_div_low) &&
+ (c->div > c->u.periph.min_div_high))
+ interim_div = c->u.periph.min_div_low;
+
+ if (interim_div) {
+ u64 interim_rate = old_rate * c->div;
+ do_div(interim_rate, interim_div);
+ ret = clk_set_rate_locked(c, interim_rate);
+ if (ret) {
+ pr_err("Failed to set %s rate to %lu\n",
+ c->name, (unsigned long)interim_rate);
+ return ret;
+ }
+ pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
+ clk_get_rate_locked(c), c->parent->name);
+ }
+
+ ret = clk_set_parent_locked(c, new_parent);
+ if (ret) {
+ pr_err("Failed to set %s parent %s\n",
+ c->name, new_parent->name);
+ return ret;
+ }
+
+ old_rate = clk_get_rate_locked(c);
+ pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
+ old_rate, c->parent->name);
+ if (rate == old_rate)
+ return 0;
+ }
+
+ ret = clk_set_rate_locked(c, rate);
+ if (ret) {
+ pr_err("Failed to set %s rate to %lu\n", c->name, rate);
+ return ret;
+ }
+ pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
+ clk_get_rate_locked(c), c->parent->name);
+ return 0;
+
+}
+
+static struct clk_ops tegra_1xbus_clk_ops = {
+ .init = &tegra12_periph_clk_init,
+ .enable = &tegra12_periph_clk_enable,
+ .disable = &tegra12_periph_clk_disable,
+ .set_parent = &tegra12_periph_clk_set_parent,
+ .set_rate = &tegra12_1xbus_set_rate,
+ .round_rate = &tegra12_1xbus_round_rate,
+ .round_rate_updown = &tegra12_1xbus_round_updown,
+ .reset = &tegra12_periph_clk_reset,
+ .shared_bus_update = &tegra12_clk_1xbus_update,
+};
-#if !defined(CONFIG_TEGRA_SIMULATION_PLATFORM)
/* msenc clock propagation WAR for bug 1005168 */
static int tegra12_msenc_clk_enable(struct clk *c)
{
.round_rate = &tegra12_periph_clk_round_rate,
.reset = &tegra12_periph_clk_reset,
};
-#endif
/* Periph extended clock configuration ops */
static int
tegra12_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
};
/* pciex clock support only reset function */
-static struct clk_ops tegra_pciex_clk_ops = {
- .reset = tegra12_periph_clk_reset,
-};
+static void tegra12_pciex_clk_init(struct clk *c)
+{
+ c->state = c->parent->state;
+}
-/* Output clock ops */
+static int tegra12_pciex_clk_enable(struct clk *c)
+{
+ return 0;
+}
+
+static void tegra12_pciex_clk_disable(struct clk *c)
+{
+}
+
+static int tegra12_pciex_clk_set_rate(struct clk *c, unsigned long rate)
+{
+ unsigned long parent_rate = clk_get_rate(c->parent);
+
+ /*
+ * the only supported pcie configurations:
+ * Gen1: plle = 100MHz, link at 250MHz
+ * Gen2: plle = 100MHz, link at 500MHz
+ */
+ if (parent_rate == 100000000) {
+ if (rate == 500000000) {
+ c->mul = 5;
+ c->div = 1;
+ return 0;
+ } else if (rate == 250000000) {
+ c->mul = 5;
+ c->div = 2;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static struct clk_ops tegra_pciex_clk_ops = {
+ .init = tegra12_pciex_clk_init,
+ .enable = tegra12_pciex_clk_enable,
+ .disable = tegra12_pciex_clk_disable,
+ .set_rate = tegra12_pciex_clk_set_rate,
+ .reset = tegra12_periph_clk_reset,
+};
+
+/* Output clock ops */
static DEFINE_SPINLOCK(clk_out_lock);
c->max_rate = clk_get_rate(c->parent);
}
-static long tegra12_emc_clk_round_rate(struct clk *c, unsigned long rate)
+static long tegra12_emc_clk_round_updown(struct clk *c, unsigned long rate,
+ bool up)
{
- long new_rate = max(rate, c->min_rate);
+ unsigned long new_rate = max(rate, c->min_rate);
- new_rate = tegra_emc_round_rate(new_rate);
- if (new_rate < 0)
+ new_rate = tegra_emc_round_rate_updown(new_rate, up);
+ if (IS_ERR_VALUE(new_rate))
new_rate = c->max_rate;
return new_rate;
}
+static long tegra12_emc_clk_round_rate(struct clk *c, unsigned long rate)
+{
+ return tegra12_emc_clk_round_updown(c, rate, true);
+}
+
static int tegra12_emc_clk_set_rate(struct clk *c, unsigned long rate)
{
int ret;
if (detach_shared_bus)
return 0;
- rate = tegra12_clk_shared_bus_update(bus, NULL, NULL);
- rate = clk_round_rate_locked(bus, rate);
+ rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
if (rate == clk_get_rate_locked(bus))
return 0;
.disable = &tegra12_periph_clk_disable,
.set_rate = &tegra12_emc_clk_set_rate,
.round_rate = &tegra12_emc_clk_round_rate,
+ .round_rate_updown = &tegra12_emc_clk_round_updown,
.reset = &tegra12_periph_clk_reset,
.shared_bus_update = &tegra12_clk_emc_bus_update,
};
return 0;
}
-static long tegra12_clk_cbus_round_rate(struct clk *c, unsigned long rate)
+static long tegra12_clk_cbus_round_updown(struct clk *c, unsigned long rate,
+ bool up)
{
int i;
+ const int *millivolts;
if (!c->dvfs) {
if (!c->min_rate)
}
rate = max(rate, c->min_rate);
- for (i = 0; i < (c->dvfs->num_freqs - 1); i++) {
+ millivolts = tegra_dvfs_get_millivolts_pll(c->dvfs);
+ for (i = 0; ; i++) {
unsigned long f = c->dvfs->freqs[i];
- int mv = c->dvfs->millivolts[i];
- if ((f >= rate) || (mv >= c->dvfs->max_millivolts))
+ int mv = millivolts[i];
+ if ((f >= rate) || (mv >= c->dvfs->max_millivolts) ||
+ ((i + 1) >= c->dvfs->num_freqs)) {
+ if (!up && i && (f > rate))
+ i--;
break;
+ }
}
return c->dvfs->freqs[i];
}
+static long tegra12_clk_cbus_round_rate(struct clk *c, unsigned long rate)
+{
+ return tegra12_clk_cbus_round_updown(c, rate, true);
+}
+
static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort)
{
int ret = 0;
struct clk *slow = NULL;
struct clk *top = NULL;
unsigned long rate;
+ unsigned long old_rate;
+ unsigned long ceiling;
if (detach_shared_bus)
return 0;
- rate = tegra12_clk_shared_bus_update(bus, &top, &slow);
+ rate = tegra12_clk_shared_bus_update(bus, &top, &slow, &ceiling);
/* use dvfs table of the slowest enabled client as cbus dvfs table */
if (bus->dvfs && slow && (slow != bus->u.cbus.slow_user)) {
bus->u.cbus.slow_user = slow;
bus->u.cbus.top_user = top;
- rate = bus->ops->round_rate(bus, rate);
+ rate = tegra12_clk_cap_shared_bus(bus, rate, ceiling);
mv = tegra_dvfs_predict_millivolts(bus, rate);
if (IS_ERR_VALUE(mv))
return -EINVAL;
}
}
- ret = bus->ops->set_rate(bus, rate);
- if (ret)
- return ret;
+ old_rate = clk_get_rate_locked(bus);
+ if (IS_ENABLED(CONFIG_TEGRA_MIGRATE_CBUS_USERS) || (old_rate != rate)) {
+ ret = bus->ops->set_rate(bus, rate);
+ if (ret)
+ return ret;
+ }
if (bus->dvfs) {
if (bus->refcnt && (mv <= 0)) {
}
}
+ clk_rate_change_notify(bus, rate);
return 0;
};
#else
if (detach_shared_bus)
return 0;
- rate = tegra12_clk_shared_bus_update(bus, NULL, NULL);
- rate = clk_round_rate_locked(bus, rate);
+ rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
old_rate = clk_get_rate_locked(bus);
if (rate == old_rate)
.enable = tegra12_clk_cbus_enable,
.set_rate = tegra12_clk_cbus_set_rate,
.round_rate = tegra12_clk_cbus_round_rate,
+ .round_rate_updown = tegra12_clk_cbus_round_updown,
.shared_bus_update = tegra12_clk_cbus_update,
};
* clock to each user. The frequency of the bus is set to the highest
* enabled shared_bus_user clock, with a minimum value set by the
* shared bus.
+ *
+ * Optionally shared bus may support users migration. Since shared bus and
+ * its * children (users) have reversed rate relations: user rates determine
+ * bus rate, * switching user from one parent/bus to another may change rates
+ * of both parents. Therefore we need a cross-bus lock on top of individual
+ * user and bus locks. For now, limit bus switch support to cbus only if
+ * CONFIG_TEGRA_MIGRATE_CBUS_USERS is set.
*/
-static unsigned long tegra12_clk_shared_bus_update(
- struct clk *bus, struct clk **bus_top, struct clk **bus_slow)
+static unsigned long tegra12_clk_shared_bus_update(struct clk *bus,
+ struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap)
{
struct clk *c;
struct clk *slow = NULL;
unsigned long bw = 0;
unsigned long iso_bw = 0;
unsigned long ceiling = bus->max_rate;
+ unsigned long ceiling_but_iso = bus->max_rate;
u32 usage_flags = 0;
+ bool rate_set = false;
list_for_each_entry(c, &bus->shared_bus_list,
u.shared_bus_user.node) {
+ bool cap_user = (c->u.shared_bus_user.mode == SHARED_CEILING) ||
+ (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO);
/*
* Ignore requests from disabled floor and bw users, and from
* auto-users riding the bus. Always honor ceiling users, even
* if they are disabled - we do not want to keep enabled parent
- * bus just because ceiling is set.
+ * bus just because ceiling is set. Ignore SCLK/AHB/APB dividers
+ * to propagate flat max request.
*/
- if (c->u.shared_bus_user.enabled ||
- (c->u.shared_bus_user.mode == SHARED_CEILING)) {
- unsigned long request_rate = c->u.shared_bus_user.rate *
- (c->div ? : 1);
+ if (c->u.shared_bus_user.enabled || cap_user) {
+ unsigned long request_rate = c->u.shared_bus_user.rate;
+ if (!(c->flags & DIV_BUS))
+ request_rate *= c->div ? : 1;
usage_flags |= c->u.shared_bus_user.usage_flag;
+ if (!(c->flags & BUS_RATE_LIMIT))
+ rate_set = true;
+
switch (c->u.shared_bus_user.mode) {
case SHARED_ISO_BW:
iso_bw += request_rate;
if (bw > bus->max_rate)
bw = bus->max_rate;
break;
+ case SHARED_CEILING_BUT_ISO:
+ ceiling_but_iso =
+ min(request_rate, ceiling_but_iso);
+ break;
case SHARED_CEILING:
ceiling = min(request_rate, ceiling);
break;
case SHARED_FLOOR:
default:
rate = max(request_rate, rate);
- if (c->u.shared_bus_user.client) {
+ if (c->u.shared_bus_user.client
+ && request_rate) {
if (top_rate < request_rate) {
top_rate = request_rate;
top = c;
}
}
- if (bus->flags & PERIPH_EMC_ENB)
+ if (bus->flags & PERIPH_EMC_ENB) {
+ unsigned long iso_bw_min;
bw = tegra_emc_apply_efficiency(
- bw, iso_bw, bus->max_rate, usage_flags);
+ bw, iso_bw, bus->max_rate, usage_flags, &iso_bw_min);
+ if (bus->ops && bus->ops->round_rate)
+ iso_bw_min = bus->ops->round_rate(bus, iso_bw_min);
+ ceiling_but_iso = max(ceiling_but_iso, iso_bw_min);
+ }
- rate = override_rate ? : min(max(rate, bw), ceiling);
+ rate = override_rate ? : max(rate, bw);
+ ceiling = min(ceiling, ceiling_but_iso);
+ ceiling = override_rate ? bus->max_rate : ceiling;
+ bus->override_rate = override_rate;
- if (bus_top)
+ if (bus_top && bus_slow && rate_cap) {
+ /* If dynamic bus dvfs table, let the caller to complete
+ rounding and aggregation */
*bus_top = top;
- if (bus_slow)
*bus_slow = slow;
+ *rate_cap = ceiling;
+ } else {
+ /*
+ * If satic bus dvfs table, complete rounding and aggregation.
+ * In case when no user requested bus rate, and bus retention
+ * is enabled, don't scale down - keep current rate.
+ */
+ if (!rate_set && (bus->shared_bus_flags & SHARED_BUS_RETENTION))
+ rate = clk_get_rate_locked(bus);
+ rate = tegra12_clk_cap_shared_bus(bus, rate, ceiling);
+ }
+
return rate;
};
+static unsigned long tegra12_clk_cap_shared_bus(struct clk *bus,
+ unsigned long rate, unsigned long ceiling)
+{
+ if (bus->ops && bus->ops->round_rate_updown)
+ ceiling = bus->ops->round_rate_updown(bus, ceiling, false);
+
+ rate = min(rate, ceiling);
+
+ if (bus->ops && bus->ops->round_rate)
+ rate = bus->ops->round_rate(bus, rate);
+
+ return rate;
+}
+
static int tegra_clk_shared_bus_migrate_users(struct clk *user)
{
if (detach_shared_bus)
c->state = OFF;
c->set = true;
+ if ((c->u.shared_bus_user.mode == SHARED_CEILING) ||
+ (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) {
+ c->state = ON;
+ c->refcnt++;
+ }
+
if (c->u.shared_bus_user.client_id) {
c->u.shared_bus_user.client =
tegra_get_clock_by_name(c->u.shared_bus_user.client_id);
&c->parent->shared_bus_list);
}
-/*
- * Shared bus and its children/users have reversed rate relations - user rates
- * determine bus rate. Hence switching user from one parent/bus to another may
- * change rates of both parents. Therefore we need a cross-bus lock on top of
- * individual user and bus locks. For now limit bus switch support to cansleep
- * users with cross-clock mutex only.
- */
static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
{
+ int ret;
const struct clk_mux_sel *sel;
if (detach_shared_bus)
clk_enable(p);
list_move_tail(&c->u.shared_bus_user.node, &p->shared_bus_list);
- tegra_clk_shared_bus_update(p);
+ ret = tegra_clk_shared_bus_update(p);
+ if (ret) {
+ list_move_tail(&c->u.shared_bus_user.node,
+ &c->parent->shared_bus_list);
+ tegra_clk_shared_bus_update(c->parent);
+ clk_disable(p);
+ return ret;
+ }
+
tegra_clk_shared_bus_update(c->parent);
- if (c->refcnt && c->parent)
+ if (c->refcnt)
clk_disable(c->parent);
clk_reparent(c, p);
static int tegra_clk_shared_bus_user_set_rate(struct clk *c, unsigned long rate)
{
+ int ret;
+
c->u.shared_bus_user.rate = rate;
- tegra_clk_shared_bus_update(c->parent);
+ ret = tegra_clk_shared_bus_update(c->parent);
- if (c->cross_clk_mutex && clk_cansleep(c))
+ if (!ret && c->cross_clk_mutex && clk_cansleep(c))
tegra_clk_shared_bus_migrate_users(c);
- return 0;
+ return ret;
}
static long tegra_clk_shared_bus_user_round_rate(
struct clk *c, unsigned long rate)
{
- /* Defer rounding requests until aggregated. BW users must not be
- rounded at all, others just clipped to bus range (some clients
- may use round api to find limits) */
+ /*
+ * Defer rounding requests until aggregated. BW users must not be
+ * rounded at all, others just clipped to bus range (some clients
+ * may use round api to find limits). Ignore SCLK/AHB and AHB/APB
+ * dividers to keep flat bus requests propagation.
+ */
if ((c->u.shared_bus_user.mode != SHARED_BW) &&
(c->u.shared_bus_user.mode != SHARED_ISO_BW)) {
- if (c->div > 1)
+ if (!(c->flags & DIV_BUS) && (c->div > 1))
rate *= c->div;
if (rate > c->parent->max_rate)
else if (rate < c->parent->min_rate)
rate = c->parent->min_rate;
- if (c->div > 1)
+ if (!(c->flags & DIV_BUS) && (c->div > 1))
rate /= c->div;
}
return rate;
static int tegra_clk_shared_bus_user_enable(struct clk *c)
{
- int ret = 0;
+ int ret;
c->u.shared_bus_user.enabled = true;
- tegra_clk_shared_bus_update(c->parent);
- if (c->u.shared_bus_user.client)
+ ret = tegra_clk_shared_bus_update(c->parent);
+ if (!ret && c->u.shared_bus_user.client)
ret = clk_enable(c->u.shared_bus_user.client);
- if (c->cross_clk_mutex && clk_cansleep(c))
+ if (!ret && c->cross_clk_mutex && clk_cansleep(c))
tegra_clk_shared_bus_migrate_users(c);
return ret;
.reset = tegra_clk_shared_bus_user_reset,
};
+/* shared bus connector ops (user/bus connector to cascade shared buses) */
+static int tegra12_clk_shared_connector_update(struct clk *bus)
+{
+ unsigned long rate, old_rate;
+
+ if (detach_shared_bus)
+ return 0;
+
+ rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
+
+ old_rate = clk_get_rate_locked(bus);
+ if (rate == old_rate)
+ return 0;
+
+ return clk_set_rate_locked(bus, rate);
+}
+
+static struct clk_ops tegra_clk_shared_connector_ops = {
+ .init = tegra_clk_shared_bus_user_init,
+ .enable = tegra_clk_shared_bus_user_enable,
+ .disable = tegra_clk_shared_bus_user_disable,
+ .set_parent = tegra_clk_shared_bus_user_set_parent,
+ .set_rate = tegra_clk_shared_bus_user_set_rate,
+ .round_rate = tegra_clk_shared_bus_user_round_rate,
+ .reset = tegra_clk_shared_bus_user_reset,
+ .shared_bus_update = tegra12_clk_shared_connector_update,
+};
+
/* coupled gate ops */
/*
* Some clocks may have common enable/disable control, but run at different
};
+/*
+ * AHB and APB shared bus operations
+ * APB shared bus is a user of AHB shared bus
+ * AHB shared bus is a user of SCLK complex shared bus
+ * SCLK/AHB and AHB/APB dividers can be dynamically changed. When AHB and APB
+ * users requests are propagated to SBUS target rate, current values of the
+ * dividers are ignored, and flat maximum request is selected as SCLK bus final
+ * target. Then the dividers will be re-evaluated, based on AHB and APB targets.
+ * Both AHB and APB buses are always enabled.
+ */
+static void tegra12_clk_ahb_apb_init(struct clk *c, struct clk *bus_clk)
+{
+ tegra_clk_shared_bus_user_init(c);
+ c->max_rate = bus_clk->max_rate;
+ c->min_rate = bus_clk->min_rate;
+ c->mul = bus_clk->mul;
+ c->div = bus_clk->div;
+
+ c->u.shared_bus_user.rate = clk_get_rate(bus_clk);
+ c->u.shared_bus_user.enabled = true;
+ c->parent->child_bus = c;
+}
+
+static void tegra12_clk_ahb_init(struct clk *c)
+{
+ struct clk *bus_clk = c->parent->u.system.hclk;
+ tegra12_clk_ahb_apb_init(c, bus_clk);
+}
+
+static void tegra12_clk_apb_init(struct clk *c)
+{
+ struct clk *bus_clk = c->parent->parent->u.system.pclk;
+ tegra12_clk_ahb_apb_init(c, bus_clk);
+}
+
+static int tegra12_clk_ahb_apb_update(struct clk *bus)
+{
+ unsigned long rate;
+
+ if (detach_shared_bus)
+ return 0;
+
+ rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
+ return clk_set_rate_locked(bus, rate);
+}
+
+static struct clk_ops tegra_clk_ahb_ops = {
+ .init = tegra12_clk_ahb_init,
+ .set_rate = tegra_clk_shared_bus_user_set_rate,
+ .round_rate = tegra_clk_shared_bus_user_round_rate,
+ .shared_bus_update = tegra12_clk_ahb_apb_update,
+};
+
+static struct clk_ops tegra_clk_apb_ops = {
+ .init = tegra12_clk_apb_init,
+ .set_rate = tegra_clk_shared_bus_user_set_rate,
+ .round_rate = tegra_clk_shared_bus_user_round_rate,
+ .shared_bus_update = tegra12_clk_ahb_apb_update,
+};
+
/* Clock definitions */
static struct clk tegra_clk_32k = {
.name = "clk_32k",
.input_max = 500000000,
.cf_min = 12000000,
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
- .vco_min = 400000000,
+ .vco_min = 500000000,
.vco_max = 1066000000,
.freq_table = tegra_pll_m_freq_table,
.lock_delay = 300,
.ops = &tegra_plld_ops,
.reg = 0xd0,
.parent = &tegra_pll_ref,
- .max_rate = 1000000000,
+ .max_rate = 1500000000,
.u.pll = {
.input_min = 2000000,
.input_max = 40000000,
.cf_min = 1000000,
.cf_max = 6000000,
.vco_min = 500000000,
- .vco_max = 1000000000,
+ .vco_max = 1500000000,
.freq_table = tegra_pll_d_freq_table,
.lock_delay = 1000,
- .cpcon_default = 8,
},
};
.vco_max = 960000000,
.freq_table = tegra_pll_u_freq_table,
.lock_delay = 1000,
- .cpcon_default = 12,
},
};
.ops = &tegra_pllxc_ops,
.reg = 0xe0,
.parent = &tegra_pll_ref,
- .max_rate = 1800000000,
+ .max_rate = 3000000000UL,
.u.pll = {
.input_min = 12000000,
.input_max = 800000000,
.cf_min = 12000000,
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
.vco_min = 700000000,
- .vco_max = 2400000000U,
+ .vco_max = 3000000000UL,
.freq_table = tegra_pll_x_freq_table,
.lock_delay = 300,
.misc1 = 0x510 - 0xe0,
.max_rate = 700000000,
};
-/* FIXME: remove; for now, should be always checked-in as "0" */
-#define USE_LP_CPU_TO_TEST_DFLL 0
-
static struct clk tegra_dfll_cpu = {
.name = "dfll_cpu",
.flags = DFLL,
.ops = &tegra_dfll_ops,
.reg = 0x2f4,
- .max_rate = 2000000000,
+ .max_rate = 3000000000UL,
};
static struct clk_pll_freq_table tegra_pllc4_freq_table[] = {
.name = "pciex",
.parent = &tegra_pll_e,
.ops = &tegra_pciex_clk_ops,
- .max_rate = 100000000,
+ .max_rate = 500000000,
.u.periph = {
.clk_num = 74,
},
#define MUX_I2S_SPDIF(_id, _index) \
static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
{.input = &tegra_pll_a_out0, .value = 0}, \
- {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \
- {.input = &tegra_pll_p, .value = 2}, \
- {.input = &tegra_clk_m, .value = 3}, \
+ {.input = &tegra_clk_audio_2x_list[(_index)], .value = 2}, \
+ {.input = &tegra_pll_p, .value = 4}, \
+ {.input = &tegra_clk_m, .value = 6}, \
{ 0, 0}, \
}
MUX_I2S_SPDIF(audio0, 0);
/* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra12x */
/* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra12x */
{ .input = &tegra_pll_x_out0, .value = 8},
-#if USE_LP_CPU_TO_TEST_DFLL
- { .input = &tegra_dfll_cpu, .value = 15},
-#endif
{ .input = &tegra_pll_x, .value = 8 | SUPER_LP_DIV2_BYPASS},
{ 0, 0},
};
{ .input = &tegra_clk_m, .value = 0},
{ .input = &tegra_pll_c_out1, .value = 1},
{ .input = &tegra_pll_p_out4, .value = 2},
- { .input = &tegra_pll_p_out3, .value = 3},
+ { .input = &tegra_pll_p, .value = 3},
{ .input = &tegra_pll_p_out2, .value = 4},
- /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra12x */
+ { .input = &tegra_pll_c, .value = 5},
{ .input = &tegra_clk_32k, .value = 6},
{ .input = &tegra_pll_m_out1, .value = 7},
{ 0, 0},
.inputs = mux_cclk_g,
.reg = 0x368,
.ops = &tegra_super_ops,
- .max_rate = 2000000000,
+ .max_rate = 3000000000UL,
};
static struct clk tegra_clk_cclk_lp = {
.inputs = mux_cclk_lp,
.reg = 0x370,
.ops = &tegra_super_ops,
- .max_rate = 700000000,
+ .max_rate = 1350000000,
};
static struct clk tegra_clk_sclk = {
.inputs = mux_sclk,
.reg = 0x28,
.ops = &tegra_super_ops,
- .max_rate = 336000000,
+ .max_rate = 420000000,
.min_rate = 12000000,
};
.name = "cpu_g",
.parent = &tegra_clk_cclk_g,
.ops = &tegra_cpu_ops,
- .max_rate = 2000000000,
+ .max_rate = 3000000000UL,
.u.cpu = {
.main = &tegra_pll_x,
.backup = &tegra_pll_p_out4,
.name = "cpu_lp",
.parent = &tegra_clk_cclk_lp,
.ops = &tegra_cpu_ops,
- .max_rate = 700000000,
+ .max_rate = 1350000000,
.u.cpu = {
.main = &tegra_pll_x,
.backup = &tegra_pll_p_out4,
-#if USE_LP_CPU_TO_TEST_DFLL
- .dynamic = &tegra_dfll_cpu,
-#endif
.mode = MODE_LP,
},
};
.name = "cpu",
.inputs = mux_cpu_cmplx,
.ops = &tegra_cpu_cmplx_ops,
- .max_rate = 2000000000,
+ .max_rate = 3000000000UL,
};
static struct clk tegra_clk_cop = {
.pclk = &tegra_clk_pclk,
.hclk = &tegra_clk_hclk,
.sclk_low = &tegra_pll_p_out2,
+#ifdef CONFIG_TEGRA_PLLM_SCALED
+ .sclk_high = &tegra_pll_c_out1,
+#else
.sclk_high = &tegra_pll_m_out1,
+#endif
},
.rate_change_nh = &sbus_rate_change_nh,
};
+static struct clk tegra_clk_ahb = {
+ .name = "ahb.sclk",
+ .flags = DIV_BUS,
+ .parent = &tegra_clk_sbus_cmplx,
+ .ops = &tegra_clk_ahb_ops,
+};
+
+static struct clk tegra_clk_apb = {
+ .name = "apb.sclk",
+ .flags = DIV_BUS,
+ .parent = &tegra_clk_ahb,
+ .ops = &tegra_clk_apb_ops,
+};
+
static struct clk tegra_clk_blink = {
.name = "blink",
.parent = &tegra_clk_32k,
static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
{ .input = &tegra_pll_m, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_pll_p, .value = 2},
- { .input = &tegra_pll_a_out0, .value = 3},
+ { .input = &tegra_pll_c, .value = 2},
+ { .input = &tegra_pll_p, .value = 4},
+ { .input = &tegra_pll_a_out0, .value = 6},
{ 0, 0},
};
static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
{ .input = &tegra_pll_a_out0, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_pll_p, .value = 2},
- { .input = &tegra_clk_m, .value = 3},
+ { .input = &tegra_pll_c, .value = 2},
+ { .input = &tegra_pll_p, .value = 4},
+ { .input = &tegra_clk_m, .value = 6},
{ 0, 0},
};
{ .input = &tegra_pll_c, .value = 1},
{ .input = &tegra_pll_p, .value = 2},
{ .input = &tegra_clk_m, .value = 3},
- { .input = &tegra_pll_m, .value = 4}, /* low jitter PLLM input */
+ { .input = &tegra_pll_m, .value = 4}, /* low jitter PLLM output */
+ /* { .input = &tegra_pll_c2, .value = 5}, - no use on tegra12x */
+ /* { .input = &tegra_pll_c3, .value = 6}, - no use on tegra12x */
+ { .input = &tegra_pll_c, .value = 7}, /* low jitter PLLC output */
{ 0, 0},
};
{ 0, 0},
};
+/* Peripheral muxes */
static struct clk_mux_sel mux_pllp_pllc_clkm[] = {
+ {.input = &tegra_pll_p, .value = 0},
+ {.input = &tegra_pll_c, .value = 2},
+ {.input = &tegra_clk_m, .value = 6},
+ { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_clkm1[] = {
{.input = &tegra_pll_p, .value = 0},
{.input = &tegra_pll_c, .value = 1},
{.input = &tegra_clk_m, .value = 3},
{ 0, 0},
};
-/* Peripheral muxes */
static struct clk_mux_sel mux_pllp_pllc2_c_c3_pllm_clkm[] = {
{ .input = &tegra_pll_p, .value = 0},
{ .input = &tegra_pll_c2, .value = 1},
static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
{ .input = &tegra_pll_p, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_pll_m, .value = 2},
- { .input = &tegra_clk_m, .value = 3},
+ { .input = &tegra_pll_c, .value = 2},
+ { .input = &tegra_pll_m, .value = 4},
+ { .input = &tegra_clk_m, .value = 6},
{ 0, 0},
};
static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
{.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_c, .value = 1},
- {.input = &tegra_pll_m, .value = 2},
+ {.input = &tegra_pll_c, .value = 2},
+ {.input = &tegra_pll_m, .value = 4},
{ 0, 0},
};
-static struct clk_mux_sel mux_pllp_clkm1[] = {
- { .input = &tegra_pll_p, .value = 0},
- { .input = &tegra_clk_m, .value = 1},
+static struct clk_mux_sel mux_pllp_clkm_clk32_plle[] = {
+ { .input = &tegra_pll_p, .value = 0},
+ { .input = &tegra_clk_m, .value = 1},
+ { .input = &tegra_clk_32k, .value = 2},
+ { .input = &tegra_pll_e, .value = 3},
{ 0, 0},
};
static struct clk_mux_sel mux_pllp_clkm[] = {
{ .input = &tegra_pll_p, .value = 0},
- { .input = &tegra_clk_m, .value = 3},
+ { .input = &tegra_clk_m, .value = 6},
{ 0, 0},
};
static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
{.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_c, .value = 1},
- {.input = &tegra_clk_32k, .value = 2},
- {.input = &tegra_clk_m, .value = 3},
+ {.input = &tegra_pll_c, .value = 2},
+ {.input = &tegra_clk_32k, .value = 4},
+ {.input = &tegra_clk_m, .value = 6},
{ 0, 0},
};
static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
{.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_c, .value = 1},
- {.input = &tegra_clk_m, .value = 2},
- {.input = &tegra_clk_32k, .value = 3},
+ {.input = &tegra_pll_c, .value = 2},
+ {.input = &tegra_clk_m, .value = 4},
+ {.input = &tegra_clk_32k, .value = 6},
{ 0, 0},
};
static struct clk_mux_sel mux_clkm_48M_pllp_480M[] = {
{ .input = &tegra_clk_m, .value = 0},
- { .input = &tegra_pll_u_48M, .value = 1},
- { .input = &tegra_pll_p, .value = 2},
- { .input = &tegra_pll_u_480M, .value = 3},
+ { .input = &tegra_pll_u_48M, .value = 2},
+ { .input = &tegra_pll_p, .value = 4},
+ { .input = &tegra_pll_u_480M, .value = 6},
{ 0, 0},
};
};
-/* xusb_hs has an alternative source, that is not used - therefore, xusb_hs
- is modeled as a single source mux */
-static struct clk_mux_sel mux_pllu_60M[] = {
- { .input = &tegra_pll_u_60M, .value = 1},
- { 0, 0},
-};
-
static struct raw_notifier_head emc_rate_change_nh;
static struct clk tegra_clk_emc = {
.max_rate = 1066000000,
.min_rate = 12750000,
.inputs = mux_pllm_pllc_pllp_clkm,
- .flags = MUX | MUX8 | DIV_U71 | PERIPH_EMC_ENB,
+ .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
.u.periph = {
.clk_num = 57,
},
.rate_change_nh = &emc_rate_change_nh,
};
+static struct raw_notifier_head host1x_rate_change_nh;
+
+static struct clk tegra_clk_host1x = {
+ .name = "host1x",
+ .lookup = {
+ .dev_id = "host1x",
+ },
+ .ops = &tegra_1xbus_clk_ops,
+ .reg = 0x180,
+ .inputs = mux_pllm_pllc_pllp_plla,
+ .flags = MUX | DIV_U71 | DIV_U71_INT,
+ .max_rate = 500000000,
+ .min_rate = 12000000,
+ .u.periph = {
+ .clk_num = 28,
+ .pll_low = &tegra_pll_p,
+#ifdef CONFIG_TEGRA_PLLM_SCALED
+ .pll_high = &tegra_pll_c,
+#else
+ .pll_high = &tegra_pll_m,
+#endif
+ },
+ .rate_change_nh = &host1x_rate_change_nh,
+};
+
#ifdef CONFIG_TEGRA_DUAL_CBUS
static struct raw_notifier_head c2bus_rate_change_nh;
.name = "c3bus",
.parent = &tegra_pll_c3,
.ops = &tegra_clk_cbus_ops,
- .max_rate = 700000000,
+ .max_rate = 900000000,
.mul = 1,
.div = 1,
.flags = PERIPH_ON_CBUS,
.rate_change_nh = &c3bus_rate_change_nh,
};
+#ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
static DEFINE_MUTEX(cbus_mutex);
+#define CROSS_CBUS_MUTEX (&cbus_mutex)
+#else
+#define CROSS_CBUS_MUTEX NULL
+#endif
+
static struct clk_mux_sel mux_clk_cbus[] = {
{ .input = &tegra_clk_c2bus, .value = 0},
.client_div = _div, \
.mode = _mode, \
}, \
- .cross_clk_mutex = &cbus_mutex, \
+ .cross_clk_mutex = CROSS_CBUS_MUTEX, \
}
#else
dvfs to control voltage of gpu rail along with frequency change of actual
gpu clock. So frequency here and in dvfs are based on the acutal gpu clock. */
static struct clk tegra_clk_gpu = {
- .name = "gpu",
+ .name = "gpu_ref",
.ops = &tegra_clk_gpu_ops,
.parent = &tegra_pll_ref,
.u.periph = {
.clk_num = 184,
},
- .max_rate = 806000000,
+ .max_rate = 48000000,
+ .min_rate = 12000000,
+};
+
+static void tegra12_clk_gbus_init(struct clk *c)
+{
+ unsigned long rate;
+ bool enabled;
+
+ pr_debug("%s on clock %s (export ops %s)\n", __func__,
+ c->name, c->u.export_clk.ops ? "ready" : "not ready");
+
+ if (!c->u.export_clk.ops || !c->u.export_clk.ops->init)
+ return;
+
+ c->u.export_clk.ops->init(c->u.export_clk.ops->data, &rate, &enabled);
+ c->div = clk_get_rate(c->parent) / 1000000;
+ c->mul = rate / 1000000;
+ c->state = enabled ? ON : OFF;
+}
+
+static int tegra12_clk_gbus_enable(struct clk *c)
+{
+ pr_debug("%s on clock %s (export ops %s)\n", __func__,
+ c->name, c->u.export_clk.ops ? "ready" : "not ready");
+
+ if (!c->u.export_clk.ops || !c->u.export_clk.ops->enable)
+ return -ENOENT;
+
+ return c->u.export_clk.ops->enable(c->u.export_clk.ops->data);
+}
+
+static void tegra12_clk_gbus_disable(struct clk *c)
+{
+ pr_debug("%s on clock %s (export ops %s)\n", __func__,
+ c->name, c->u.export_clk.ops ? "ready" : "not ready");
+
+ if (!c->u.export_clk.ops || !c->u.export_clk.ops->disable)
+ return;
+
+ c->u.export_clk.ops->disable(c->u.export_clk.ops->data);
+}
+
+static int tegra12_clk_gbus_set_rate(struct clk *c, unsigned long rate)
+{
+ int ret;
+
+ pr_debug("%s %lu on clock %s (export ops %s)\n", __func__,
+ rate, c->name, c->u.export_clk.ops ? "ready" : "not ready");
+
+ if (!c->u.export_clk.ops || !c->u.export_clk.ops->set_rate)
+ return -ENOENT;
+
+ ret = c->u.export_clk.ops->set_rate(c->u.export_clk.ops->data, &rate);
+ if (!ret)
+ c->mul = rate / 1000000;
+ return ret;
+}
+
+static struct clk_ops tegra_clk_gbus_ops = {
+ .init = tegra12_clk_gbus_init,
+ .enable = tegra12_clk_gbus_enable,
+ .disable = tegra12_clk_gbus_disable,
+ .set_rate = tegra12_clk_gbus_set_rate,
+ .round_rate = tegra12_clk_cbus_round_rate, /* re-use */
+ .round_rate_updown = tegra12_clk_cbus_round_updown, /* re-use */
+ .shared_bus_update = tegra12_clk_shared_connector_update, /* re-use */
+};
+
+static struct raw_notifier_head gbus_rate_change_nh;
+
+static struct clk tegra_clk_gbus = {
+ .name = "gbus",
+ .ops = &tegra_clk_gbus_ops,
+ .parent = &tegra_clk_gpu,
+ .max_rate = 1000000000,
+ .shared_bus_flags = SHARED_BUS_RETENTION,
+ .rate_change_nh = &gbus_rate_change_nh,
+};
+
+static void tegra12_camera_mclk_init(struct clk *c)
+{
+ c->state = OFF;
+ c->set = true;
+
+ if (!strcmp(c->name, "mclk")) {
+ c->parent = tegra_get_clock_by_name("vi_sensor");
+ c->max_rate = c->parent->max_rate;
+ } else if (!strcmp(c->name, "mclk2")) {
+ c->parent = tegra_get_clock_by_name("vi_sensor2");
+ c->max_rate = c->parent->max_rate;
+ }
+}
+
+static int tegra12_camera_mclk_set_rate(struct clk *c, unsigned long rate)
+{
+ return clk_set_rate(c->parent, rate);
+}
+
+static struct clk_ops tegra_camera_mclk_ops = {
+ .init = tegra12_camera_mclk_init,
+ .enable = tegra12_periph_clk_enable,
+ .disable = tegra12_periph_clk_disable,
+ .set_rate = tegra12_camera_mclk_set_rate,
+};
+
+static struct clk tegra_camera_mclk = {
+ .name = "mclk",
+ .ops = &tegra_camera_mclk_ops,
+ .u.periph = {
+ .clk_num = 92, /* csus */
+ },
+ .flags = PERIPH_NO_RESET,
+};
+
+static struct clk tegra_camera_mclk2 = {
+ .name = "mclk2",
+ .ops = &tegra_camera_mclk_ops,
+ .u.periph = {
+ .clk_num = 171, /* vim2_clk */
+ },
+ .flags = PERIPH_NO_RESET,
+};
+
+static struct clk tegra_clk_isp = {
+ .name = "isp",
+ .ops = &tegra_periph_clk_ops,
+ .reg = 0x144,
+ .max_rate = 700000000,
+ .inputs = mux_pllm_pllc_pllp_plla_clkm_pllc4,
+ .flags = MUX | DIV_U71 | PERIPH_NO_ENB | PERIPH_NO_RESET,
+};
+
+static struct clk_mux_sel mux_isp[] = {
+ { .input = &tegra_clk_isp, .value = 0},
+ { 0, 0},
+};
+
+static struct raw_notifier_head c4bus_rate_change_nh;
+
+static struct clk tegra_clk_c4bus = {
+ .name = "c4bus",
+ .parent = &tegra_pll_c4,
+ .ops = &tegra_clk_cbus_ops,
+ .max_rate = 700000000,
+ .mul = 1,
+ .div = 1,
+ .shared_bus_backup = {
+ .input = &tegra_pll_p,
+ },
+ .rate_change_nh = &c4bus_rate_change_nh,
};
#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
.mode = _mode, \
}, \
}
+#define SHARED_LIMIT(_name, _dev, _con, _parent, _id, _div, _mode)\
+ { \
+ .name = _name, \
+ .lookup = { \
+ .dev_id = _dev, \
+ .con_id = _con, \
+ }, \
+ .ops = &tegra_clk_shared_bus_user_ops, \
+ .parent = _parent, \
+ .flags = BUS_RATE_LIMIT, \
+ .u.shared_bus_user = { \
+ .client_id = _id, \
+ .client_div = _div, \
+ .mode = _mode, \
+ }, \
+ }
+#define SHARED_CONNECT(_name, _dev, _con, _parent, _id, _div, _mode)\
+ { \
+ .name = _name, \
+ .lookup = { \
+ .dev_id = _dev, \
+ .con_id = _con, \
+ }, \
+ .ops = &tegra_clk_shared_connector_ops, \
+ .parent = _parent, \
+ .u.shared_bus_user = { \
+ .client_id = _id, \
+ .client_div = _div, \
+ .mode = _mode, \
+ }, \
+ }
+
#define SHARED_EMC_CLK(_name, _dev, _con, _parent, _id, _div, _mode, _flag)\
{ \
.name = _name, \
}, \
}
+static DEFINE_MUTEX(sbus_cross_mutex);
+#define SHARED_SCLK(_name, _dev, _con, _parent, _id, _div, _mode)\
+ { \
+ .name = _name, \
+ .lookup = { \
+ .dev_id = _dev, \
+ .con_id = _con, \
+ }, \
+ .ops = &tegra_clk_shared_bus_user_ops, \
+ .parent = _parent, \
+ .u.shared_bus_user = { \
+ .client_id = _id, \
+ .client_div = _div, \
+ .mode = _mode, \
+ }, \
+ .cross_clk_mutex = &sbus_cross_mutex, \
+}
+
struct clk tegra_list_clks[] = {
PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 24576000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 24576000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 48000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 48000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
D_AUDIO_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
- D_AUDIO_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
- D_AUDIO_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
- D_AUDIO_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("adx1", "adx1", NULL, 180, 0x670, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("amx1", "amx1", NULL, 185, 0x674, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0),
- PERIPH_CLK("sbc1", "spi-tegra114.0", NULL, 41, 0x134, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc2", "spi-tegra114.1", NULL, 44, 0x118, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc3", "spi-tegra114.2", NULL, 46, 0x11c, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc4", "spi-tegra114.3", NULL, 68, 0x1b4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc5", "spi-tegra114.4", NULL, 104, 0x3c8, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc6", "spi-tegra114.5", NULL, 105, 0x3cc, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0),
+ D_AUDIO_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 40000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
+ D_AUDIO_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 40000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
+ D_AUDIO_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 40000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 24580000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("adx1", "adx1", NULL, 180, 0x670, 24580000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 24600000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("amx1", "amx1", NULL, 185, 0x674, 24600000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
+ PERIPH_CLK("sbc1", "spi-tegra114.0", NULL, 41, 0x134, 51000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc2", "spi-tegra114.1", NULL, 44, 0x118, 51000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc3", "spi-tegra114.2", NULL, 46, 0x11c, 51000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc4", "spi-tegra114.3", NULL, 68, 0x1b4, 51000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc5", "spi-tegra114.4", NULL, 104, 0x3c8, 51000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc6", "spi-tegra114.5", NULL, 105, 0x3cc, 51000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
+ PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
+ PERIPH_CLK("cec", "tegra_cec", NULL, 136, 0, 250000000, mux_clk_m, PERIPH_ON_APB),
+ PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("trace", "trace", NULL, 77, 0x634, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2c1", "tegra14-i2c.0", "div-clk", 12, 0x124, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c2", "tegra14-i2c.1", "div-clk", 54, 0x198, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c3", "tegra14-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c4", "tegra14-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c5", "tegra14-i2c.4", "div-clk", 47, 0x128, 58300000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c6", "tegra14-i2c.5", "div-clk", 166, 0x65c, 58300000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c1-fast", "tegra14-i2c.0", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c2-fast", "tegra14-i2c.1", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c3-fast", "tegra14-i2c.2", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c4-fast", "tegra14-i2c.3", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c5-fast", "tegra14-i2c.4", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c6-fast", "tegra14-i2c.5", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, 0),
+ PERIPH_CLK("i2c1", "tegra12-i2c.0", "div-clk", 12, 0x124, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
+ PERIPH_CLK("i2c2", "tegra12-i2c.1", "div-clk", 54, 0x198, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
+ PERIPH_CLK("i2c3", "tegra12-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
+ PERIPH_CLK("i2c4", "tegra12-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
+ PERIPH_CLK("i2c5", "tegra12-i2c.4", "div-clk", 47, 0x128, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
+ PERIPH_CLK("i2c6", "tegra12-i2c.5", "div-clk", 166, 0x65c, 58300000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
+ PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("mipi-cal-fixed", "mipi-cal-fixed", NULL, 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
PERIPH_CLK("uarta", "serial-tegra.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartb", "serial-tegra.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartc", "serial-tegra.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartd", "serial-tegra.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
- PERIPH_CLK("uarta_dbg", "serial8250.0", "uarta", 6, 0x178, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
- PERIPH_CLK("uartb_dbg", "serial8250.0", "uartb", 7, 0x17c, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
- PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc", 55, 0x1a0, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
- PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd", 65, 0x1c0, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
-#ifdef CONFIG_ARCH_TEGRA_VIC
- PERIPH_CLK("vic03", "vic03", NULL, 178, 0x678, 500000000, mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, MUX | MUX8 | DIV_U71),
-#endif
- PERIPH_CLK_EX("vi", "vi", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla_pllc4, MUX | MUX8 | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
- PERIPH_CLK("vi_sensor", "vi", "vi_sensor", 164, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("vi_sensor2", "vi", "vi_sensor2", 165, 0x658, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
-#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
- PERIPH_CLK("msenc", "msenc", NULL, 60, 0x170, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
-#else
- PERIPH_CLK_EX("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops),
-#endif
- PERIPH_CLK("tsec", "tsec", NULL, 83, 0x1f4, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
- PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 324000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
+ PERIPH_CLK("vic03", "vic03", NULL, 178, 0x678, 900000000, mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, MUX | DIV_U71),
+ PERIPH_CLK_EX("vi", "vi", "vi", 20, 0x148, 700000000, mux_pllm_pllc_pllp_plla_pllc4, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
+ PERIPH_CLK("vi_sensor", NULL, "vi_sensor", 164, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
+ PERIPH_CLK("vi_sensor2", NULL, "vi_sensor2", 165, 0x658, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
+ PERIPH_CLK_EX("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops),
+ PERIPH_CLK("tsec", "tsec", NULL, 83, 0x1f4, 900000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops),
- PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 594000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
- PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
- PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
- PERIPH_CLK_EX("sor0", "sor0", NULL, 182, 0x414, 198000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8, &tegra_sor_clk_ops),
+ PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 594000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | DIV_U71),
+ PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX),
+ PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX),
+ PERIPH_CLK_EX("sor0", "sor0", NULL, 182, 0x414, 198000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | DIV_U71, &tegra_sor_clk_ops),
PERIPH_CLK("dpaux", "dpaux", NULL, 181, 0, 24000000, mux_clk_m, 0),
PERIPH_CLK("usbd", "tegra-udc.0", NULL, 22, 0, 480000000, mux_clk_m, 0),
PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0),
PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0),
- PERIPH_CLK_EX("dsia", "tegradc.0", "dsia", 48, 0xd0, 500000000, mux_plld_out0, PLLD, &tegra_dsi_clk_ops),
- PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0x4b8, 500000000, mux_plld_out0, PLLD, &tegra_dsi_clk_ops),
+ PERIPH_CLK_EX("dsia", "tegradc.0", "dsia", 48, 0xd0, 750000000, mux_plld_out0, PLLD, &tegra_dsi_clk_ops),
+ PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0x4b8, 750000000, mux_plld_out0, PLLD, &tegra_dsi_clk_ops),
PERIPH_CLK("dsi1-fixed", "tegradc.0", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
PERIPH_CLK("dsi2-fixed", "tegradc.1", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("csi", "vi", "csi", 52, 0, 102000000, mux_plld, PLLD),
- PERIPH_CLK("isp", "vi", "isp", 23, 0x144, 600000000, mux_pllm_pllc_pllp_plla_clkm_pllc4, MUX | MUX8 | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("ispb", "vi", "ispb", 3, 0, 600000000, mux_clk_m, 0),
+ PERIPH_CLK("csi", "vi", "csi", 52, 0, 750000000, mux_plld, PLLD),
+ PERIPH_CLK("ispa", "isp", "ispa", 23, 0, 700000000, mux_isp, PERIPH_ON_APB),
+ PERIPH_CLK("ispb", "isp", "ispb", 3, 0, 700000000, mux_isp, PERIPH_ON_APB),
PERIPH_CLK("csus", "vi", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
- PERIPH_CLK("vim2_clk", "vi", "vim2_clk",171, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
+ PERIPH_CLK("vim2_clk", "vi", "vim2_clk", 171, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
PERIPH_CLK("cilab", "vi", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
PERIPH_CLK("cilcd", "vi", "cilcd", 145, 0x618, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
PERIPH_CLK("cile", "vi", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 156000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
PERIPH_CLK("dsiblp", "tegradc.1", "dsiblp", 148, 0x624, 156000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
- PERIPH_CLK("entropy", "entropy", NULL, 149, 0x628, 102000000, mux_pllp_clkm1, MUX | MUX8 | DIV_U71),
- PERIPH_CLK("hdmi_audio", "hdmi_audio", NULL, 176, 0x668, 48000000, mux_pllp_pllc_clkm, MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("clk72mhz", "clk72mhz", NULL, 177, 0x66c, 102000000, mux_pllp3_pllc_clkm, MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET),
+ PERIPH_CLK("entropy", "entropy", NULL, 149, 0x628, 102000000, mux_pllp_clkm_clk32_plle, MUX | DIV_U71),
+ PERIPH_CLK("hdmi_audio", "hdmi_audio", NULL, 176, 0x668, 48000000, mux_pllp_pllc_clkm1, MUX | DIV_U71 | PERIPH_NO_RESET),
+ PERIPH_CLK("clk72mhz", "clk72mhz", NULL, 177, 0x66c, 102000000, mux_pllp3_pllc_clkm, MUX | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 12000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
- PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
- PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
- PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
+ PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | DIV_U71),
+ PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | DIV_U71),
+ PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | DIV_U71),
PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("se", "se", NULL, 127, 0x42c, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
+ PERIPH_CLK("se", "se", NULL, 127, 0x42c, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 102000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs", "ref", 155, 0x62c, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs", "soc", 155, 0x630, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
- PERIPH_CLK("soc_therm", "soc_therm", NULL, 78, 0x644, 136000000, mux_pllm_pllc_pllp_plla_v2, MUX | MUX8 | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("soc_therm", "soc_therm", NULL, 78, 0x644, 136000000, mux_pllm_pllc_pllp_plla_v2, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("dds", "dds", NULL, 150, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("dp2", "dp2", NULL, 152, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
- SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
- SHARED_CLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
- SHARED_CLK("sbc1.sclk", "tegra11-spi.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("sbc2.sclk", "tegra11-spi.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("sbc3.sclk", "tegra11-spi.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("sbc4.sclk", "tegra11-spi.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("sbc5.sclk", "tegra11-spi.4", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("sbc6.sclk", "tegra11-spi.5", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_SCLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_SCLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_SCLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_ahb, NULL, 0, 0),
+ SHARED_SCLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_ahb, NULL, 0, 0),
+ SHARED_SCLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_ahb, NULL, 0, 0),
+ SHARED_SCLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_ahb, NULL, 0, 0),
+ SHARED_SCLK("sdmmc3.sclk", "sdhci-tegra.2", "sclk", &tegra_clk_apb, NULL, 0, 0),
+ SHARED_SCLK("sdmmc4.sclk", "sdhci-tegra.3", "sclk", &tegra_clk_apb, NULL, 0, 0),
+ SHARED_SCLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_SCLK("camera.sclk", "vi", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_SCLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_SCLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
+ SHARED_SCLK("cap.throttle.sclk", "cap_throttle", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
+ SHARED_SCLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_SCLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
+ SHARED_SCLK("sbc1.sclk", "tegra12-spi.0", "sclk", &tegra_clk_apb, NULL, 0, 0),
+ SHARED_SCLK("sbc2.sclk", "tegra12-spi.1", "sclk", &tegra_clk_apb, NULL, 0, 0),
+ SHARED_SCLK("sbc3.sclk", "tegra12-spi.2", "sclk", &tegra_clk_apb, NULL, 0, 0),
SHARED_EMC_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
- SHARED_EMC_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
- SHARED_EMC_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC)),
- SHARED_EMC_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC)),
+ SHARED_EMC_CLK("mon_cpu.emc", "tegra_mon", "cpu_emc",
+ &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC1)),
+ SHARED_EMC_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC2)),
SHARED_EMC_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("usbd.emc", "tegra-udc.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("sdmmc3.emc", "sdhci-tegra.2","emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("sdmmc4.emc", "sdhci-tegra.3","emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
+ SHARED_EMC_CLK("cap.throttle.emc", "cap_throttle", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING_BUT_ISO, 0),
SHARED_EMC_CLK("3d.emc", "tegra_gk20a", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_3D)),
SHARED_EMC_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, BIT(EMC_USER_MSENC)),
SHARED_EMC_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
- SHARED_EMC_CLK("camera.emc", "vi", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI)),
- SHARED_EMC_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, 0),
+ SHARED_EMC_CLK("via.emc", "tegra_vi", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI)),
+ SHARED_EMC_CLK("vib.emc", "tegra_vi.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI2)),
+ SHARED_EMC_CLK("ispa.emc", "tegra_isp", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_ISP1)),
+ SHARED_EMC_CLK("ispb.emc", "tegra_isp.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_ISP2)),
+ SHARED_EMC_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE, 0),
SHARED_EMC_CLK("edp.emc", "edp.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
-#ifdef CONFIG_ARCH_TEGRA_VIC
SHARED_EMC_CLK("vic.emc", "tegra_vic03", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
-#endif
#ifdef CONFIG_TEGRA_DUAL_CBUS
DUAL_CBUS_CLK("msenc.cbus", "tegra_msenc", "msenc", &tegra_clk_c2bus, "msenc", 0, 0),
DUAL_CBUS_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_c2bus, "vde", 0, 0),
DUAL_CBUS_CLK("se.cbus", "tegra12-se", NULL, &tegra_clk_c2bus, "se", 0, 0),
- SHARED_CLK("cap.c2bus", "cap.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
- SHARED_CLK("floor.c2bus", "floor.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0),
+ SHARED_LIMIT("cap.c2bus", "cap.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("cap.throttle.c2bus", "cap_throttle", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("floor.c2bus", "floor.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0),
SHARED_CLK("override.c2bus", "override.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_OVERRIDE),
- SHARED_CLK("edp.c2bus", "edp.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
-#ifdef CONFIG_ARCH_TEGRA_VIC
+ SHARED_LIMIT("edp.c2bus", "edp.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
+
DUAL_CBUS_CLK("vic03.cbus", "tegra_vic03", "vic03", &tegra_clk_c3bus, "vic03", 0, 0),
-#endif
DUAL_CBUS_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_c3bus, "tsec", 0, 0),
- SHARED_CLK("cap.c3bus", "cap.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
- SHARED_CLK("floor.c3bus", "floor.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, 0),
+ SHARED_LIMIT("cap.c3bus", "cap.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("cap.throttle.c3bus", "cap_throttle", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("floor.c3bus", "floor.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, 0),
SHARED_CLK("override.c3bus", "override.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_OVERRIDE),
#else
-#ifdef CONFIG_ARCH_TEGRA_VIC
SHARED_CLK("vic03.cbus", "tegra_vic03", "vic03", &tegra_clk_cbus, "vic03", 0, 0),
-#endif
SHARED_CLK("msenc.cbus","tegra_msenc", "msenc",&tegra_clk_cbus, "msenc", 0, 0),
SHARED_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_cbus, "tsec", 0, 0),
SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0),
SHARED_CLK("se.cbus", "tegra12-se", NULL, &tegra_clk_cbus, "se", 0, 0),
- SHARED_CLK("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
- SHARED_CLK("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0),
+ SHARED_LIMIT("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("cap.throttle.cbus", "cap_throttle", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0),
SHARED_CLK("override.cbus", "override.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_OVERRIDE),
- SHARED_CLK("edp.cbus", "edp.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("edp.cbus", "edp.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
#endif
+ SHARED_CLK("gk20a.gbus", "tegra_gk20a", "gpu", &tegra_clk_gbus, NULL, 0, 0),
+ SHARED_LIMIT("cap.gbus", "cap.gbus", NULL, &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("cap.throttle.gbus", "cap_throttle", NULL, &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("cap.profile.gbus", "profile.gbus", "cap", &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("override.gbus", "override.gbus", NULL, &tegra_clk_gbus, NULL, 0, SHARED_OVERRIDE),
+ SHARED_LIMIT("floor.gbus", "floor.gbus", NULL, &tegra_clk_gbus, NULL, 0, 0),
+ SHARED_LIMIT("floor.profile.gbus", "profile.gbus", "floor", &tegra_clk_gbus, NULL, 0, 0),
+
+ SHARED_CLK("nv.host1x", "tegra_host1x", "host1x", &tegra_clk_host1x, NULL, 0, 0),
+ SHARED_CLK("vi.host1x", "tegra_vi", "host1x", &tegra_clk_host1x, NULL, 0, 0),
+ SHARED_LIMIT("cap.host1x", "cap.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_CEILING),
+ SHARED_LIMIT("floor.host1x", "floor.host1x", NULL, &tegra_clk_host1x, NULL, 0, 0),
+ SHARED_CLK("override.host1x", "override.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_OVERRIDE),
};
+/* VI, ISP buses */
+static struct clk tegra_visp_clks[] = {
+ SHARED_CONNECT("vi.c4bus", "vi.c4bus", NULL, &tegra_clk_c4bus, "vi", 0, 0),
+ SHARED_CONNECT("isp.c4bus", "isp.c4bus", NULL, &tegra_clk_c4bus, "isp", 0, 0),
+ SHARED_CLK("override.c4bus", "override.c4bus", NULL, &tegra_clk_c4bus, NULL, 0, SHARED_OVERRIDE),
+
+ SHARED_CLK("via.vi.c4bus", "via.vi", NULL, &tegra_visp_clks[0], NULL, 0, 0),
+ SHARED_CLK("vib.vi.c4bus", "vib.vi", NULL, &tegra_visp_clks[0], NULL, 0, 0),
+
+ SHARED_CLK("ispa.isp.c4bus", "ispa.isp", NULL, &tegra_visp_clks[1], "ispa", 0, 0),
+ SHARED_CLK("ispb.isp.c4bus", "ispb.isp", NULL, &tegra_visp_clks[1], "ispb", 0, 0),
+};
/* XUSB clocks */
#define XUSB_ID "tegra-xhci"
+/* xusb common clock gate - enabled on init and never disabled */
+static void tegra12_xusb_gate_clk_init(struct clk *c)
+{
+ tegra12_periph_clk_enable(c);
+}
+
+static struct clk_ops tegra_xusb_gate_clk_ops = {
+ .init = tegra12_xusb_gate_clk_init,
+};
+
+static struct clk tegra_clk_xusb_gate = {
+ .name = "xusb_gate",
+ .flags = ENABLE_ON_INIT | PERIPH_NO_RESET,
+ .ops = &tegra_xusb_gate_clk_ops,
+ .rate = 12000000,
+ .max_rate = 48000000,
+ .u.periph = {
+ .clk_num = 143,
+ },
+};
static struct clk tegra_xusb_source_clks[] = {
- PERIPH_CLK("xusb_host_src", XUSB_ID, "host_src", 143, 0x600, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET | PERIPH_ON_APB),
- PERIPH_CLK("xusb_falcon_src", XUSB_ID, "falcon_src", 143, 0x604, 350000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET),
+ PERIPH_CLK("xusb_host_src", XUSB_ID, "host_src", 143, 0x600, 112000000, mux_clkm_pllp_pllc_pllre, MUX | DIV_U71 | PERIPH_NO_RESET | PERIPH_ON_APB),
+ PERIPH_CLK("xusb_falcon_src", XUSB_ID, "falcon_src", 143, 0x604, 336000000, mux_clkm_pllp_pllc_pllre, MUX | DIV_U71 | PERIPH_NO_RESET),
PERIPH_CLK("xusb_fs_src", XUSB_ID, "fs_src", 143, 0x608, 48000000, mux_clkm_48M_pllp_480M, MUX | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 120000000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("xusb_dev_src", XUSB_ID, "dev_src", 95, 0x60c, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET | PERIPH_ON_APB),
- {
- .name = "xusb_hs_src",
- .lookup = {
- .dev_id = XUSB_ID,
- .con_id = "hs_src",
- },
- .ops = &tegra_periph_clk_ops,
- .reg = 0x610,
- .inputs = mux_pllu_60M,
- .flags = PLLU | PERIPH_NO_ENB,
- .max_rate = 60000000,
- .u.periph = {
- .src_mask = 0x1,
- .src_shift = 25,
- },
- },
+ PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 120000000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | DIV_U71 | PERIPH_NO_RESET),
+ PERIPH_CLK("xusb_dev_src", XUSB_ID, "dev_src", 95, 0x60c, 112000000, mux_clkm_pllp_pllc_pllre, MUX | DIV_U71 | PERIPH_NO_RESET | PERIPH_ON_APB),
SHARED_EMC_CLK("xusb.emc", XUSB_ID, "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, 0),
};
+static struct clk tegra_xusb_ss_div2 = {
+ .name = "xusb_ss_div2",
+ .ops = &tegra_clk_m_div_ops,
+ .parent = &tegra_xusb_source_clks[3],
+ .mul = 1,
+ .div = 2,
+ .state = OFF,
+ .max_rate = 61200000,
+};
+
+static struct clk_mux_sel mux_ss_div2_pllu_60M[] = {
+ { .input = &tegra_xusb_ss_div2, .value = 0},
+ { .input = &tegra_pll_u_60M, .value = 1},
+ { 0, 0},
+};
+
+static struct clk tegra_xusb_hs_src = {
+ .name = "xusb_hs_src",
+ .lookup = {
+ .dev_id = XUSB_ID,
+ .con_id = "hs_src",
+ },
+ .ops = &tegra_periph_clk_ops,
+ .reg = 0x610,
+ .inputs = mux_ss_div2_pllu_60M,
+ .flags = MUX | PLLU | PERIPH_NO_ENB,
+ .max_rate = 60000000,
+ .u.periph = {
+ .src_mask = 0x1 << 25,
+ .src_shift = 25,
+ },
+};
+
static struct clk_mux_sel mux_xusb_host[] = {
{ .input = &tegra_xusb_source_clks[0], .value = 0},
{ .input = &tegra_xusb_source_clks[1], .value = 1},
{ .input = &tegra_xusb_source_clks[2], .value = 2},
- { .input = &tegra_xusb_source_clks[5], .value = 5},
+ { .input = &tegra_xusb_hs_src, .value = 5},
{ 0, 0},
};
PERIPH_CLK_EX("xusb_dev", XUSB_ID, "dev", 95, 0, 120000000, mux_xusb_dev, 0, &tegra_clk_coupled_gate_ops),
};
-
#define CLK_DUPLICATE(_name, _dev, _con) \
{ \
.name = _name, \
* table under two names.
*/
struct clk_duplicate tegra_clk_duplicates[] = {
+ CLK_DUPLICATE("uarta", "serial8250.0", NULL),
+ CLK_DUPLICATE("uartb", "serial8250.1", NULL),
+ CLK_DUPLICATE("uartc", "serial8250.2", NULL),
+ CLK_DUPLICATE("uartd", "serial8250.3", NULL),
CLK_DUPLICATE("usbd", "utmip-pad", NULL),
CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
CLK_DUPLICATE("usbd", "tegra-otg", NULL),
CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.1", "dsialp"),
CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.0", "dsi-fixed"),
CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.1", "dsi-fixed"),
- CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
- CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
- CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
- CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
CLK_DUPLICATE("cop", "tegra-avp", "cop"),
CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
CLK_DUPLICATE("cop", "nvavp", "cop"),
CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
+ CLK_DUPLICATE("clk_m", NULL, "apb_pclk"),
CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
CLK_DUPLICATE("vde.cbus", "nvavp", "vde"),
CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
- CLK_DUPLICATE("host1x", "tegra_host1x", "host1x"),
- CLK_DUPLICATE("gpu", "tegra_gk20a", "PLLG_ref"),
+ CLK_DUPLICATE("actmon", "tegra_host1x", "actmon"),
+ CLK_DUPLICATE("gpu_ref", "tegra_gk20a", "PLLG_ref"),
+ CLK_DUPLICATE("gbus", "tegra_gk20a", "PLLG_out"),
CLK_DUPLICATE("pll_p_out5", "tegra_gk20a", "pwr"),
- CLK_DUPLICATE("isp", "tegra_isp", NULL),
- CLK_DUPLICATE("isp", "tegra_isp.1", NULL),
- CLK_DUPLICATE("vi", "tegra_vi", NULL),
- CLK_DUPLICATE("vi", "tegra_vi.1", NULL),
+ CLK_DUPLICATE("ispa.isp.c4bus", "tegra_isp", "isp"),
+ CLK_DUPLICATE("ispb.isp.c4bus", "tegra_isp.1", "isp"),
+ CLK_DUPLICATE("via.vi.c4bus", "tegra_vi", "vi"),
+ CLK_DUPLICATE("vib.vi.c4bus", "tegra_vi.1", "vi"),
CLK_DUPLICATE("csi", "tegra_vi", "csi"),
CLK_DUPLICATE("csi", "tegra_vi.1", "csi"),
+ CLK_DUPLICATE("csus", "tegra_vi", "csus"),
+ CLK_DUPLICATE("vim2_clk", "tegra_vi.1", "vim2_clk"),
+ CLK_DUPLICATE("cilab", "tegra_vi", "cilab"),
+ CLK_DUPLICATE("cilcd", "tegra_vi.1", "cilcd"),
+ CLK_DUPLICATE("cile", "tegra_vi.1", "cile"),
CLK_DUPLICATE("i2s0", NULL, "i2s0"),
CLK_DUPLICATE("i2s1", NULL, "i2s1"),
CLK_DUPLICATE("i2s2", NULL, "i2s2"),
CLK_DUPLICATE("dam1", NULL, "dam1"),
CLK_DUPLICATE("dam2", NULL, "dam2"),
CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
+ CLK_DUPLICATE("mclk", NULL, "default_mclk"),
};
struct clk *tegra_ptr_clks[] = {
&tegra_pll_a_out0,
&tegra_pll_d,
&tegra_pll_d_out0,
+ &tegra_clk_xusb_gate,
&tegra_pll_u,
&tegra_pll_u_480M,
&tegra_pll_u_60M,
&tegra_clk_blink,
&tegra_clk_cop,
&tegra_clk_sbus_cmplx,
+ &tegra_clk_ahb,
+ &tegra_clk_apb,
&tegra_clk_emc,
+ &tegra_clk_host1x,
#ifdef CONFIG_TEGRA_DUAL_CBUS
&tegra_clk_c2bus,
&tegra_clk_c3bus,
&tegra_clk_cbus,
#endif
&tegra_clk_gpu,
+ &tegra_clk_gbus,
+ &tegra_clk_isp,
+ &tegra_clk_c4bus,
+};
+
+struct clk *tegra_ptr_camera_mclks[] = {
+ &tegra_camera_mclk,
+ &tegra_camera_mclk2,
};
/* Return true from this function if the target rate can be locked without
tegra_pll_p_out1.u.pll_div.default_rate = 28800000;
tegra_pll_p_out3.u.pll_div.default_rate = 72000000;
tegra_clk_sbus_cmplx.u.system.threshold = 108000000;
+ tegra_clk_host1x.u.periph.threshold = 108000000;
break;
case 408000000:
tegra_pll_p_out1.u.pll_div.default_rate = 9600000;
tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
+ tegra_clk_host1x.u.periph.threshold = 204000000;
break;
case 204000000:
tegra_pll_p_out1.u.pll_div.default_rate = 4800000;
tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
+ tegra_clk_host1x.u.periph.threshold = 204000000;
break;
default:
pr_err("tegra: PLLP rate: %lu is not supported\n", pllp_rate);
clkdev_add(&c->lookup);
}
+/* Direct access to CPU clock sources fot CPU idle driver */
+int tegra12_cpu_g_idle_rate_exchange(unsigned long *rate)
+{
+ int ret = 0;
+ struct clk *dfll = tegra_clk_cpu_cmplx.parent->u.cpu.dynamic;
+ unsigned long old_rate, new_rate, flags;
+
+ if (!dfll || !tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail))
+ return -EPERM;
+
+ /* Clipping min to oscillator rate is pretty much arbitrary */
+ new_rate = max(*rate, tegra_clk_m.rate);
+
+ clk_lock_save(dfll, &flags);
+
+ old_rate = clk_get_rate_locked(dfll);
+ *rate = old_rate;
+ if (new_rate != old_rate)
+ ret = clk_set_rate_locked(dfll, new_rate);
+
+ clk_unlock_restore(dfll, &flags);
+ return ret;
+}
+
+int tegra12_cpu_lp_idle_rate_exchange(unsigned long *rate)
+{
+ int ret = 0;
+ struct clk *backup = tegra_clk_cpu_cmplx.parent->u.cpu.backup;
+ unsigned long old_rate, flags;
+ unsigned long new_rate = min(
+ *rate, tegra_clk_cpu_cmplx.parent->u.cpu.backup_rate);
+
+ clk_lock_save(backup, &flags);
+
+ old_rate = clk_get_rate_locked(backup);
+ *rate = old_rate;
+ if (new_rate != old_rate)
+ ret = clk_set_rate_locked(backup, new_rate);
+
+ clk_unlock_restore(backup, &flags);
+ return ret;
+}
+
void tegra_edp_throttle_cpu_now(u8 factor)
{
/* empty definition for tegra12 */
#ifdef CONFIG_PM_SLEEP
static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
- PERIPH_CLK_SOURCE_NUM + 25];
+ PERIPH_CLK_SOURCE_NUM + 26];
static int tegra12_clk_suspend(void)
{
*ctx++ = clk_readl(MISC_CLK_ENB);
*ctx++ = clk_readl(CLK_MASK_ARM);
+ *ctx++ = clk_get_rate_all_locked(&tegra_clk_emc);
return 0;
}
static void tegra12_clk_resume(void)
{
- unsigned long off;
+ unsigned long off, rate;
const u32 *ctx = clk_rst_suspend;
u32 val;
u32 plla_base;
clk_writel(*ctx++, CPU_SOFTRST_CTRL1);
clk_writel(*ctx++, CPU_SOFTRST_CTRL2);
- /* FIXME: DFLL? */
/* Since we are going to reset devices and switch clock sources in this
* function, plls and secondary dividers is required to be enabled. The
* actual value will be restored back later. Note that boot plls: pllm,
off <= PERIPH_CLK_SOURCE_VIC; off += 4)
clk_writel(*ctx++, off);
+ udelay(RESET_PROPAGATION_DELAY);
+
clk_writel(*ctx++, RST_DEVICES_L);
clk_writel(*ctx++, RST_DEVICES_H);
clk_writel(*ctx++, RST_DEVICES_U);
clk_writel(*ctx++, CLK_OUT_ENB_U);
/* For LP0 resume, clk to lpcpu is required to be on */
- /* FIXME: should be saved as on? */
val = *ctx++;
val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN;
clk_writel(val, CLK_OUT_ENB_V);
p = tegra_clk_emc.parent;
tegra12_periph_clk_init(&tegra_clk_emc);
+ /* Turn Off pll_m if it was OFF before suspend, and emc was not switched
+ to pll_m across suspend; re-init pll_m to sync s/w and h/w states */
+ if ((tegra_pll_m.state == OFF) &&
+ (&tegra_pll_m != tegra_clk_emc.parent))
+ tegra12_pllm_clk_disable(&tegra_pll_m);
+ tegra12_pllm_clk_init(&tegra_pll_m);
+
if (p != tegra_clk_emc.parent) {
- /* FIXME: old parent is left enabled here even if EMC was its
- only child before suspend (may happen on Tegra11 !!) */
pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)",
p->name, p->refcnt, tegra_clk_emc.parent->name,
tegra_clk_emc.parent->refcnt);
- BUG_ON(!p->refcnt);
- p->refcnt--;
+ /* emc switched to the new parent by low level code, but ref
+ count and s/w state need to be updated */
+ clk_disable(p);
+ clk_enable(tegra_clk_emc.parent);
+ }
- /* the new parent is enabled by low level code, but ref count
- need to be updated up to the root */
- p = tegra_clk_emc.parent;
- while (p && ((p->refcnt++) == 0))
- p = p->parent;
+ rate = clk_get_rate_all_locked(&tegra_clk_emc);
+ if (*ctx != rate) {
+ tegra_dvfs_set_rate(&tegra_clk_emc, rate);
+ if (p == tegra_clk_emc.parent) {
+ rate = clk_get_rate_all_locked(p);
+ tegra_dvfs_set_rate(p, rate);
+ }
}
tegra_emc_timing_invalidate();
};
#endif
+/* Tegra12 CPU clock and reset control functions */
+static void tegra12_wait_cpu_in_reset(u32 cpu)
+{
+ unsigned int reg;
+
+ do {
+ reg = readl(reg_clk_base +
+ TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+ cpu_relax();
+ } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
+
+ return;
+}
+
+static void tegra12_put_cpu_in_reset(u32 cpu)
+{
+ writel(CPU_RESET(cpu),
+ reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+ dmb();
+}
+
+static void tegra12_cpu_out_of_reset(u32 cpu)
+{
+ writel(CPU_RESET(cpu),
+ reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+ wmb();
+}
+
+static void tegra12_enable_cpu_clock(u32 cpu)
+{
+ unsigned int reg;
+
+ writel(CPU_CLOCK(cpu),
+ reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+ reg = readl(reg_clk_base +
+ TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+}
+static void tegra12_disable_cpu_clock(u32 cpu)
+{
+}
+
+static struct tegra_cpu_car_ops tegra12_cpu_car_ops = {
+ .wait_for_reset = tegra12_wait_cpu_in_reset,
+ .put_in_reset = tegra12_put_cpu_in_reset,
+ .out_of_reset = tegra12_cpu_out_of_reset,
+ .enable_clock = tegra12_enable_cpu_clock,
+ .disable_clock = tegra12_disable_cpu_clock,
+};
+
+void __init tegra12_cpu_car_ops_init(void)
+{
+ tegra_cpu_car_ops = &tegra12_cpu_car_ops;
+}
+
+static void tegra12_init_xusb_clocks(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
+ tegra12_init_one_clock(&tegra_xusb_source_clks[i]);
+
+ tegra12_init_one_clock(&tegra_xusb_ss_div2);
+ tegra12_init_one_clock(&tegra_xusb_hs_src);
+
+ for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
+ tegra12_init_one_clock(&tegra_xusb_coupled_clks[i]);
+}
+
void __init tegra12x_init_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
tegra12_init_one_clock(tegra_ptr_clks[i]);
+ /* Fix bug in simulator clock routing */
+ if (tegra_platform_is_linsim()) {
+ for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) {
+ if (!strcmp("msenc", tegra_list_clks[i].name)) {
+ tegra_list_clks[i].u.periph.clk_num = 60;
+ tegra_list_clks[i].reg = 0x170;
+ tegra_list_clks[i].flags &= ~MUX8;
+ }
+ }
+ }
+
for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
tegra12_init_one_clock(&tegra_list_clks[i]);
- for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
- c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
- if (!c) {
- pr_err("%s: Unknown duplicate clock %s\n", __func__,
- tegra_clk_duplicates[i].name);
- continue;
- }
+ for (i = 0; i < ARRAY_SIZE(tegra_visp_clks); i++)
+ tegra12_init_one_clock(&tegra_visp_clks[i]);
- tegra_clk_duplicates[i].lookup.clk = c;
- clkdev_add(&tegra_clk_duplicates[i].lookup);
- }
+ for (i = 0; i < ARRAY_SIZE(tegra_ptr_camera_mclks); i++)
+ tegra12_init_one_clock(tegra_ptr_camera_mclks[i]);
for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
tegra12_init_one_clock(&tegra_sync_source_list[i]);
for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
tegra12_init_one_clock(&tegra_clk_out_list[i]);
- for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
- tegra12_init_one_clock(&tegra_xusb_source_clks[i]);
+ tegra12_init_xusb_clocks();
- for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
- tegra12_init_one_clock(&tegra_xusb_coupled_clks[i]);
+ for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+ c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+ if (!c) {
+ pr_err("%s: Unknown duplicate clock %s\n", __func__,
+ tegra_clk_duplicates[i].name);
+ continue;
+ }
+
+ tegra_clk_duplicates[i].lookup.clk = c;
+ clkdev_add(&tegra_clk_duplicates[i].lookup);
+ }
/* Initialize to default */
tegra_init_cpu_edp_limits(0);
+ tegra12_cpu_car_ops_init();
+
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&tegra_clk_syscore_ops);
#endif
Code Review / linux-3.10.git / blobdiff