ARM: tegra11: power: Add AP40X core EDP tables
[linux-3.10.git] / arch / arm / mach-tegra / tegra11_edp.c
index db63057..933108f 100644 (file)
@@ -640,6 +640,123 @@ static struct core_edp_entry core_edp_table[] = {
                        },
                },
        },
+       /* SKU 8 */
+       {
+               .sku            = 0x8,          /* SKU = 8 */
+               .process_id     = -1,           /* any process id */
+               .cap_mA         = 6000,         /* 6A cap */
+               .mult           = 1000000,      /* MHZ */
+               .cap_scpu_on    = {
+                       /* favor emc */
+                       {       /* core modules power state 0 (all ON) */
+                               {{ 744, 672 },
+                                { 744, 636 },
+                                { 744, 636 },
+                                { 744, 576 },
+                               },
+                       },
+                       /* balanced profile */
+                       {       /* core modules power state 0 (all ON) */
+                               {{ 744, 672 },
+                                { 744, 636 },
+                                { 744, 636 },
+                                { 744, 576 },
+                               },
+                       },
+                       /* favor gpu */
+                       {       /* core modules power state 0 (all ON) */
+                               {{ 744, 672 },
+                                { 624, 672 },
+                                { 624, 672 },
+                                { 624, 636 },
+                               }
+                       },
+               },
+               .cap_scpu_off   = {
+                       /* favor emc */
+                       {       /* core modules power state 0 (all ON) */
+                               {{ 744, 672 },
+                                { 744, 672 },
+                                { 744, 672 },
+                                { 744, 648 },
+                               },
+                       },
+                       /* balanced profile */
+                       {       /* core modules power state 0 (all ON) */
+                               {{ 744, 672 },
+                                { 744, 672 },
+                                { 744, 672 },
+                                { 744, 648 },
+                               },
+                       },
+                       /* favor gpu */
+                       {       /* core modules power state 0 (all ON) */
+                               {{ 744, 672 },
+                                { 744, 672 },
+                                { 744, 672 },
+                                { 744, 648 },
+                               }
+                       },
+               },
+       },
+       {
+               .sku            = 0x8,          /* SKU = 8 */
+               .process_id     = -1,           /* any process id */
+               .cap_mA         = 8000,         /* 8A cap */
+               .mult           = 1000000,      /* MHZ */
+               .cap_scpu_on    = {
+                       /* favor emc */
+                       {       /* core modules power state 0 (all ON) */
+                               {{ 744, 672 },
+                                { 744, 672 },
+                                { 744, 672 },
+                                { 744, 648 },
+                               },
+                       },
+                       /* balanced profile */
+                       {       /* core modules power state 0 (all ON) */
+                               {{ 744, 672 },
+                                { 744, 672 },
+                                { 744, 672 },
+                                { 744, 648 },
+                               },
+                       },
+                       /* favor gpu */
+                       {       /* core modules power state 0 (all ON) */
+                               {{ 744, 672 },
+                                { 744, 672 },
+                                { 744, 672 },
+                                { 744, 648 },
+                               }
+                       },
+               },
+               .cap_scpu_off   = {
+                       /* favor emc */
+                       {       /* core modules power state 0 (all ON) */
+                               {{ 744, 672 },
+                                { 744, 672 },
+                                { 744, 672 },
+                                { 744, 648 },
+                               },
+                       },
+                       /* balanced profile */
+                       {       /* core modules power state 0 (all ON) */
+                               {{ 744, 672 },
+                                { 744, 672 },
+                                { 744, 672 },
+                                { 744, 648 },
+                               },
+                       },
+                       /* favor gpu */
+                       {       /* core modules power state 0 (all ON) */
+                               {{ 792, 828 },
+                                { 792, 816 },
+                                { 792, 804 },
+                                { 792, 648 },
+                               }
+                       },
+               },
+       },
 };
 
 #ifdef CONFIG_TEGRA_EDP_LIMITS
@@ -777,7 +894,7 @@ static struct core_edp_entry *find_edp_entry(int sku, unsigned int regulator_mA)
        if ((sku == 0x5) || (sku == 0x6)) {
                if (regulator_mA >= 8000)
                        return NULL;            /* no edp limits above 8A */
-       } else if ((sku == 0x3) || (sku == 0x4)) {
+       } else if ((sku == 0x3) || (sku == 0x4) || (sku == 0x8)) {
                if (regulator_mA >= 8000)
                        regulator_mA = 8000;    /* apply 8A table above 8A */
        } else {