#include <linux/syscore_ops.h>
#include <linux/platform_device.h>
#include <linux/clk/tegra.h>
+#include <linux/tegra-soc.h>
+#include <linux/tegra-powergate.h>
#include <asm/clkdev.h>
#include <mach/edp.h>
-#include <mach/hardware.h>
#include <mach/mc.h>
-#include <mach/powergate.h>
#include "clock.h"
#include "fuse.h"
static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
static void __iomem *reg_xusb_padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
-#define MISC_GP_HIDREV 0x804
#define MISC_GP_TRANSACTOR_SCRATCH_0 0x864
#define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE (0x1 << 1)
#define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE (0x1 << 2)
__raw_writel(value, reg_pmc_base + (reg))
#define pmc_readl(reg) \
__raw_readl(reg_pmc_base + (reg))
-#define chipid_readl() \
- __raw_readl(misc_gp_base + MISC_GP_HIDREV)
#define xusb_padctl_writel(value, reg) \
__raw_writel(value, reg_xusb_padctl_base + (reg))
#define xusb_padctl_readl(reg) \
#define clk_writel_delay(value, reg) \
do { \
- __raw_writel((value), reg_clk_base + (reg)); \
+ __raw_writel((value), reg_clk_base + (reg)); \
+ __raw_readl(reg_clk_base + (reg)); \
udelay(2); \
} while (0)
#define pll_writel_delay(value, reg) \
do { \
- __raw_writel((value), reg_clk_base + (reg)); \
+ __raw_writel((value), reg_clk_base + (reg)); \
+ __raw_readl(reg_clk_base + (reg)); \
udelay(1); \
} while (0)
* flush the write operation in apb bus. This will avoid the
* peripheral access after disabling clock*/
if (c->flags & PERIPH_ON_APB)
- val = chipid_readl();
+ val = tegra_read_chipid();
clk_writel_delay(
PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
* will avoid the peripheral access after disabling
* clock */
if (c->flags & PERIPH_ON_APB)
- val = chipid_readl();
+ val = tegra_read_chipid();
clk_writel(PERIPH_CLK_TO_BIT(c),
PERIPH_CLK_TO_RST_SET_REG(c));
D_AUDIO_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
D_AUDIO_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
D_AUDIO_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 24730000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 24730000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("i2c3", "tegra11-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
PERIPH_CLK("i2c4", "tegra11-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
PERIPH_CLK("i2c5", "tegra11-i2c.4", "div-clk", 47, 0x128, 64000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, 0),
+ PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("mipi-cal-fixed", "mipi-cal-fixed", NULL, 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
PERIPH_CLK("uarta", "serial-tegra.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartb", "serial-tegra.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
SHARED_CLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
SHARED_EMC_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
- SHARED_EMC_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
- SHARED_EMC_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC1)),
- SHARED_EMC_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC2)),
+ SHARED_EMC_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc,
+ NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC1)),
+ SHARED_EMC_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc,
+ NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC2)),
+ SHARED_EMC_CLK("mon_cpu.emc", "tegra_mon", "cpu_emc",
+ &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("usbd.emc", "tegra-udc.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
SHARED_EMC_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),