ARM: tegra: clock: Update CPU cluster switch clock control
[linux-3.10.git] / arch / arm / mach-tegra / tegra11_clocks.c
index 90a646c..eb412a8 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/tegra11_clocks.c
  *
- * Copyright (C) 2011-2012 NVIDIA Corporation
+ * Copyright (C) 2011-2013 NVIDIA Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
 #define USB_PLLS_USE_LOCKDET                   (1<<6)
 #define USB_PLLS_ENABLE_SWCTL                  ((1<<2) | (1<<0))
 
+/* CPU clock trimmers */
+#define CPU_FINETRIM_BYP                       0x4d0
+#define CPU_FINETRIM_SELECT                    0x4d4
+#define CPU_FINETRIM_DR                                0x4d8
+#define CPU_FINETRIM_DF                                0x4dc
+#define CPU_FINETRIM_F                         0x4e0
+#define CPU_FINETRIM_R                         0x4e4
+
 /* DFLL */
 #define DFLL_BASE                              0x2f4
 #define DFLL_BASE_RESET                                (1<<0)
@@ -1149,8 +1157,10 @@ static int tegra11_cpu_clk_dfll_on(struct clk *c, unsigned long rate,
                        }
                }
 
+               tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
                ret = clk_set_parent(c->parent, dfll);
                if (ret) {
+                       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
                        pr_err("Failed to switch cpu to %s\n", dfll->name);
                        return ret;
                }
@@ -1159,6 +1169,7 @@ static int tegra11_cpu_clk_dfll_on(struct clk *c, unsigned long rate,
 
                /* prevent legacy dvfs voltage scaling */
                tegra_dvfs_dfll_mode_set(c->dvfs, rate);
+               tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        }
        return 0;
 }
@@ -1173,7 +1184,23 @@ static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
 
        rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost);
        pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main;
+       dfll_rate_min = max(rate, dfll_rate_min);
+
+       /* set target rate last time in dfll mode */
+       if (old_rate != dfll_rate_min) {
+               ret = tegra_dvfs_set_rate(c, dfll_rate_min);
+               if (!ret)
+                       ret = clk_set_rate(dfll, dfll_rate_min);
 
+               if (ret) {
+                       pr_err("Failed to set cpu rate %lu on source %s\n",
+                              dfll_rate_min, dfll->name);
+                       return ret;
+               }
+       }
+
+       /* unlock dfll - release volatge rail control */
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
        ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
        if (ret) {
                pr_err("Failed to unlock %s\n", dfll->name);
@@ -1181,7 +1208,7 @@ static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
        }
 
        /* restore legacy dvfs operations and set appropriate voltage */
-       ret = tegra_dvfs_dfll_mode_clear(c->dvfs, max(rate, dfll_rate_min));
+       ret = tegra_dvfs_dfll_mode_clear(c->dvfs, dfll_rate_min);
        if (ret) {
                pr_err("Failed to set cpu rail for rate %lu\n", rate);
                goto back_to_dfll;
@@ -1205,11 +1232,13 @@ static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
        if (old_rate <= rate)
                tegra_dvfs_set_rate(c, rate);
 
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return 0;
 
 back_to_dfll:
        tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
        tegra_dvfs_dfll_mode_set(c->dvfs, old_rate);
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return ret;
 }
 
@@ -1226,7 +1255,8 @@ static int tegra11_cpu_clk_set_rate(struct clk *c, unsigned long rate)
        if (c->dvfs) {
                if (!c->dvfs->dvfs_rail)
                        return -ENOSYS;
-               else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate)) {
+               else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate) &&
+                        (c->boot_rate < rate)) {
                        WARN(1, "Increasing CPU rate while regulator is not"
                                " ready is not allowed\n");
                        return -ENOSYS;
@@ -1330,6 +1360,7 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
        const struct clk_mux_sel *sel;
        unsigned long rate = clk_get_rate(c->parent);
        struct clk *dfll = c->parent->u.cpu.dynamic ? : p->u.cpu.dynamic;
+       struct clk *p_source_old = NULL;
        struct clk *p_source;
 
        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
@@ -1387,6 +1418,7 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                return 0;       /* already switched - exit */
        }
 
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
        if (c->parent->parent->parent == dfll) {
                /* G (DFLL selected as clock source) => LP switch:
                 * turn DFLL into open loop mode ("release" VDD_CPU rail)
@@ -1396,28 +1428,38 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                if (ret)
                        goto abort;
 
+               ret = tegra_dvfs_rail_dfll_mode_set_cold(tegra_cpu_rail);
+               if (ret)
+                       goto abort;
+
                p_source = rate <= p->u.cpu.backup_rate ?
                        p->u.cpu.backup : p->u.cpu.main;
                ret = clk_set_rate(p_source, rate);
                if (ret)
                        goto abort;
-       } else if (p->parent->parent == dfll) {
+       } else if ((p->parent->parent == dfll) || ((p->u.cpu.dynamic == dfll) &&
+                       (dfll->state != UNINITIALIZED) && use_dfll)) {
                /* LP => G (DFLL selected as clock source) switch:
                 * set DFLL rate ready (DFLL is still disabled)
                 * (set target p_source as dfll, G source is already selected)
                 */
                p_source = dfll;
-               ret = clk_set_rate(p_source, rate);
+               ret = clk_set_rate(dfll,
+                       tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail) ? rate :
+                       max(rate, p->dvfs->dfll_data.use_dfll_rate_min));
                if (ret)
                        goto abort;
        } else
-               /* DFLL is not selcted on either side of the switch:
+               /* DFLL is not selected on either side of the switch:
                 * set target p_source equal to current clock source
                 */
                p_source = c->parent->parent->parent;
 
        /* Switch new parent to target clock source if necessary */
        if (p->parent->parent != p_source) {
+               clk_enable(p->parent->parent);
+               clk_enable(p->parent);
+               p_source_old = p->parent->parent;
                ret = clk_set_parent(p->parent, p_source);
                if (ret) {
                        pr_err("%s: Failed to set parent %s for %s\n",
@@ -1444,19 +1486,46 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
        /* Disabling old parent scales old mode voltage rail */
        if (c->refcnt)
                clk_disable(c->parent);
+       if (p_source_old) {
+               clk_disable(p->parent);
+               clk_disable(p_source_old);
+       }
 
        clk_reparent(c, p);
 
-       /* Lock DFLL now (resume closed loop VDD_CPU control) */
-       if (p_source == dfll)
-               tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+       /*
+        * Lock DFLL now (resume closed loop VDD_CPU control).
+        * G CPU operations are always resumed on DFLL if it can be used, even
+        * when autoswitch between PLL and DFLL is allowed, and resume rate is
+        * low enough to run on PLL. This makes CPU clock source ready for
+        * speedy ramp with cl_dvfs controlling volatge (and that ramp is the
+        * most likely reason for going to G CPU in the 1st place)
+        */
+       if (p_source == dfll) {
+               if (tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail)) {
+                       tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+               } else {
+                       clk_set_rate(dfll, rate);
+                       tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+                       tegra_dvfs_dfll_mode_set(p->dvfs, rate);
+               }
+       }
 
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return 0;
 
 abort:
        /* Re-lock DFLL if necessary after aborted switch */
-       if (c->parent->parent->parent == dfll)
+       if (c->parent->parent->parent == dfll) {
+               clk_set_rate(dfll, rate);
                tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+       }
+       if (p_source_old) {
+               clk_disable(p->parent);
+               clk_disable(p_source_old);
+       }
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
+
        pr_err("%s: aborted switch from %s to %s\n",
               __func__, c->parent->name, p->name);
        return ret;
@@ -1778,15 +1847,28 @@ static int tegra11_pll_clk_wait_for_lock(
 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
 #if USE_PLL_LOCK_BITS
        int i;
+       u32 val = 0;
+
        for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) {
                udelay(PLL_PRE_LOCK_DELAY);
-               if ((clk_readl(lock_reg) & lock_bits) == lock_bits) {
+               val = clk_readl(lock_reg);
+               if ((val & lock_bits) == lock_bits) {
                        udelay(PLL_POST_LOCK_DELAY);
                        return 0;
                }
        }
-       pr_err("Timed out waiting for lock bit on pll %s\n", c->name);
-       return -1;
+
+       /* PLLCX lock bits may fluctuate after the lock - don't report timeout
+          in this case (phase lock bit happens to uniquely identify PLLCX) */
+       if (lock_bits & PLLCX_BASE_PHASE_LOCK) {
+               pr_debug("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+                        c->name, lock_reg, val);
+               return 0;
+       } else {
+               pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+                      c->name, lock_reg, val);
+               return -ETIMEDOUT;
+       }
 #endif
        udelay(c->u.pll.lock_delay);
 #endif
@@ -3438,11 +3520,33 @@ static struct clk_ops tegra_plle_ops = {
 
 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
 /* DFLL operations */
+static void tune_cpu_trimmers(bool trim_high)
+{
+       if (trim_high) {
+               clk_writel(0, CPU_FINETRIM_SELECT);
+               clk_writel(0, CPU_FINETRIM_DR);
+               clk_writel(0, CPU_FINETRIM_R);
+       } else {
+               clk_writel(0x3F, CPU_FINETRIM_SELECT);
+               clk_writel(0x3F, CPU_FINETRIM_DR);
+               clk_writel(0xFFF, CPU_FINETRIM_R);
+       }
+       wmb();
+       clk_readl(CPU_FINETRIM_R);
+}
+
 static void __init tegra11_dfll_cpu_late_init(struct clk *c)
 {
 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
        int ret;
-       struct clk *cpu = tegra_get_clock_by_name("cpu");
+       struct clk *cpu = tegra_get_clock_by_name("cpu_g");
+
+       if (!cpu || !cpu->dvfs) {
+               pr_err("%s: CPU dvfs is not present\n", __func__);
+               return;
+       }
+       if (cpu->dvfs->speedo_id > 0)   /* A01P and above parts */
+               tegra_dvfs_set_dfll_tune_trimmers(cpu->dvfs, tune_cpu_trimmers);
 
 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
        u32 netlist, patchid;
@@ -3462,7 +3566,7 @@ static void __init tegra11_dfll_cpu_late_init(struct clk *c)
                c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device);
 
                use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
-               tegra_dvfs_set_dfll_range(cpu->parent->dvfs, use_dfll);
+               tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll);
                pr_info("Tegra CPU DFLL is initialized\n");
        }
 #endif
@@ -5403,7 +5507,7 @@ static struct clk tegra_pll_m_out1 = {
        .parent    = &tegra_pll_m,
        .reg       = 0x94,
        .reg_shift = 0,
-       .max_rate  = 600000000,
+       .max_rate  = 1066000000,
 };
 
 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
@@ -6492,9 +6596,6 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("sbc4",      "spi-tegra114.3",       NULL,   68,     0x1b4,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("sbc5",      "spi-tegra114.4",       NULL,   104,    0x3c8,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("sbc6",      "spi-tegra114.5",       NULL,   105,    0x3cc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata_oob",  "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata",      "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata_cold", "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   PERIPH_ON_APB),
        PERIPH_CLK_EX("ndflash", "tegra_nand",          NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB,  &tegra_nand_clk_ops),
        PERIPH_CLK("ndspeed",   "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
@@ -6516,7 +6617,7 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("i2c2",      "tegra11-i2c.1",        "div-clk",      54,     0x198,  136000000, mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
        PERIPH_CLK("i2c3",      "tegra11-i2c.2",        "div-clk",      67,     0x1b8,  136000000, mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
        PERIPH_CLK("i2c4",      "tegra11-i2c.3",        "div-clk",      103,    0x3c4,  136000000, mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
-       PERIPH_CLK("i2c5",      "tegra11-i2c.4",        "div-clk",      47,     0x128,  58300000,  mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
+       PERIPH_CLK("i2c5",      "tegra11-i2c.4",        "div-clk",      47,     0x128,  64000000,  mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
        PERIPH_CLK("mipi-cal",  "mipi-cal",             NULL,   56,     0,      60000000,  mux_clk_m,   0),
        PERIPH_CLK("uarta",     "tegra_uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
        PERIPH_CLK("uartb",     "tegra_uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
@@ -6525,8 +6626,8 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("uarte",     "tegra_uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
-       PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
-       PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
+       PERIPH_CLK_EX("vi",     "vi",                   "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
+       PERIPH_CLK("vi_sensor", "vi",                   "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
        PERIPH_CLK("msenc",     "msenc",                NULL,   60,     0x170,  600000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
@@ -6546,12 +6647,12 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK_EX("dsib",   "tegradc.1",            "dsib", 82,     0x4b8,  500000000, mux_plld_out0_plld2_out0,    MUX | PLLD,     &tegra_dsi_clk_ops),
        PERIPH_CLK("dsi1-fixed", "tegradc.0",           "dsi-fixed",    0,      0,      108000000, mux_pllp_out3,       PERIPH_NO_ENB),
        PERIPH_CLK("dsi2-fixed", "tegradc.1",           "dsi-fixed",    0,      0,      108000000, mux_pllp_out3,       PERIPH_NO_ENB),
-       PERIPH_CLK("csi",       "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0),
-       PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
-       PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
-       PERIPH_CLK("cilab",     "tegra_camera",         "cilab", 144,   0x614,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
-       PERIPH_CLK("cilcd",     "tegra_camera",         "cilcd", 145,   0x618,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
-       PERIPH_CLK("cile",      "tegra_camera",         "cile",  146,   0x61c,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
+       PERIPH_CLK("csi",       "vi",                   "csi",  52,     0,      102000000, mux_pllp_out3,               0),
+       PERIPH_CLK("isp",       "vi",                   "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
+       PERIPH_CLK("csus",      "vi",                   "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
+       PERIPH_CLK("cilab",     "vi",                   "cilab", 144,   0x614,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
+       PERIPH_CLK("cilcd",     "vi",                   "cilcd", 145,   0x618,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
+       PERIPH_CLK("cile",      "vi",                   "cile",  146,   0x61c,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
        PERIPH_CLK("dsialp",    "tegradc.0",            "dsialp", 147,  0x620,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
        PERIPH_CLK("dsiblp",    "tegradc.1",            "dsiblp", 148,  0x624,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
 
@@ -6579,6 +6680,7 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("usb2.sclk", "tegra-ehci.1",         "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("usb3.sclk", "tegra-ehci.2",         "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("wake.sclk", "wake_sclk",            "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("camera.sclk",       "vi",           "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("mon.avp",   "tegra_actmon",         "avp",  &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("cap.sclk",  "cap_sclk",             NULL,   &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
        SHARED_CLK("cap.throttle.sclk", "cap_throttle", NULL,   &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
@@ -6608,11 +6710,12 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("msenc.emc", "tegra_msenc",          "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
        SHARED_CLK("tsec.emc",  "tegra_tsec",           "emc",  &tegra_clk_emc, NULL, 0, 0),
        SHARED_CLK("sdmmc4.emc", "sdhci-tegra.3",       "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("camera.emc", "tegra_camera",        "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
+       SHARED_CLK("camera.emc", "vi",                  "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
        SHARED_CLK("iso.emc",   "iso",                  "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
        SHARED_CLK("floor.emc", "floor.emc",            NULL,   &tegra_clk_emc, NULL, 0, 0),
        SHARED_CLK("override.emc", "override.emc",      NULL,   &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE),
        SHARED_CLK("edp.emc",   "edp.emc",              NULL,   &tegra_clk_emc, NULL, 0, SHARED_CEILING),
+       SHARED_CLK("battery.emc", "battery_edp",        "emc",  &tegra_clk_emc, NULL, 0, SHARED_CEILING),
 
 #ifdef CONFIG_TEGRA_DUAL_CBUS
        DUAL_CBUS_CLK("3d.cbus",        "tegra_gr3d",           "gr3d", &tegra_clk_c2bus, "3d",  0, 0),
@@ -6623,6 +6726,8 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("floor.c2bus",       "floor.c2bus",          NULL,   &tegra_clk_c2bus, NULL,  0, 0),
        SHARED_CLK("override.c2bus",    "override.c2bus",       NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_OVERRIDE),
        SHARED_CLK("edp.c2bus",         "edp.c2bus",            NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("battery.c2bus",     "battery_edp",          "gpu",  &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.profile.c2bus", "profile.c2bus",        NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
 
        DUAL_CBUS_CLK("msenc.cbus",     "tegra_msenc",          "msenc",  &tegra_clk_c3bus, "msenc", 0, 0),
        DUAL_CBUS_CLK("tsec.cbus",      "tegra_tsec",           "tsec",   &tegra_clk_c3bus, "tsec", 0, 0),
@@ -6645,6 +6750,8 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("floor.cbus", "floor.cbus",          NULL,   &tegra_clk_cbus, NULL,  0, 0),
        SHARED_CLK("override.cbus", "override.cbus",    NULL,   &tegra_clk_cbus, NULL,  0, SHARED_OVERRIDE),
        SHARED_CLK("edp.cbus",  "edp.cbus",             NULL,   &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("battery.cbus", "battery_edp",       "gpu",  &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.profile.cbus", "profile.cbus",  NULL,   &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
 #endif
 };
 
@@ -6759,6 +6866,8 @@ struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
        CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
        CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
+       CLK_DUPLICATE("cl_dvfs_soc", "tegra11-i2c.4", NULL),
+       CLK_DUPLICATE("cl_dvfs_ref", "tegra11-i2c.4", NULL),
        CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL),
        CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL),
        CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL),
@@ -6938,16 +7047,47 @@ static void tegra11_init_one_clock(struct clk *c)
        clkdev_add(&c->lookup);
 }
 
-int tegra11_cpu_backup_rate_exchange(unsigned long *rate)
+/* Direct access to CPU clock sources fot CPU idle driver */
+int tegra11_cpu_g_idle_rate_exchange(unsigned long *rate)
+{
+       int ret = 0;
+       struct clk *dfll = tegra_clk_cpu_cmplx.parent->u.cpu.dynamic;
+       unsigned long old_rate, new_rate, flags;
+
+       if (!dfll || !tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail))
+               return -EPERM;
+
+       /* Clipping min to oscillator rate is pretty much arbitrary */
+       new_rate = max(*rate, tegra_clk_m.rate);
+
+       clk_lock_save(dfll, &flags);
+
+       old_rate = clk_get_rate_locked(dfll);
+       *rate = old_rate;
+       if (new_rate != old_rate)
+               ret = clk_set_rate_locked(dfll, new_rate);
+
+       clk_unlock_restore(dfll, &flags);
+       return ret;
+}
+
+int tegra11_cpu_lp_idle_rate_exchange(unsigned long *rate)
 {
+       int ret = 0;
        struct clk *backup = tegra_clk_cpu_cmplx.parent->u.cpu.backup;
-       unsigned long old_rate = clk_get_rate(backup);
+       unsigned long old_rate, flags;
        unsigned long new_rate = min(
                *rate, tegra_clk_cpu_cmplx.parent->u.cpu.backup_rate);
+
+       clk_lock_save(backup, &flags);
+
+       old_rate = clk_get_rate_locked(backup);
        *rate = old_rate;
        if (new_rate != old_rate)
-               return clk_set_rate(backup, new_rate);
-       return 0;
+               ret = clk_set_rate_locked(backup, new_rate);
+
+       clk_unlock_restore(backup, &flags);
+       return ret;
 }
 
 void tegra_edp_throttle_cpu_now(u8 factor)
@@ -6972,9 +7112,11 @@ bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
         * source for EMC only when pll_m is fixed, or as a general fixed rate
         * clock source for EMC and other peripherals if pll_m is scaled. In
         * configuration with single cbus pll_c can be used as a scaled cbus
-        * clock source only.
+        * clock source only. No direct use for pll_c by super clocks.
         */
        if ((p == &tegra_pll_c) && (c != &tegra_pll_c_out1)) {
+               if (c->ops == &tegra_super_ops)
+                       return false;
 #ifdef CONFIG_TEGRA_DUAL_CBUS
 #ifndef CONFIG_TEGRA_PLLM_SCALED
                return c->flags & PERIPH_EMC_ENB;
@@ -6988,9 +7130,12 @@ bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
         * In any configuration pll_m must not be used as a clock source for
         * cbus modules. If pll_m is scaled it can be used as EMC source only.
         * Otherwise fixed rate pll_m can be used as clock source for EMC and
-        * other peripherals.
+        * other peripherals. No direct use for pll_m by super clocks.
         */
        if ((p == &tegra_pll_m) && (c != &tegra_pll_m_out1)) {
+               if (c->ops == &tegra_super_ops)
+                       return false;
+
                if (c->flags & PERIPH_ON_CBUS)
                        return false;
 #ifdef CONFIG_TEGRA_PLLM_SCALED
@@ -7533,18 +7678,6 @@ void __init tegra11x_init_clocks(void)
        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
                tegra11_init_one_clock(&tegra_list_clks[i]);
 
-       for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
-               c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
-               if (!c) {
-                       pr_err("%s: Unknown duplicate clock %s\n", __func__,
-                               tegra_clk_duplicates[i].name);
-                       continue;
-               }
-
-               tegra_clk_duplicates[i].lookup.clk = c;
-               clkdev_add(&tegra_clk_duplicates[i].lookup);
-       }
-
        for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
                tegra11_init_one_clock(&tegra_sync_source_list[i]);
        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
@@ -7562,6 +7695,18 @@ void __init tegra11x_init_clocks(void)
        for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
                tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]);
 
+       for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+               c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+               if (!c) {
+                       pr_err("%s: Unknown duplicate clock %s\n", __func__,
+                               tegra_clk_duplicates[i].name);
+                       continue;
+               }
+
+               tegra_clk_duplicates[i].lookup.clk = c;
+               clkdev_add(&tegra_clk_duplicates[i].lookup);
+       }
+
        /* Initialize to default */
        tegra_init_cpu_edp_limits(0);