/*
* arch/arm/mach-tegra/tegra11_clocks.c
*
- * Copyright (C) 2011-2012 NVIDIA Corporation
+ * Copyright (C) 2011-2013 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
+#include <linux/syscore_ops.h>
+#include <linux/platform_device.h>
+#include <linux/clk/tegra.h>
#include <asm/clkdev.h>
-#include <mach/iomap.h>
#include <mach/edp.h>
#include <mach/hardware.h>
+#include <mach/mc.h>
#include "clock.h"
#include "fuse.h"
+#include "iomap.h"
#include "dvfs.h"
#include "pm.h"
#include "sleep.h"
+#include "devices.h"
#include "tegra11_emc.h"
#include "tegra_cl_dvfs.h"
#define CLK_OUT_ENB_CLR_X 0x288
#define CLK_OUT_ENB_NUM 6
-#define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)
+#define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1) /* Reserved on Tegra11 */
#define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
#define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
#define PERIPH_CLK_SOURCE_NUM3 \
((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
-#define PERIPH_CLK_SOURCE_XUSB 0x4cc
-#define PERIPH_CLK_SOURCE_DDS_UART 0x4f8
+#define SPARE_REG 0x55c
+#define PERIPH_CLK_SOURCE_XUSB_HOST 0x600
+#define PERIPH_CLK_SOURCE_SOC_THERM 0x644
#define PERIPH_CLK_SOURCE_NUM4 \
- ((PERIPH_CLK_SOURCE_XUSB - PERIPH_CLK_SOURCE_DDS_UART) / 4 + 1)
+ ((PERIPH_CLK_SOURCE_SOC_THERM - PERIPH_CLK_SOURCE_XUSB_HOST) / 4 + 1)
#define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
PERIPH_CLK_SOURCE_NUM2 + \
PERIPH_CLK_SOURCE_NUM4)
#define CPU_SOFTRST_CTRL 0x380
+#define CPU_SOFTRST_CTRL1 0x384
+#define CPU_SOFTRST_CTRL2 0x388
#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
#define PLL_FIXED_MDIV(c, ref) ((ref) > (c)->u.pll.cf_max ? 2 : 1)
/* PLLU */
+#define PLLU_BASE_OVERRIDE (1<<24)
#define PLLU_BASE_POST_DIV (1<<20)
/* PLLD */
#define PLLD_MISC_DIV_RST (1<<23)
#define PLLD_MISC_DCCON_SHIFT 12
-#define PLLDU_LFCON_SET_DIVN 600
+#define PLLDU_LFCON 2
/* PLLC2 and PLLC3 (PLLCX) */
#define PLLCX_USE_DYN_RAMP 0
#define PLLCX_MISC_KOEF_LOW_RANGE \
((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
-#define PLLCX_MISC_KOEF_HIGH_RANGE \
- ((0x10 << PLLCX_MISC_KA_SHIFT) | (0xA0 << PLLCX_MISC_KB_SHIFT))
+
+#define PLLCX_MISC_DIV_LOW_RANGE \
+ ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
+#define PLLCX_MISC_DIV_HIGH_RANGE \
+ ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
#define PLLCX_MISC_DEFAULT_VALUE ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \
PLLCX_MISC_KOEF_LOW_RANGE | \
(0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
- (0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
- (0x2 << PLLCX_MISC_FILT_DIV_SHIFT) | \
+ PLLCX_MISC_DIV_LOW_RANGE | \
PLLCX_MISC_RESET)
-#define PLLCX_MISC1_DEFAULT_VALUE 0x00132308
-#define PLLCX_MISC2_DEFAULT_VALUE 0x11111100
-#define PLLCX_MISC3_DEFAULT_VALUE 0x0
+#define PLLCX_MISC1_DEFAULT_VALUE 0x000d2308
+#define PLLCX_MISC2_DEFAULT_VALUE 0x30211200
+#define PLLCX_MISC3_DEFAULT_VALUE 0x200
/* PLLX and PLLC (PLLXC)*/
#define PLLXC_USE_DYN_RAMP 0
#define PLLRE_MISC_LOCK (0x1 << 24)
#define PLLRE_MISC_IDDQ (0x1 << 16)
-/* FIXME: OUT_OF_TABLE_CPCON per pll */
#define OUT_OF_TABLE_CPCON 0x8
#define SUPER_CLK_MUX 0x00
#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP (1 << 1)
#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP (1 << 3)
#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP (1 << 5)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN (1 << 24)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP (1 << 25)
#define UTMIP_PLL_CFG1 0x484
#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15)
#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
+#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17)
#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
-#define PLLE_BASE_CML_ENABLE (1<<31)
-#define PLLE_BASE_ENABLE (1<<30)
+/* PLLE */
+#define PLLE_BASE_LOCK_OVERRIDE (0x1 << 29)
#define PLLE_BASE_DIVCML_SHIFT 24
#define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
-#define PLLE_BASE_DIVP_SHIFT 16
-#define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT)
-#define PLLE_BASE_DIVN_SHIFT 8
-#define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT)
-#define PLLE_BASE_DIVM_SHIFT 0
-#define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT)
-#define PLLE_BASE_DIV_MASK \
- (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \
- PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)
-#define PLLE_BASE_DIV(m, n, p, cml) \
- (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \
- ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))
-
-#define PLLE_MISC_SETUP_BASE_SHIFT 16
-#define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)
+#define PLLE_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
+#define PLLE_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT)
+
+/* PLLE has 4-bit CMLDIV, but entry 15 is not allowed in h/w */
+#define PLLE_CMLDIV_MAX 14
+
#define PLLE_MISC_READY (1<<15)
+#define PLLE_MISC_IDDQ_SW_CTRL (1<<14)
+#define PLLE_MISC_IDDQ_SW_VALUE (1<<13)
#define PLLE_MISC_LOCK (1<<11)
#define PLLE_MISC_LOCK_ENABLE (1<<9)
-#define PLLE_MISC_SETUP_EX_SHIFT 2
-#define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT)
-#define PLLE_MISC_SETUP_MASK \
- (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)
-#define PLLE_MISC_SETUP_VALUE \
- ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))
+#define PLLE_MISC_PLLE_PTS (1<<8)
+#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
+#define PLLE_MISC_VREG_BG_CTRL_MASK (0x3<<PLLE_MISC_VREG_BG_CTRL_SHIFT)
+#define PLLE_MISC_VREG_CTRL_SHIFT 2
+#define PLLE_MISC_VREG_CTRL_MASK (0x3<<PLLE_MISC_VREG_CTRL_SHIFT)
#define PLLE_SS_CTRL 0x68
#define PLLE_SS_INCINTRV_SHIFT 24
#define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
#define PLLE_SS_INC_SHIFT 16
#define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
+#define PLLE_SS_CNTL_SSC_BYP (0x1 << 12)
+#define PLLE_SS_CNTL_INTERP_RESET (0x1 << 11)
+#define PLLE_SS_CNTL_BYPASS_SS (0x1 << 10)
#define PLLE_SS_MAX_SHIFT 0
#define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
#define PLLE_SS_COEFFICIENTS_MASK \
(PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
-#define PLLE_SS_COEFFICIENTS_12MHZ \
- ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
- (0x24<<PLLE_SS_MAX_SHIFT))
-#define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10))
+#define PLLE_SS_COEFFICIENTS_VAL \
+ ((0x20<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
+ (0x25<<PLLE_SS_MAX_SHIFT))
+#define PLLE_SS_DISABLE (PLLE_SS_CNTL_SSC_BYP |\
+ PLLE_SS_CNTL_INTERP_RESET | PLLE_SS_CNTL_BYPASS_SS)
#define PLLE_AUX 0x48c
+#define PLLE_AUX_PLLRE_SEL (1<<28)
+#define PLLE_AUX_SEQ_STATE_SHIFT 26
+#define PLLE_AUX_SEQ_STATE_MASK (0x3<<PLLE_AUX_SEQ_STATE_SHIFT)
+#define PLLE_AUX_SEQ_START_STATE (1<<25)
+#define PLLE_AUX_SEQ_ENABLE (1<<24)
+#define PLLE_AUX_SS_SWCTL (1<<6)
+#define PLLE_AUX_ENABLE_SWCTL (1<<4)
+#define PLLE_AUX_USE_LOCKDET (1<<3)
#define PLLE_AUX_PLLP_SEL (1<<2)
-#define PLLE_AUX_CML_SATA_ENABLE (1<<1)
-#define PLLE_AUX_CML_PCIE_ENABLE (1<<0)
-#define PMC_SATA_PWRGT 0x1ac
-#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5)
-#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4)
+/* USB PLLs PD HW controls */
+#define XUSBIO_PLL_CFG0 0x51c
+#define XUSBIO_PLL_CFG0_SEQ_START_STATE (1<<25)
+#define XUSBIO_PLL_CFG0_SEQ_ENABLE (1<<24)
+#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1<<6)
+#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1<<2)
+#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1<<0)
+
+/* XUSB PLL PAD controls */
+#define XUSB_PADCTL_IOPHY_PLL0_CTL1 0x30
+#define XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD (1<<3)
+#define XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ (1<<0)
+
+#define UTMIPLL_HW_PWRDN_CFG0 0x52c
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
+#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1<<5)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1<<4)
+#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
+#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1<<1)
+#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1<<0)
+
+#define PLLU_HW_PWRDN_CFG0 0x530
+#define PLLU_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
+#define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
+#define PLLU_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
+#define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
+#define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL (1<<0)
+
+#define USB_PLLS_SEQ_START_STATE (1<<25)
+#define USB_PLLS_SEQ_ENABLE (1<<24)
+#define USB_PLLS_USE_LOCKDET (1<<6)
+#define USB_PLLS_ENABLE_SWCTL ((1<<2) | (1<<0))
+
+/* CPU clock trimmers */
+#define CPU_FINETRIM_BYP 0x4d0
+#define CPU_FINETRIM_SELECT 0x4d4
+#define CPU_FINETRIM_DR 0x4d8
+#define CPU_FINETRIM_DF 0x4dc
+#define CPU_FINETRIM_F 0x4e0
+#define CPU_FINETRIM_R 0x4e4
+
+/* DFLL */
+#define DFLL_BASE 0x2f4
+#define DFLL_BASE_RESET (1<<0)
+
+#define LVL2_CLK_GATE_OVRE 0x554
#define ROUND_DIVIDER_UP 0
#define ROUND_DIVIDER_DOWN 1
+#define DIVIDER_1_5_ALLOWED 0
+
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
+#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
+#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
+
+#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
+#define CPU_RESET(cpu) (0x111001ul << (cpu))
/* PLLP default fixed rate in h/w controlled mode */
#define PLLP_DEFAULT_FIXED_RATE 216000000
+/* Use PLL_RE as PLLE input (default - OSC via pll reference divider) */
+#define USE_PLLE_INPUT_PLLRE 0
+
static bool tegra11_is_dyn_ramp(struct clk *c,
unsigned long rate, bool from_vco_min);
static void tegra11_pllp_init_dependencies(unsigned long pllp_rate);
-static int tegra11_clk_shared_bus_update(struct clk *bus);
+static unsigned long tegra11_clk_shared_bus_update(struct clk *bus,
+ struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap);
+static unsigned long tegra11_clk_cap_shared_bus(struct clk *bus,
+ unsigned long rate, unsigned long ceiling);
static bool detach_shared_bus;
module_param(detach_shared_bus, bool, 0644);
-static bool use_dfll;
-module_param(use_dfll, bool, 0644);
+static int use_dfll;
/**
* Structure defining the fields for USB UTMI clocks Parameters.
static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
+static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
+static void __iomem *reg_xusb_padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
-#define MISC_GP_HIDREV 0x804
+#define MISC_GP_HIDREV 0x804
+#define MISC_GP_TRANSACTOR_SCRATCH_0 0x864
+#define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE (0x1 << 1)
+#define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE (0x1 << 2)
+#define MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE (0x1 << 3)
/*
* Some peripheral clocks share an enable bit, so refcount the enable bits
static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
#define clk_writel(value, reg) \
- __raw_writel(value, (u32)reg_clk_base + (reg))
+ __raw_writel(value, reg_clk_base + (reg))
#define clk_readl(reg) \
- __raw_readl((u32)reg_clk_base + (reg))
+ __raw_readl(reg_clk_base + (reg))
#define pmc_writel(value, reg) \
- __raw_writel(value, (u32)reg_pmc_base + (reg))
+ __raw_writel(value, reg_pmc_base + (reg))
#define pmc_readl(reg) \
- __raw_readl((u32)reg_pmc_base + (reg))
+ __raw_readl(reg_pmc_base + (reg))
#define chipid_readl() \
- __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV)
+ __raw_readl(misc_gp_base + MISC_GP_HIDREV)
+#define xusb_padctl_writel(value, reg) \
+ __raw_writel(value, reg_xusb_padctl_base + (reg))
+#define xusb_padctl_readl(reg) \
+ __raw_readl(reg_xusb_padctl_base + (reg))
#define clk_writel_delay(value, reg) \
do { \
- __raw_writel((value), (u32)reg_clk_base + (reg)); \
+ __raw_writel((value), reg_clk_base + (reg)); \
udelay(2); \
} while (0)
if (divider_ux1 - 2 > max_x)
return -EINVAL;
+#if !DIVIDER_1_5_ALLOWED
+ if (divider_ux1 == 3)
+ divider_ux1 = (round_mode == ROUND_DIVIDER_UP) ? 4 : 2;
+#endif
return divider_ux1 - 2;
}
return divider_u16 - 1;
}
+static inline bool bus_user_is_slower(struct clk *a, struct clk *b)
+{
+ return a->u.shared_bus_user.client->max_rate * a->div <
+ b->u.shared_bus_user.client->max_rate * b->div;
+}
+
+static inline bool bus_user_request_is_lower(struct clk *a, struct clk *b)
+{
+ return a->u.shared_bus_user.rate * a->div <
+ b->u.shared_bus_user.rate * b->div;
+}
+
/* clk_m functions */
static unsigned long tegra11_clk_m_autodetect_rate(struct clk *c)
{
shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
source = (val >> shift) & SUPER_SOURCE_MASK;
- if (c->flags & DIV_2)
- source |= val & SUPER_LP_DIV2_BYPASS;
+
+ /*
+ * Enforce PLLX DIV2 bypass setting as early as possible. It is always
+ * safe to do for both cclk_lp and cclk_g when booting on G CPU. (In
+ * case of booting on LP CPU, cclk_lp will be updated during the cpu
+ * rate change after boot, and cclk_g after the cluster switch.)
+ */
+ if ((c->flags & DIV_U71) && (!is_lp_cluster())) {
+ val |= SUPER_LP_DIV2_BYPASS;
+ clk_writel_delay(val, c->reg);
+ }
+
for (sel = c->inputs; sel->input != NULL; sel++) {
if (sel->value == source)
break;
BUG_ON(sel->input == NULL);
c->parent = sel->input;
+ /* Update parent in case when LP CPU PLLX DIV2 bypassed */
+ if ((c->flags & DIV_2) && (c->parent->flags & PLLX) &&
+ (val & SUPER_LP_DIV2_BYPASS))
+ c->parent = c->parent->parent;
+
if (c->flags & DIV_U71) {
c->mul = 2;
c->div = 2;
return clk_set_rate(c->parent, rate);
}
+#ifdef CONFIG_PM_SLEEP
+static void tegra11_super_clk_resume(struct clk *c, struct clk *backup,
+ u32 setting)
+{
+ u32 val;
+ const struct clk_mux_sel *sel;
+ int shift;
+
+ /* For sclk and cclk_g super clock just restore saved value */
+ if (!(c->flags & DIV_2)) {
+ clk_writel_delay(setting, c->reg);
+ return;
+ }
+
+ /*
+ * For cclk_lp supper clock: switch to backup (= not PLLX) source,
+ * safely restore PLLX DIV2 bypass, and only then restore full
+ * setting
+ */
+ val = clk_readl(c->reg);
+ BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+ ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+ shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+ SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+ for (sel = c->inputs; sel->input != NULL; sel++) {
+ if (sel->input == backup) {
+ val &= ~(SUPER_SOURCE_MASK << shift);
+ val |= (sel->value & SUPER_SOURCE_MASK) << shift;
+
+ BUG_ON(backup->flags & PLLX);
+ clk_writel_delay(val, c->reg);
+
+ val &= ~SUPER_LP_DIV2_BYPASS;
+ val |= (setting & SUPER_LP_DIV2_BYPASS);
+ clk_writel_delay(val, c->reg);
+ clk_writel_delay(setting, c->reg);
+ return;
+ }
+ }
+ BUG();
+}
+#endif
+
static struct clk_ops tegra_super_ops = {
.init = tegra11_super_clk_init,
.enable = tegra11_super_clk_enable,
if (dramp)
goto out;
} else if (old_rate > vco_min) {
+#if PLLXC_USE_DYN_RAMP
pr_warn("No dynamic ramp down: %s: %lu to %lu\n",
c->u.cpu.main->name, old_rate, vco_min);
+#endif
}
}
if (rate > vco_min) {
if (tegra11_is_dyn_ramp(c->u.cpu.main, rate, true))
main_rate = vco_min;
+#if PLLXC_USE_DYN_RAMP
else
pr_warn("No dynamic ramp up: %s: %lu to %lu\n",
c->u.cpu.main->name, vco_min, rate);
+#endif
}
ret = clk_set_rate(c->u.cpu.main, main_rate);
{
int ret;
struct clk *dfll = c->u.cpu.dynamic;
+ unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
/* dfll rate request */
ret = clk_set_rate(dfll, rate);
/* 1st time - switch to dfll */
if (c->parent->parent != dfll) {
+ if (max(old_rate, rate) < dfll_rate_min) {
+ /* set interim cpu dvfs rate at dfll_rate_min to
+ prevent voltage drop below dfll Vmin */
+ ret = tegra_dvfs_set_rate(c, dfll_rate_min);
+ if (ret) {
+ pr_err("Failed to set cpu dvfs rate %lu\n",
+ dfll_rate_min);
+ return ret;
+ }
+ }
+
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
ret = clk_set_parent(c->parent, dfll);
if (ret) {
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
pr_err("Failed to switch cpu to %s\n", dfll->name);
return ret;
}
ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
- if (ret) {
- pr_err("Failed to lock %s\n", dfll->name);
- return ret;
- }
+ WARN(ret, "Failed to lock %s at rate %lu\n", dfll->name, rate);
+
/* prevent legacy dvfs voltage scaling */
- if (c->dvfs && c->dvfs->dvfs_rail)
- c->dvfs->dvfs_rail->auto_control = true;
+ tegra_dvfs_dfll_mode_set(c->dvfs, rate);
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
}
return 0;
}
unsigned long old_rate)
{
int ret;
+ struct clk *pll;
struct clk *dfll = c->u.cpu.dynamic;
- struct clk *pll = (old_rate <= c->u.cpu.backup_rate) ?
- c->u.cpu.backup : c->u.cpu.main;
+ unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
+
+ rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost);
+ pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main;
+ dfll_rate_min = max(rate, dfll_rate_min);
+
+ /* set target rate last time in dfll mode */
+ if (old_rate != dfll_rate_min) {
+ ret = tegra_dvfs_set_rate(c, dfll_rate_min);
+ if (!ret)
+ ret = clk_set_rate(dfll, dfll_rate_min);
+
+ if (ret) {
+ pr_err("Failed to set cpu rate %lu on source %s\n",
+ dfll_rate_min, dfll->name);
+ return ret;
+ }
+ }
+ /* unlock dfll - release volatge rail control */
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
if (ret) {
pr_err("Failed to unlock %s\n", dfll->name);
- return ret;
+ goto back_to_dfll;
}
/* restore legacy dvfs operations and set appropriate voltage */
- if (c->dvfs && c->dvfs->dvfs_rail)
- c->dvfs->dvfs_rail->auto_control = false;
-
- rate = max(rate, old_rate);
- ret = tegra_dvfs_set_rate(c, rate);
+ ret = tegra_dvfs_dfll_mode_clear(c->dvfs, dfll_rate_min);
if (ret) {
pr_err("Failed to set cpu rail for rate %lu\n", rate);
- return ret;
+ goto back_to_dfll;
}
- /* set pll rate same as dfll old rate, and return to pll source */
- ret = clk_set_rate(pll, old_rate);
+ /* set pll to target rate and return to pll source */
+ ret = clk_set_rate(pll, rate);
if (ret) {
pr_err("Failed to set cpu rate %lu on source"
- " %s\n", old_rate, pll->name);
- return ret;
+ " %s\n", rate, pll->name);
+ goto back_to_dfll;
}
ret = clk_set_parent(c->parent, pll);
if (ret) {
pr_err("Failed to switch cpu to %s\n", pll->name);
- return ret;
+ goto back_to_dfll;
}
+
+ /* If going up, adjust voltage here (down path is taken care of by the
+ framework after set rate exit) */
+ if (old_rate <= rate)
+ tegra_dvfs_set_rate(c, rate);
+
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
return 0;
+
+back_to_dfll:
+ tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+ tegra_dvfs_dfll_mode_set(c->dvfs, old_rate);
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
+ return ret;
}
static int tegra11_cpu_clk_set_rate(struct clk *c, unsigned long rate)
if (c->dvfs) {
if (!c->dvfs->dvfs_rail)
return -ENOSYS;
- else if ((!c->dvfs->dvfs_rail->reg) && (old_rate != rate)) {
- WARN(1, "Changing CPU rate while regulator is not"
+ else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate) &&
+ (c->boot_rate < rate)) {
+ WARN(1, "Increasing CPU rate while regulator is not"
" ready is not allowed\n");
return -ENOSYS;
}
}
#endif
- if (has_dfll) {
- if (use_dfll)
+ if (has_dfll && c->dvfs && c->dvfs->dvfs_rail) {
+ if (tegra_dvfs_is_dfll_range(c->dvfs, rate))
return tegra11_cpu_clk_dfll_on(c, rate, old_rate);
- else if (is_dfll) {
- int ret = tegra11_cpu_clk_dfll_off(c, rate, old_rate);
- if (ret)
- return ret;
- }
+ else if (is_dfll)
+ return tegra11_cpu_clk_dfll_off(c, rate, old_rate);
}
return tegra11_cpu_clk_set_plls(c, rate, old_rate);
}
+static long tegra11_cpu_clk_round_rate(struct clk *c, unsigned long rate)
+{
+ unsigned long max_rate = c->max_rate;
+
+ /* Remove dfll boost to maximum rate when running on PLL */
+ if (c->dvfs && !tegra_dvfs_is_dfll_scale(c->dvfs, rate))
+ max_rate -= c->dvfs->dfll_data.max_rate_boost;
+
+ if (rate > max_rate)
+ rate = max_rate;
+ else if (rate < c->min_rate)
+ rate = c->min_rate;
+ return rate;
+}
+
static struct clk_ops tegra_cpu_ops = {
.init = tegra11_cpu_clk_init,
.enable = tegra11_cpu_clk_enable,
.disable = tegra11_cpu_clk_disable,
.set_rate = tegra11_cpu_clk_set_rate,
+ .round_rate = tegra11_cpu_clk_round_rate,
};
const struct clk_mux_sel *sel;
unsigned long rate = clk_get_rate(c->parent);
struct clk *dfll = c->parent->u.cpu.dynamic ? : p->u.cpu.dynamic;
+ struct clk *p_source_old = NULL;
struct clk *p_source;
pr_debug("%s: %s %s\n", __func__, c->name, p->name);
spin_unlock(¶meters_lock);
if (flags) {
- /* over-clocking after the switch - allow, but lower rate */
- if (rate > p->max_rate) {
- rate = p->max_rate;
+ /* over/under-clocking after switch - allow, but update rate */
+ if ((rate > p->max_rate) || (rate < p->min_rate)) {
+ rate = rate > p->max_rate ? p->max_rate : p->min_rate;
ret = clk_set_rate(c->parent, rate);
if (ret) {
pr_err("%s: Failed to set rate %lu for %s\n",
} else
#endif
{
- if (p == c->parent) /* already switched - exit*/
- return 0;
-
if (rate > p->max_rate) { /* over-clocking - no switch */
pr_warn("%s: No %s mode switch to %s at rate %lu\n",
__func__, c->name, p->name, rate);
flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP :
TEGRA_POWER_CLUSTER_G;
+ if (p == c->parent) {
+ if (flags & TEGRA_POWER_CLUSTER_FORCE) {
+ /* Allow parameterized switch to the same mode */
+ ret = tegra_cluster_control(delay, flags);
+ if (ret)
+ pr_err("%s: Failed to force %s mode to %s\n",
+ __func__, c->name, p->name);
+ return ret;
+ }
+ return 0; /* already switched - exit */
+ }
+
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
if (c->parent->parent->parent == dfll) {
/* G (DFLL selected as clock source) => LP switch:
* turn DFLL into open loop mode ("release" VDD_CPU rail)
*/
ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
if (ret)
- return ret;
+ goto abort;
+
+ ret = tegra_dvfs_rail_dfll_mode_set_cold(tegra_cpu_rail);
+ if (ret)
+ goto abort;
p_source = rate <= p->u.cpu.backup_rate ?
p->u.cpu.backup : p->u.cpu.main;
ret = clk_set_rate(p_source, rate);
if (ret)
- return ret;
- } else if (p->parent->parent == dfll) {
+ goto abort;
+ } else if ((p->parent->parent == dfll) || ((p->u.cpu.dynamic == dfll) &&
+ (dfll->state != UNINITIALIZED) && use_dfll)) {
/* LP => G (DFLL selected as clock source) switch:
* set DFLL rate ready (DFLL is still disabled)
* (set target p_source as dfll, G source is already selected)
*/
p_source = dfll;
- ret = clk_set_rate(p_source, rate);
+ ret = clk_set_rate(dfll,
+ tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail) ? rate :
+ max(rate, p->dvfs->dfll_data.use_dfll_rate_min));
if (ret)
- return ret;
+ goto abort;
} else
- /* DFLL is not selcted on either side of the switch:
+ /* DFLL is not selected on either side of the switch:
* set target p_source equal to current clock source
*/
p_source = c->parent->parent->parent;
/* Switch new parent to target clock source if necessary */
if (p->parent->parent != p_source) {
+ clk_enable(p->parent->parent);
+ clk_enable(p->parent);
+ p_source_old = p->parent->parent;
ret = clk_set_parent(p->parent, p_source);
if (ret) {
pr_err("%s: Failed to set parent %s for %s\n",
__func__, p_source->name, p->name);
- return ret;
+ goto abort;
}
}
clk_disable(p);
pr_err("%s: Failed to switch %s mode to %s\n",
__func__, c->name, p->name);
- return ret;
+ goto abort;
}
/* Disabling old parent scales old mode voltage rail */
- if (c->refcnt && c->parent)
+ if (c->refcnt)
clk_disable(c->parent);
+ if (p_source_old) {
+ clk_disable(p->parent);
+ clk_disable(p_source_old);
+ }
clk_reparent(c, p);
- /* Lock DFLL now (resume closed loop VDD_CPU control) */
- if (p_source == dfll)
- tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+ /*
+ * Lock DFLL now (resume closed loop VDD_CPU control).
+ * G CPU operations are always resumed on DFLL if it can be used, even
+ * when autoswitch between PLL and DFLL is allowed, and resume rate is
+ * low enough to run on PLL. This makes CPU clock source ready for
+ * speedy ramp with cl_dvfs controlling volatge (and that ramp is the
+ * most likely reason for going to G CPU in the 1st place)
+ */
+ if (p_source == dfll) {
+ if (tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail)) {
+ tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+ } else {
+ clk_set_rate(dfll, rate);
+ tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+ tegra_dvfs_dfll_mode_set(p->dvfs, rate);
+ }
+ }
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
return 0;
+
+abort:
+ /* Re-lock DFLL if necessary after aborted switch */
+ if (c->parent->parent->parent == dfll) {
+ clk_set_rate(dfll, rate);
+ tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+ }
+ if (p_source_old) {
+ clk_disable(p->parent);
+ clk_disable(p_source_old);
+ }
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
+
+ pr_err("%s: aborted switch from %s to %s\n",
+ __func__, c->parent->name, p->name);
+ return ret;
}
static long tegra11_cpu_cmplx_round_rate(struct clk *c,
unsigned long rate)
{
- if (rate > c->parent->max_rate)
- rate = c->parent->max_rate;
- else if (rate < c->parent->min_rate)
- rate = c->parent->min_rate;
- return rate;
+ return clk_round_rate(c->parent, rate);
}
static struct clk_ops tegra_cpu_cmplx_ops = {
/* This special sbus round function is implemented because:
*
- * (a) fractional dividers can not be used to derive system bus clock with one
- * exception: 1 : 2.5 divider is allowed at 1.2V and above (and we do need this
- * divider to reach top sbus frequencies from high frequency source).
+ * (a) sbus complex clock source is selected automatically based on rate
*
* (b) since sbus is a shared bus, and its frequency is set to the highest
* enabled shared_bus_user clock, the target rate should be rounded up divider
* recursive calls. Lost 1Hz is added in tegra11_sbus_cmplx_set_rate before
* actually setting divider rate.
*/
-static unsigned long sclk_high_2_5_rate;
-static bool sclk_high_2_5_valid;
-
-static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
+static long tegra11_sbus_cmplx_round_updown(struct clk *c, unsigned long rate,
+ bool up)
{
- int i, divider;
+ int divider;
unsigned long source_rate, round_rate;
struct clk *new_parent;
rate = max(rate, c->min_rate);
- if (!sclk_high_2_5_rate) {
- source_rate = clk_get_rate(c->u.system.sclk_high->parent);
- sclk_high_2_5_rate = 2 * source_rate / 5;
- i = tegra_dvfs_predict_millivolts(c, sclk_high_2_5_rate);
- if (!IS_ERR_VALUE(i) && (i >= 1200) &&
- (sclk_high_2_5_rate <= c->max_rate))
- sclk_high_2_5_valid = true;
- }
-
new_parent = (rate <= c->u.system.threshold) ?
c->u.system.sclk_low : c->u.system.sclk_high;
source_rate = clk_get_rate(new_parent->parent);
divider = clk_div71_get_divider(source_rate, rate,
- new_parent->flags | DIV_U71_INT, ROUND_DIVIDER_DOWN);
+ new_parent->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
if (divider < 0)
- return divider;
+ return c->min_rate;
+
+ if (divider == 1)
+ divider = 0;
round_rate = source_rate * 2 / (divider + 2);
if (round_rate > c->max_rate) {
- divider += 2;
+ divider += new_parent->flags & DIV_U71_INT ? 2 : 1;
+#if !DIVIDER_1_5_ALLOWED
+ divider = max(2, divider);
+#endif
round_rate = source_rate * 2 / (divider + 2);
}
if (new_parent == c->u.system.sclk_high) {
- /* Check if 1 : 2.5 ratio provides better approximation */
- if (sclk_high_2_5_valid) {
- if (((sclk_high_2_5_rate < round_rate) &&
- (sclk_high_2_5_rate >= rate)) ||
- ((round_rate < sclk_high_2_5_rate) &&
- (round_rate < rate)))
- round_rate = sclk_high_2_5_rate;
- }
-
+ /* Prevent oscillation across threshold */
if (round_rate <= c->u.system.threshold)
round_rate = c->u.system.threshold;
}
return round_rate;
}
+static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
+{
+ return tegra11_sbus_cmplx_round_updown(c, rate, true);
+}
+
static int tegra11_sbus_cmplx_set_rate(struct clk *c, unsigned long rate)
{
int ret;
return 0;
}
+static int tegra11_clk_sbus_update(struct clk *bus)
+{
+ unsigned long rate, old_rate;
+
+ if (detach_shared_bus)
+ return 0;
+
+ rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL);
+
+ old_rate = clk_get_rate_locked(bus);
+ if (rate == old_rate)
+ return 0;
+
+ return clk_set_rate_locked(bus, rate);
+}
+
static struct clk_ops tegra_sbus_cmplx_ops = {
.init = tegra11_sbus_cmplx_init,
.set_rate = tegra11_sbus_cmplx_set_rate,
.round_rate = tegra11_sbus_cmplx_round_rate,
- .shared_bus_update = tegra11_clk_shared_bus_update,
+ .round_rate_updown = tegra11_sbus_cmplx_round_updown,
+ .shared_bus_update = tegra11_clk_sbus_update,
};
/* Blink output functions */
#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
#if USE_PLL_LOCK_BITS
int i;
+ u32 val = 0;
+
for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) {
udelay(PLL_PRE_LOCK_DELAY);
- if ((clk_readl(lock_reg) & lock_bits) == lock_bits) {
+ val = clk_readl(lock_reg);
+ if ((val & lock_bits) == lock_bits) {
udelay(PLL_POST_LOCK_DELAY);
return 0;
}
}
- pr_err("Timed out waiting for lock bit on pll %s\n", c->name);
- return -1;
+
+ /* PLLCX lock bits may fluctuate after the lock - don't report timeout
+ in this case (phase lock bit happens to uniquely identify PLLCX) */
+ if (lock_bits & PLLCX_BASE_PHASE_LOCK) {
+ pr_debug("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+ c->name, lock_reg, val);
+ return 0;
+ } else {
+ pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+ c->name, lock_reg, val);
+ return -ETIMEDOUT;
+ }
#endif
udelay(c->u.pll.lock_delay);
#endif
return 0;
}
+static void usb_plls_hw_control_enable(u32 reg)
+{
+ u32 val = clk_readl(reg);
+ val |= USB_PLLS_USE_LOCKDET | USB_PLLS_SEQ_START_STATE;
+ val &= ~USB_PLLS_ENABLE_SWCTL;
+ val |= USB_PLLS_SEQ_START_STATE;
+ pll_writel_delay(val, reg);
+
+ val |= USB_PLLS_SEQ_ENABLE;
+ pll_writel_delay(val, reg);
+}
static void tegra11_utmi_param_configure(struct clk *c)
{
utmi_parameters[i].active_delay_count);
/* Remove power downs from UTMIP PLL control bits */
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP;
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
+ reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
clk_writel(reg, UTMIP_PLL_CFG2);
/* Remove power downs from UTMIP PLL control bits */
reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
+ reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
+ clk_writel(reg, UTMIP_PLL_CFG1);
+
+ /* Setup HW control of UTMIPLL */
+ reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
+ reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
+ reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
+ reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
+ clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
+ reg = clk_readl(UTMIP_PLL_CFG1);
+ reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
+ reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
clk_writel(reg, UTMIP_PLL_CFG1);
+
+ udelay(1);
+
+ /* Setup SW override of UTMIPLL assuming USB2.0
+ ports are assigned to USB2 */
+ reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
+ reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
+ reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
+ clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
+
+ udelay(1);
+
+ /* Enable HW control UTMIPLL */
+ reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
+ reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
+ clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
}
static void tegra11_pll_clk_init(struct clk *c)
}
if (c->flags & PLLU) {
+ /* Configure UTMI PLL power management */
tegra11_utmi_param_configure(c);
+
+ /* Put PLLU under h/w control */
+ usb_plls_hw_control_enable(PLLU_HW_PWRDN_CFG0);
+
+ val = clk_readl(c->reg + PLL_BASE);
+ val &= ~PLLU_BASE_OVERRIDE;
+ clk_writel(val, c->reg + PLL_BASE);
+
+ /* Set XUSB PLL pad pwr override and iddq */
+ val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL0_CTL1);
+ val |= XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD;
+ val |= XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ;
+ xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL0_CTL1);
}
}
pr_debug("%s on clock %s\n", __func__, c->name);
#if USE_PLL_LOCK_BITS
+ /* toggle lock enable bit to reset lock detection circuit (couple
+ register reads provide enough duration for reset pulse) */
+ val = clk_readl(c->reg + PLL_MISC(c));
+ val &= ~PLL_MISC_LOCK_ENABLE(c);
+ clk_writel(val, c->reg + PLL_MISC(c));
+ val = clk_readl(c->reg + PLL_MISC(c));
val = clk_readl(c->reg + PLL_MISC(c));
val |= PLL_MISC_LOCK_ENABLE(c);
clk_writel(val, c->reg + PLL_MISC(c));
clk_writel(val, c->reg);
}
+static u8 get_pll_cpcon(struct clk *c, u16 n)
+{
+ if (c->flags & PLLD) {
+ if (n >= 600)
+ return 12;
+ else if (n >= 300)
+ return 8;
+ else if (n >= 50)
+ return 3;
+ else
+ return 2;
+ }
+ return c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
+}
+
static int tegra11_pll_clk_set_rate(struct clk *c, unsigned long rate)
{
u32 val, p_div, old_base;
/* Configure out-of-table rate */
if (sel->input_rate == 0) {
- unsigned long cfreq;
+ unsigned long cfreq, vco;
BUG_ON(c->flags & PLLU);
sel = &cfg;
BUG();
}
- /* Raise VCO to guarantee 0.5% accuracy */
- for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
- cfg.output_rate <<= 1, p_div++);
+ /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */
+ vco = max(200 * cfreq, c->u.pll.vco_min);
+ for (cfg.output_rate = rate; cfg.output_rate < vco; p_div++)
+ cfg.output_rate <<= 1;
cfg.p = 0x1 << p_div;
cfg.m = input_rate / cfreq;
cfg.n = cfg.output_rate / cfreq;
- cfg.cpcon = OUT_OF_TABLE_CPCON;
+ cfg.cpcon = get_pll_cpcon(c, cfg.n);
if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
(cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
if (c->flags & (PLLU | PLLD)) {
val &= ~PLL_MISC_LFCON_MASK;
- if (sel->n >= PLLDU_LFCON_SET_DIVN)
- val |= 0x1 << PLL_MISC_LFCON_SHIFT;
+ val |= PLLDU_LFCON << PLL_MISC_LFCON_SHIFT;
}
clk_writel(val, c->reg + PLL_MISC(c));
}
tegra11_pllp_init_dependencies(c->u.pll.fixed_rate);
}
+#ifdef CONFIG_PM_SLEEP
static void tegra11_pllp_clk_resume(struct clk *c)
{
unsigned long rate = c->u.pll.fixed_rate;
tegra11_pll_clk_init(c);
BUG_ON(rate != c->u.pll.fixed_rate);
}
+#endif
static struct clk_ops tegra_pllp_ops = {
.init = tegra11_pllp_clk_init,
if (sel->input_rate == input_rate && sel->output_rate == rate) {
u32 p = c->u.pll.round_p_to_pdiv(sel->p, pdiv);
BUG_ON(IS_ERR_VALUE(p));
- if (rate >= c->u.pll.vco_min)
- BUG_ON(sel->p != 1);
BUG_ON(sel->m != PLL_FIXED_MDIV(c, input_rate));
*cfg = *sel;
return 0;
}
-/* FIXME: pllcx suspend/resume */
-
static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */
/* p: */ 1, 2, 3, 4, 6, 8, 12, 16 };
if (p) {
for (i = 0; i <= PLLCX_PDIV_MAX; i++) {
+ /* Do not use DIV3 p values - mapped to even PDIV */
+ if (i && ((i & 0x1) == 0))
+ continue;
+
if (p <= pllcx_p[i]) {
if (pdiv)
*pdiv = i;
switch (input_rate) {
case 12000000:
- n_threshold = 77;
+ n_threshold = 70;
break;
case 13000000:
case 26000000:
}
val = clk_readl(c->reg + PLL_MISC(c));
- val &= ~(PLLCX_MISC_KA_MASK | PLLCX_MISC_KB_MASK);
+ val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
val |= n <= n_threshold ?
- PLLCX_MISC_KOEF_LOW_RANGE : PLLCX_MISC_KOEF_HIGH_RANGE;
+ PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
clk_writel(val, c->reg + PLL_MISC(c));
}
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+static void tegra11_pllcx_clk_resume_enable(struct clk *c)
+{
+ unsigned long rate = clk_get_rate_all_locked(c->parent);
+ u32 val = clk_readl(c->reg + PLL_BASE);
+ enum clk_state state = c->state;
+
+ if (val & PLL_BASE_ENABLE)
+ return; /* already resumed */
+
+ /* Restore input divider */
+ val &= ~PLLCX_BASE_DIVM_MASK;
+ val |= PLL_FIXED_MDIV(c, rate) << PLL_BASE_DIVM_SHIFT;
+ clk_writel(val, c->reg + PLL_BASE);
+
+ /* temporarily sync h/w and s/w states, final sync happens
+ in tegra_clk_resume later */
+ c->state = OFF;
+ pllcx_set_defaults(c, rate, c->mul);
+
+ rate = clk_get_rate_all_locked(c) + 1;
+ tegra11_pllcx_clk_set_rate(c, rate);
+ tegra11_pllcx_clk_enable(c);
+ c->state = state;
+}
+#endif
+
static struct clk_ops tegra_pllcx_ops = {
.init = tegra11_pllcx_clk_init,
.enable = tegra11_pllcx_clk_enable,
};
-/* FIXME: pllxc suspend/resume */
-
/* non-monotonic mapping below is not a typo */
static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+static void tegra11_pllxc_clk_resume_enable(struct clk *c)
+{
+ unsigned long rate = clk_get_rate_all_locked(c->parent);
+ enum clk_state state = c->state;
+
+ if (clk_readl(c->reg + PLL_BASE) & PLL_BASE_ENABLE)
+ return; /* already resumed */
+
+ /* temporarily sync h/w and s/w states, final sync happens
+ in tegra_clk_resume later */
+ c->state = OFF;
+ if (c->flags & PLLX)
+ pllx_set_defaults(c, rate);
+ else
+ pllc_set_defaults(c, rate);
+
+ rate = clk_get_rate_all_locked(c) + 1;
+ tegra11_pllxc_clk_set_rate(c, rate);
+ tegra11_pllxc_clk_enable(c);
+ c->state = state;
+}
+#endif
+
static struct clk_ops tegra_pllxc_ops = {
.init = tegra11_pllxc_clk_init,
.enable = tegra11_pllxc_clk_enable,
};
-/* FIXME: pllre suspend/resume */
/* non-monotonic mapping below is not a typo */
static u8 pllre_p[PLLRE_PDIV_MAX + 1] = {
/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
.set_rate = tegra11_pllre_out_clk_set_rate,
};
+#ifdef CONFIG_PM_SLEEP
+/* Resume both pllre_vco and pllre_out */
+static void tegra11_pllre_clk_resume_enable(struct clk *c)
+{
+ u32 pdiv;
+ u32 val = clk_readl(c->reg + PLL_BASE);
+ unsigned long rate = clk_get_rate_all_locked(c->parent->parent);
+ enum clk_state state = c->parent->state;
+
+ if (val & PLL_BASE_ENABLE)
+ return; /* already resumed */
+
+ /* temporarily sync h/w and s/w states, final sync happens
+ in tegra_clk_resume later */
+ c->parent->state = OFF;
+ pllre_set_defaults(c->parent, rate);
+
+ /* restore PLLRE VCO feedback loop (m, n) */
+ rate = clk_get_rate_all_locked(c->parent) + 1;
+ tegra11_pllre_clk_set_rate(c->parent, rate);
+
+ /* restore PLLRE post-divider */
+ c->parent->u.pll.round_p_to_pdiv(c->div, &pdiv);
+ val = clk_readl(c->reg);
+ val &= ~PLLRE_BASE_DIVP_MASK;
+ val |= pdiv << PLLRE_BASE_DIVP_SHIFT;
+ clk_writel(val, c->reg);
+
+ tegra11_pllre_clk_enable(c->parent);
+ c->parent->state = state;
+}
+#endif
+
+/* non-monotonic mapping below is not a typo */
+static u8 plle_p[PLLE_CMLDIV_MAX + 1] = {
+/* CMLDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
+/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
+
+static inline void select_pll_e_input(u32 aux_reg)
+{
+#if USE_PLLE_INPUT_PLLRE
+ aux_reg |= PLLE_AUX_PLLRE_SEL;
+#else
+ aux_reg &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
+#endif
+ clk_writel(aux_reg, PLLE_AUX);
+}
static void tegra11_plle_clk_init(struct clk *c)
{
- u32 val;
+ u32 val, p;
+ struct clk *pll_ref = tegra_get_clock_by_name("pll_ref");
+ struct clk *re_vco = tegra_get_clock_by_name("pll_re_vco");
+ struct clk *pllp = tegra_get_clock_by_name("pllp");
+#if USE_PLLE_INPUT_PLLRE
+ struct clk *ref = re_vco;
+#else
+ struct clk *ref = pll_ref;
+#endif
- val = clk_readl(PLLE_AUX);
- c->parent = (val & PLLE_AUX_PLLP_SEL) ?
- tegra_get_clock_by_name("pll_p") :
- tegra_get_clock_by_name("pll_ref");
val = clk_readl(c->reg + PLL_BASE);
- c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
- c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
- c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
- c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
+ c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+ c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+ c->div = (val & PLLE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+ p = (val & PLLE_BASE_DIVCML_MASK) >> PLLE_BASE_DIVCML_SHIFT;
+ c->div *= plle_p[p];
+
+ val = clk_readl(PLLE_AUX);
+ c->parent = (val & PLLE_AUX_PLLRE_SEL) ? re_vco :
+ (val & PLLE_AUX_PLLP_SEL) ? pllp : pll_ref;
+ if (c->parent != ref) {
+ if (c->state == ON) {
+ WARN(1, "%s: pll_e is left enabled with %s input\n",
+ __func__, c->parent->name);
+ } else {
+ c->parent = ref;
+ select_pll_e_input(val);
+ }
+ }
}
static void tegra11_plle_clk_disable(struct clk *c)
u32 val;
pr_debug("%s on clock %s\n", __func__, c->name);
+ /* FIXME: do we need to restore other s/w controls ? */
val = clk_readl(c->reg + PLL_BASE);
- val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
+ val &= ~PLL_BASE_ENABLE;
clk_writel(val, c->reg + PLL_BASE);
-}
-
-static void tegra11_plle_training(struct clk *c)
-{
- u32 val;
-
- /* PLLE is already disabled, and setup cleared;
- * create falling edge on PLLE IDDQ input */
- val = pmc_readl(PMC_SATA_PWRGT);
- val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
- pmc_writel(val, PMC_SATA_PWRGT);
- val = pmc_readl(PMC_SATA_PWRGT);
- val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
- pmc_writel(val, PMC_SATA_PWRGT);
-
- val = pmc_readl(PMC_SATA_PWRGT);
- val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
- pmc_writel(val, PMC_SATA_PWRGT);
-
- do {
- val = clk_readl(c->reg + PLL_MISC(c));
- } while (!(val & PLLE_MISC_READY));
+ val = clk_readl(c->reg + PLL_MISC(c));
+ val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
+ pll_writel_delay(val, c->reg + PLL_MISC(c));
}
-static int tegra11_plle_configure(struct clk *c, bool force_training)
+static int tegra11_plle_clk_enable(struct clk *c)
{
u32 val;
const struct clk_pll_freq_table *sel;
unsigned long rate = c->u.pll.fixed_rate;
unsigned long input_rate = clk_get_rate(c->parent);
- for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+ if (c->state == ON) {
+ /* BL left plle enabled - don't change configuartion */
+ pr_warn("%s: pll_e is already enabled\n", __func__);
+ return 0;
+ }
+
+ for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
if (sel->input_rate == input_rate && sel->output_rate == rate)
break;
}
- if (sel->input_rate == 0)
- return -ENOSYS;
-
- /* disable PLLE, clear setup fiels */
- tegra11_plle_clk_disable(c);
-
- val = clk_readl(c->reg + PLL_MISC(c));
- val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
- clk_writel(val, c->reg + PLL_MISC(c));
-
- /* training */
- val = clk_readl(c->reg + PLL_MISC(c));
- if (force_training || (!(val & PLLE_MISC_READY)))
- tegra11_plle_training(c);
+ if (sel->input_rate == 0) {
+ pr_err("%s: %s input rate %lu is out-of-table\n",
+ __func__, c->name, input_rate);
+ return -EINVAL;
+ }
- /* configure dividers, setup, disable SS */
+ /* setup locking configuration, s/w control of IDDQ and enable modes,
+ take pll out of IDDQ via s/w control, setup VREG */
val = clk_readl(c->reg + PLL_BASE);
- val &= ~PLLE_BASE_DIV_MASK;
- val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon);
+ val &= ~PLLE_BASE_LOCK_OVERRIDE;
clk_writel(val, c->reg + PLL_BASE);
- c->mul = sel->n;
- c->div = sel->m * sel->p;
val = clk_readl(c->reg + PLL_MISC(c));
- val |= PLLE_MISC_SETUP_VALUE;
val |= PLLE_MISC_LOCK_ENABLE;
+ val |= PLLE_MISC_IDDQ_SW_CTRL;
+ val &= ~PLLE_MISC_IDDQ_SW_VALUE;
+ val |= PLLE_MISC_PLLE_PTS;
+ val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
clk_writel(val, c->reg + PLL_MISC(c));
+ udelay(5);
+ /* configure dividers, disable SS */
val = clk_readl(PLLE_SS_CTRL);
val |= PLLE_SS_DISABLE;
clk_writel(val, PLLE_SS_CTRL);
- /* enable and lock PLLE*/
val = clk_readl(c->reg + PLL_BASE);
- val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
- clk_writel(val, c->reg + PLL_BASE);
-
- tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
+ val &= ~(PLLE_BASE_DIVM_MASK | PLLE_BASE_DIVN_MASK |
+ PLLE_BASE_DIVCML_MASK);
+ val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
+ (sel->n << PLL_BASE_DIVN_SHIFT) |
+ (sel->cpcon << PLLE_BASE_DIVCML_SHIFT);
+ pll_writel_delay(val, c->reg + PLL_BASE);
+ c->mul = sel->n;
+ c->div = sel->m * sel->p;
+ /* enable and lock pll */
+ val |= PLL_BASE_ENABLE;
+ clk_writel(val, c->reg + PLL_BASE);
+ tegra11_pll_clk_wait_for_lock(
+ c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
#if USE_PLLE_SS
- /* configure spread spectrum coefficients */
- /* FIXME: coefficients for 216MHZ input? */
-#ifdef CONFIG_TEGRA_SILICON_PLATFORM
- if (input_rate == 12000000)
+ val = clk_readl(PLLE_SS_CTRL);
+ val &= ~PLLE_SS_COEFFICIENTS_MASK;
+ val |= PLLE_SS_COEFFICIENTS_VAL;
+ clk_writel(val, PLLE_SS_CTRL);
+ val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
+ pll_writel_delay(val, PLLE_SS_CTRL);
+ val &= ~PLLE_SS_CNTL_INTERP_RESET;
+ pll_writel_delay(val, PLLE_SS_CTRL);
#endif
- {
- val = clk_readl(PLLE_SS_CTRL);
- val &= ~(PLLE_SS_COEFFICIENTS_MASK | PLLE_SS_DISABLE);
- val |= PLLE_SS_COEFFICIENTS_12MHZ;
- clk_writel(val, PLLE_SS_CTRL);
- }
+#if !USE_PLLE_SWCTL
+ /* switch pll under h/w control */
+ val = clk_readl(c->reg + PLL_MISC(c));
+ val &= ~PLLE_MISC_IDDQ_SW_CTRL;
+ clk_writel(val, c->reg + PLL_MISC(c));
+
+ val = clk_readl(PLLE_AUX);
+ val |= PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE;
+ val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
+ pll_writel_delay(val, PLLE_AUX);
+ val |= PLLE_AUX_SEQ_ENABLE;
+ pll_writel_delay(val, PLLE_AUX);
#endif
+ /* clear XUSB PLL pad pwr override and iddq */
+ val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL0_CTL1);
+ val &= ~XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD;
+ val &= ~XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ;
+ xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL0_CTL1);
+
+ /* enable hw control of xusb brick pll */
+ usb_plls_hw_control_enable(XUSBIO_PLL_CFG0);
+
return 0;
}
-static int tegra11_plle_clk_enable(struct clk *c)
+#ifdef CONFIG_PM_SLEEP
+static void tegra11_plle_clk_resume(struct clk *c)
{
- pr_debug("%s on clock %s\n", __func__, c->name);
- return tegra11_plle_configure(c, !c->set);
+ u32 val = clk_readl(c->reg + PLL_BASE);
+ if (val & PLL_BASE_ENABLE)
+ return; /* already resumed */
+
+ /* Restore parent */
+ val = clk_readl(PLLE_AUX);
+ select_pll_e_input(val);
}
+#endif
static struct clk_ops tegra_plle_ops = {
.init = tegra11_plle_clk_init,
.disable = tegra11_plle_clk_disable,
};
+/*
+ * Tegra11 includes dynamic frequency lock loop (DFLL) with automatic voltage
+ * control as possible CPU clock source. It is included in the Tegra11 clock
+ * tree as "complex PLL" with standard Tegra clock framework APIs. However,
+ * DFLL locking logic h/w access APIs are separated in the tegra_cl_dvfs.c
+ * module. Hence, DFLL operations, with the exception of initialization, are
+ * basically cl-dvfs wrappers.
+ */
+
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
/* DFLL operations */
+static void tune_cpu_trimmers(bool trim_high)
+{
+ if (trim_high) {
+ clk_writel(0, CPU_FINETRIM_SELECT);
+ clk_writel(0, CPU_FINETRIM_DR);
+ clk_writel(0, CPU_FINETRIM_R);
+ } else {
+ clk_writel(0x3F, CPU_FINETRIM_SELECT);
+ clk_writel(0x3F, CPU_FINETRIM_DR);
+ clk_writel(0xFFF, CPU_FINETRIM_R);
+ }
+ wmb();
+ clk_readl(CPU_FINETRIM_R);
+}
+
+static void __init tegra11_dfll_cpu_late_init(struct clk *c)
+{
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+ int ret;
+ struct clk *cpu = tegra_get_clock_by_name("cpu_g");
+
+ if (!cpu || !cpu->dvfs) {
+ pr_err("%s: CPU dvfs is not present\n", __func__);
+ return;
+ }
+ if (cpu->dvfs->speedo_id > 0) /* A01P and above parts */
+ tegra_dvfs_set_dfll_tune_trimmers(cpu->dvfs, tune_cpu_trimmers);
+
+#ifdef CONFIG_TEGRA_FPGA_PLATFORM
+ u32 netlist, patchid;
+ tegra_get_netlist_revision(&netlist, &patchid);
+ if (netlist < 12) {
+ pr_err("%s: CL-DVFS is not available on net %d\n",
+ __func__, netlist);
+ return;
+ }
+#endif
+ /* release dfll clock source reset, init cl_dvfs control logic, and
+ move dfll to initialized state, so it can be used as CPU source */
+ tegra_periph_reset_deassert(c);
+ ret = tegra_init_cl_dvfs();
+ if (!ret) {
+ c->state = OFF;
+ c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device);
+
+ use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
+ tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll);
+ pr_info("Tegra CPU DFLL is initialized\n");
+ }
+#endif
+}
+#endif
+
static int tegra11_dfll_clk_enable(struct clk *c)
{
return tegra_cl_dvfs_enable(c->u.dfll.cl_dvfs);
static void tegra11_dfll_clk_reset(struct clk *c, bool assert)
{
- u32 val = assert ? 1 : 0;
+ u32 val = assert ? DFLL_BASE_RESET : 0;
clk_writel_delay(val, c->reg);
}
return -EINVAL;
}
+#ifdef CONFIG_PM_SLEEP
+static void tegra11_dfll_clk_resume(struct clk *c)
+{
+ if (!(clk_readl(c->reg) & DFLL_BASE_RESET))
+ return; /* already resumed */
+
+ if (c->state != UNINITIALIZED) {
+ tegra_periph_reset_deassert(c);
+ tegra_cl_dvfs_resume(c->u.dfll.cl_dvfs);
+ }
+}
+#endif
+
static struct clk_ops tegra_dfll_ops = {
.enable = tegra11_dfll_clk_enable,
.disable = tegra11_dfll_clk_disable,
.clk_cfg_ex = tegra11_dfll_clk_cfg_ex,
};
+/* DFLL sysfs interface */
+static int tegra11_use_dfll_cb(const char *arg, const struct kernel_param *kp)
+{
+ int ret = 0;
+ unsigned long c_flags, p_flags;
+ unsigned int old_use_dfll;
+ struct clk *c = tegra_get_clock_by_name("cpu");
+
+ if (!c->parent || !c->parent->dvfs)
+ return -ENOSYS;
+
+ clk_lock_save(c, &c_flags);
+ if (c->parent->u.cpu.mode == MODE_LP) {
+ pr_err("%s: DFLL is not used on LP CPU\n", __func__);
+ clk_unlock_restore(c, &c_flags);
+ return -ENOSYS;
+ }
+
+ clk_lock_save(c->parent, &p_flags);
+ old_use_dfll = use_dfll;
+ param_set_int(arg, kp);
+
+ if (use_dfll != old_use_dfll) {
+ ret = tegra_dvfs_set_dfll_range(c->parent->dvfs, use_dfll);
+ if (ret) {
+ use_dfll = old_use_dfll;
+ } else {
+ ret = clk_set_rate_locked(c->parent,
+ clk_get_rate_locked(c->parent));
+ if (ret) {
+ use_dfll = old_use_dfll;
+ tegra_dvfs_set_dfll_range(
+ c->parent->dvfs, use_dfll);
+ }
+ }
+ }
+ clk_unlock_restore(c->parent, &p_flags);
+ clk_unlock_restore(c, &c_flags);
+ tegra_recalculate_cpu_edp_limits();
+ return ret;
+}
+
+static struct kernel_param_ops tegra11_use_dfll_ops = {
+ .set = tegra11_use_dfll_cb,
+ .get = param_get_int,
+};
+module_param_cb(use_dfll, &tegra11_use_dfll_ops, &use_dfll, 0644);
+
+
/* Clock divider ops (non-atomic shared register access) */
static DEFINE_SPINLOCK(pll_div_lock);
}
else
BUG();
+ } else if (c->flags & PLLU) {
+ u32 val = clk_readl(c->reg);
+ c->state = val & (0x1 << c->reg_shift) ? ON : OFF;
} else {
c->state = ON;
c->div = 1;
return 0;
} else if (c->flags & DIV_2) {
return 0;
+ } else if (c->flags & PLLU) {
+ clk_lock_save(c->parent, &flags);
+ val = clk_readl(c->reg) | (0x1 << c->reg_shift);
+ clk_writel_delay(val, c->reg);
+ clk_unlock_restore(c->parent, &flags);
+ return 0;
}
return -EINVAL;
}
val |= new_val << c->reg_shift;
clk_writel_delay(val, c->reg);
spin_unlock_irqrestore(&pll_div_lock, flags);
+ } else if (c->flags & PLLU) {
+ clk_lock_save(c->parent, &flags);
+ val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
+ clk_writel_delay(val, c->reg);
+ clk_unlock_restore(c->parent, &flags);
}
}
c->parent = mux->input;
} else {
+ if (c->flags & PLLU) {
+ /* for xusb_hs clock enforce PLLU source during init */
+ val &= ~periph_clk_source_mask(c);
+ val |= c->inputs[0].value << periph_clk_source_shift(c);
+ clk_writel_delay(val, c->reg);
+ }
c->parent = c->inputs[0].input;
}
c->mul = 1;
}
- c->state = ON;
-
- if (c->flags & PERIPH_NO_ENB)
+ if (c->flags & PERIPH_NO_ENB) {
+ c->state = c->parent->state;
return;
+ }
+
+ c->state = ON;
if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
c->state = OFF;
};
+#if !defined(CONFIG_TEGRA_SIMULATION_PLATFORM)
+/* msenc clock propagation WAR for bug 1005168 */
+static int tegra11_msenc_clk_enable(struct clk *c)
+{
+ int ret = tegra11_periph_clk_enable(c);
+ if (ret)
+ return ret;
+
+ clk_writel(0, LVL2_CLK_GATE_OVRE);
+ clk_writel(0x00400000, LVL2_CLK_GATE_OVRE);
+ udelay(1);
+ clk_writel(0, LVL2_CLK_GATE_OVRE);
+ return 0;
+}
+
+static struct clk_ops tegra_msenc_clk_ops = {
+ .init = &tegra11_periph_clk_init,
+ .enable = &tegra11_msenc_clk_enable,
+ .disable = &tegra11_periph_clk_disable,
+ .set_parent = &tegra11_periph_clk_set_parent,
+ .set_rate = &tegra11_periph_clk_set_rate,
+ .round_rate = &tegra11_periph_clk_round_rate,
+ .reset = &tegra11_periph_clk_reset,
+};
+#endif
/* Periph extended clock configuration ops */
static int
tegra11_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
{
tegra11_periph_clk_init(c);
tegra_emc_dram_type_init(c);
- c->max_rate = clk_get_rate(c->parent);
}
-static long tegra11_emc_clk_round_rate(struct clk *c, unsigned long rate)
+static long tegra11_emc_clk_round_updown(struct clk *c, unsigned long rate,
+ bool up)
{
- long new_rate = rate;
+ long new_rate = max(rate, c->min_rate);
- new_rate = tegra_emc_round_rate(new_rate);
+ new_rate = tegra_emc_round_rate_updown(new_rate, up);
if (new_rate < 0)
new_rate = c->max_rate;
return new_rate;
}
+static long tegra11_emc_clk_round_rate(struct clk *c, unsigned long rate)
+{
+ return tegra11_emc_clk_round_updown(c, rate, true);
+}
+
static int tegra11_emc_clk_set_rate(struct clk *c, unsigned long rate)
{
int ret;
* to achieve requested rate. */
p = tegra_emc_predict_parent(rate, &div_value);
div_value += 2; /* emc has fractional DIV_U71 divider */
- if (!p)
+ if (IS_ERR_OR_NULL(p)) {
+ pr_err("%s: Failed to predict emc parent for rate %lu\n",
+ __func__, rate);
return -EINVAL;
+ }
if (p == c->parent) {
if (div_value == c->div)
return 0;
}
+static int tegra11_clk_emc_bus_update(struct clk *bus)
+{
+ struct clk *p = NULL;
+ unsigned long rate, old_rate, parent_rate, backup_rate;
+
+ if (detach_shared_bus)
+ return 0;
+
+ rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL);
+
+ old_rate = clk_get_rate_locked(bus);
+ if (rate == old_rate)
+ return 0;
+
+ if (!tegra_emc_is_parent_ready(rate, &p, &parent_rate, &backup_rate)) {
+ if (bus->parent == p) {
+ /* need backup to re-lock current parent */
+ int ret;
+ if (IS_ERR_VALUE(backup_rate)) {
+ pr_err("%s: No backup for %s rate %lu\n",
+ __func__, bus->name, rate);
+ return -EINVAL;
+ }
+
+ if (backup_rate < old_rate) /* skip lowering voltage */
+ bus->auto_dvfs = false;
+ ret = clk_set_rate_locked(bus, backup_rate);
+ bus->auto_dvfs = true;
+ if (ret) {
+ pr_err("%s: Failed to backup %s for rate %lu\n",
+ __func__, bus->name, rate);
+ return -EINVAL;
+ }
+ }
+ if (p->refcnt) {
+ pr_err("%s: %s has other than emc child\n",
+ __func__, p->name);
+ return -EINVAL;
+ }
+
+ if (clk_set_rate(p, parent_rate)) {
+ pr_err("%s: Failed to set %s rate %lu\n",
+ __func__, p->name, parent_rate);
+ return -EINVAL;
+ }
+ }
+
+ return clk_set_rate_locked(bus, rate);
+}
+
static struct clk_ops tegra_emc_clk_ops = {
.init = &tegra11_emc_clk_init,
.enable = &tegra11_periph_clk_enable,
.disable = &tegra11_periph_clk_disable,
.set_rate = &tegra11_emc_clk_set_rate,
.round_rate = &tegra11_emc_clk_round_rate,
+ .round_rate_updown = &tegra11_emc_clk_round_updown,
.reset = &tegra11_periph_clk_reset,
- .shared_bus_update = &tegra11_clk_shared_bus_update,
+ .shared_bus_update = &tegra11_clk_emc_bus_update,
};
/* Clock doubler ops (non-atomic shared register access) */
.set_parent = tegra11_audio_sync_clk_set_parent,
};
-/* cml0 (pcie), and cml1 (sata) clock ops */
-static void tegra11_cml_clk_init(struct clk *c)
-{
- u32 val = clk_readl(c->reg);
- c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
-}
-
-static int tegra11_cml_clk_enable(struct clk *c)
-{
- u32 val = clk_readl(c->reg);
- val |= (0x1 << c->u.periph.clk_num);
- clk_writel(val, c->reg);
- return 0;
-}
-
-static void tegra11_cml_clk_disable(struct clk *c)
-{
- u32 val = clk_readl(c->reg);
- val &= ~(0x1 << c->u.periph.clk_num);
- clk_writel(val, c->reg);
-}
-
-static struct clk_ops tegra_cml_clk_ops = {
- .init = &tegra11_cml_clk_init,
- .enable = &tegra11_cml_clk_enable,
- .disable = &tegra11_cml_clk_disable,
-};
-
/* cbus ops */
/*
return 0;
}
-static long tegra11_clk_cbus_round_rate(struct clk *c, unsigned long rate)
+static long tegra11_clk_cbus_round_updown(struct clk *c, unsigned long rate,
+ bool up)
{
int i;
- if (!c->dvfs)
+ if (!c->dvfs) {
+ if (!c->min_rate)
+ c->min_rate = c->parent->min_rate;
+ rate = max(rate, c->min_rate);
return rate;
+ }
/* update min now, since no dvfs table was available during init
(skip placeholder entries set to 1 kHz) */
}
rate = max(rate, c->min_rate);
- for (i = 0; i < (c->dvfs->num_freqs - 1); i++) {
+ for (i = 0; ; i++) {
unsigned long f = c->dvfs->freqs[i];
int mv = c->dvfs->millivolts[i];
- if ((f >= rate) || (mv >= c->dvfs->max_millivolts))
+ if ((f >= rate) || (mv >= c->dvfs->max_millivolts) ||
+ ((i + 1) >= c->dvfs->num_freqs)) {
+ if (!up && i && (f > rate))
+ i--;
break;
+ }
}
return c->dvfs->freqs[i];
}
+static long tegra11_clk_cbus_round_rate(struct clk *c, unsigned long rate)
+{
+ return tegra11_clk_cbus_round_updown(c, rate, true);
+}
+
static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort)
{
int ret = 0;
unsigned long backup_rate = clk_get_rate(c->shared_bus_backup.input);
rate = max(rate, clk_get_rate_locked(c));
+ rate = rate - (rate >> 2); /* 25% margin for backup rate */
if ((u64)rate * div < backup_rate)
div = DIV_ROUND_UP(backup_rate, rate);
return ret;
}
-static inline bool cbus_user_is_slower(struct clk *a, struct clk *b)
-{
- return a->u.shared_bus_user.client->max_rate * a->div <
- b->u.shared_bus_user.client->max_rate * b->div;
-}
-
-static inline bool cbus_user_request_is_lower(struct clk *a, struct clk *b)
-{
- return a->u.shared_bus_user.rate * a->div <
- b->u.shared_bus_user.rate * b->div;
-}
-
static inline void cbus_move_enabled_user(
struct clk *user, struct clk *dst, struct clk *src)
{
static int tegra11_clk_cbus_update(struct clk *bus)
{
int ret, mv;
- struct clk *c;
struct clk *slow = NULL;
struct clk *top = NULL;
-
- unsigned long top_rate = 0;
- unsigned long rate = bus->min_rate;
- unsigned long ceiling = bus->max_rate;
+ unsigned long rate;
+ unsigned long old_rate;
+ unsigned long ceiling;
if (detach_shared_bus)
return 0;
- list_for_each_entry(c, &bus->shared_bus_list,
- u.shared_bus_user.node) {
- /* Ignore requests from disabled users */
- if (c->u.shared_bus_user.enabled) {
- unsigned long request_rate = c->u.shared_bus_user.rate *
- (c->div ? : 1);
-
- switch (c->u.shared_bus_user.mode) {
- case SHARED_CEILING:
- ceiling = min(request_rate, ceiling);
- break;
- case SHARED_AUTO:
- break;
- case SHARED_FLOOR:
- default:
- rate = max(request_rate, rate);
- if (c->u.shared_bus_user.client) {
- if (top_rate < request_rate) {
- top_rate = request_rate;
- top = c;
- } else if ((top_rate == request_rate) &&
- cbus_user_is_slower(c, top)) {
- top = c;
- }
- }
- }
- if (c->u.shared_bus_user.client &&
- (!slow || cbus_user_is_slower(c, slow)))
- slow = c;
- }
- }
+ rate = tegra11_clk_shared_bus_update(bus, &top, &slow, &ceiling);
/* use dvfs table of the slowest enabled client as cbus dvfs table */
if (bus->dvfs && slow && (slow != bus->u.cbus.slow_user)) {
/* update bus state variables and rate */
bus->u.cbus.slow_user = slow;
bus->u.cbus.top_user = top;
- rate = min(rate, ceiling);
- rate = bus->ops->round_rate(bus, rate);
+ rate = tegra11_clk_cap_shared_bus(bus, rate, ceiling);
mv = tegra_dvfs_predict_millivolts(bus, rate);
if (IS_ERR_VALUE(mv))
return -EINVAL;
}
}
- ret = bus->ops->set_rate(bus, rate);
- if (ret)
- return ret;
+ old_rate = clk_get_rate_locked(bus);
+ if (IS_ENABLED(CONFIG_TEGRA_MIGRATE_CBUS_USERS) || (old_rate != rate)) {
+ ret = bus->ops->set_rate(bus, rate);
+ if (ret)
+ return ret;
+ }
if (bus->dvfs) {
if (bus->refcnt && (mv <= 0)) {
}
}
+ clk_rate_change_notify(bus, rate);
return 0;
};
+#else
+static int tegra11_clk_cbus_update(struct clk *bus)
+{
+ unsigned long rate, old_rate;
+
+ if (detach_shared_bus)
+ return 0;
+
+ rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL);
+
+ old_rate = clk_get_rate_locked(bus);
+ if (rate == old_rate)
+ return 0;
+
+ return clk_set_rate_locked(bus, rate);
+}
#endif
static int tegra11_clk_cbus_migrate_users(struct clk *user)
/* Make sure top user on the source bus is requesting highest rate */
if (!src_bus->u.cbus.top_user || (dst_bus->u.cbus.top_user &&
- cbus_user_request_is_lower(src_bus->u.cbus.top_user,
+ bus_user_request_is_lower(src_bus->u.cbus.top_user,
dst_bus->u.cbus.top_user)))
swap(src_bus, dst_bus);
/* If top user is the slow one on its own (source) bus, do nothing */
top_user = src_bus->u.cbus.top_user;
BUG_ON(!top_user->u.shared_bus_user.client);
- if (!cbus_user_is_slower(src_bus->u.cbus.slow_user, top_user))
+ if (!bus_user_is_slower(src_bus->u.cbus.slow_user, top_user))
return 0;
/* If source bus top user is slower than all users on destination bus,
move top user; otherwise move all users slower than the top one */
if (!dst_bus->u.cbus.slow_user ||
- !cbus_user_is_slower(dst_bus->u.cbus.slow_user, top_user)) {
+ !bus_user_is_slower(dst_bus->u.cbus.slow_user, top_user)) {
cbus_move_enabled_user(top_user, dst_bus, src_bus);
} else {
list_for_each_safe(pos, n, &src_bus->shared_bus_list) {
c = list_entry(pos, struct clk, u.shared_bus_user.node);
if (c->u.shared_bus_user.enabled &&
c->u.shared_bus_user.client &&
- cbus_user_is_slower(c, top_user))
+ bus_user_is_slower(c, top_user))
cbus_move_enabled_user(c, dst_bus, src_bus);
}
}
.enable = tegra11_clk_cbus_enable,
.set_rate = tegra11_clk_cbus_set_rate,
.round_rate = tegra11_clk_cbus_round_rate,
-#ifdef CONFIG_TEGRA_DYNAMIC_CBUS
+ .round_rate_updown = tegra11_clk_cbus_round_updown,
.shared_bus_update = tegra11_clk_cbus_update,
-#else
- .shared_bus_update = tegra11_clk_shared_bus_update,
-#endif
};
/* shared bus ops */
* clock to each user. The frequency of the bus is set to the highest
* enabled shared_bus_user clock, with a minimum value set by the
* shared bus.
+ *
+ * Optionally shared bus may support users migration. Since shared bus and
+ * its * children (users) have reversed rate relations: user rates determine
+ * bus rate, * switching user from one parent/bus to another may change rates
+ * of both parents. Therefore we need a cross-bus lock on top of individual
+ * user and bus locks. For now, limit bus switch support to cbus only if
+ * CONFIG_TEGRA_MIGRATE_CBUS_USERS is set.
*/
-static int tegra11_clk_shared_bus_update(struct clk *bus)
+static unsigned long tegra11_clk_shared_bus_update(struct clk *bus,
+ struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap)
{
struct clk *c;
- unsigned long old_rate;
+ struct clk *slow = NULL;
+ struct clk *top = NULL;
+
+ unsigned long override_rate = 0;
+ unsigned long top_rate = 0;
unsigned long rate = bus->min_rate;
unsigned long bw = 0;
unsigned long ceiling = bus->max_rate;
-
- if (detach_shared_bus)
- return 0;
+ u8 emc_bw_efficiency = tegra_emc_bw_efficiency;
list_for_each_entry(c, &bus->shared_bus_list,
u.shared_bus_user.node) {
- /* Ignore requests from disabled users */
- if (c->u.shared_bus_user.enabled) {
+ /*
+ * Ignore requests from disabled floor and bw users, and from
+ * auto-users riding the bus. Always honor ceiling users, even
+ * if they are disabled - we do not want to keep enabled parent
+ * bus just because ceiling is set.
+ */
+ if (c->u.shared_bus_user.enabled ||
+ (c->u.shared_bus_user.mode == SHARED_CEILING)) {
unsigned long request_rate = c->u.shared_bus_user.rate *
(c->div ? : 1);
switch (c->u.shared_bus_user.mode) {
case SHARED_BW:
bw += request_rate;
+ if (bw > bus->max_rate)
+ bw = bus->max_rate;
break;
case SHARED_CEILING:
ceiling = min(request_rate, ceiling);
break;
+ case SHARED_OVERRIDE:
+ if (override_rate == 0)
+ override_rate = request_rate;
+ break;
case SHARED_AUTO:
break;
case SHARED_FLOOR:
default:
rate = max(request_rate, rate);
+ if (c->u.shared_bus_user.client
+ && request_rate) {
+ if (top_rate < request_rate) {
+ top_rate = request_rate;
+ top = c;
+ } else if ((top_rate == request_rate) &&
+ bus_user_is_slower(c, top)) {
+ top = c;
+ }
+ }
}
+ if (c->u.shared_bus_user.client &&
+ (!slow || bus_user_is_slower(c, slow)))
+ slow = c;
}
}
- rate = min(max(rate, bw), ceiling);
- rate = clk_round_rate_locked(bus, rate);
- old_rate = clk_get_rate_locked(bus);
- if (rate == old_rate)
- return 0;
+ if ((bus->flags & PERIPH_EMC_ENB) && bw && (emc_bw_efficiency < 100)) {
+ bw = emc_bw_efficiency ?
+ (bw / emc_bw_efficiency) : bus->max_rate;
+ bw = (bw < bus->max_rate / 100) ? (bw * 100) : bus->max_rate;
+ }
- return clk_set_rate_locked(bus, rate);
+ rate = override_rate ? : max(rate, bw);
+ ceiling = override_rate ? bus->max_rate : ceiling;
+
+ if (bus_top && bus_slow && rate_cap) {
+ /* If dynamic bus dvfs table, let the caller to complete
+ rounding and aggregation */
+ *bus_top = top;
+ *bus_slow = slow;
+ *rate_cap = ceiling;
+ } else {
+ /* If satic bus dvfs table, complete rounding and aggregation */
+ rate = tegra11_clk_cap_shared_bus(bus, rate, ceiling);
+ }
+
+ return rate;
};
+static unsigned long tegra11_clk_cap_shared_bus(struct clk *bus,
+ unsigned long rate, unsigned long ceiling)
+{
+ if (bus->ops && bus->ops->round_rate_updown)
+ ceiling = bus->ops->round_rate_updown(bus, ceiling, false);
+
+ rate = min(rate, ceiling);
+
+ if (bus->ops && bus->ops->round_rate)
+ rate = bus->ops->round_rate(bus, rate);
+
+ return rate;
+}
+
static int tegra_clk_shared_bus_migrate_users(struct clk *user)
{
if (detach_shared_bus)
return -ENOSYS;
}
-static void tegra_clk_shared_bus_init(struct clk *c)
+static void tegra_clk_shared_bus_user_init(struct clk *c)
{
c->max_rate = c->parent->max_rate;
c->u.shared_bus_user.rate = c->parent->max_rate;
c->state = OFF;
c->set = true;
+ if (c->u.shared_bus_user.mode == SHARED_CEILING) {
+ c->state = ON;
+ c->refcnt++;
+ }
+
if (c->u.shared_bus_user.client_id) {
c->u.shared_bus_user.client =
tegra_get_clock_by_name(c->u.shared_bus_user.client_id);
&c->parent->shared_bus_list);
}
-/*
- * Shared bus and its children/users have reversed rate relations - user rates
- * determine bus rate. Hence switching user from one parent/bus to another may
- * change rates of both parents. Therefore we need a cross-bus lock on top of
- * individual user and bus locks. For now limit bus switch support to cansleep
- * users with cross-clock mutex only.
- */
-static int tegra_clk_shared_bus_set_parent(struct clk *c, struct clk *p)
+static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
{
+ int ret;
const struct clk_mux_sel *sel;
if (detach_shared_bus)
clk_enable(p);
list_move_tail(&c->u.shared_bus_user.node, &p->shared_bus_list);
- tegra_clk_shared_bus_update(p);
+ ret = tegra_clk_shared_bus_update(p);
+ if (ret) {
+ list_move_tail(&c->u.shared_bus_user.node,
+ &c->parent->shared_bus_list);
+ tegra_clk_shared_bus_update(c->parent);
+ clk_disable(p);
+ return ret;
+ }
+
tegra_clk_shared_bus_update(c->parent);
- if (c->refcnt && c->parent)
+ if (c->refcnt)
clk_disable(c->parent);
clk_reparent(c, p);
return 0;
}
-static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
+static int tegra_clk_shared_bus_user_set_rate(struct clk *c, unsigned long rate)
{
+ int ret;
+
c->u.shared_bus_user.rate = rate;
- tegra_clk_shared_bus_update(c->parent);
+ ret = tegra_clk_shared_bus_update(c->parent);
- if (c->cross_clk_mutex && clk_cansleep(c))
+ if (!ret && c->cross_clk_mutex && clk_cansleep(c))
tegra_clk_shared_bus_migrate_users(c);
- return 0;
+ return ret;
}
-static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
+static long tegra_clk_shared_bus_user_round_rate(
+ struct clk *c, unsigned long rate)
{
/* Defer rounding requests until aggregated. BW users must not be
rounded at all, others just clipped to bus range (some clients
return rate;
}
-static int tegra_clk_shared_bus_enable(struct clk *c)
+static int tegra_clk_shared_bus_user_enable(struct clk *c)
{
- int ret = 0;
+ int ret;
c->u.shared_bus_user.enabled = true;
- tegra_clk_shared_bus_update(c->parent);
- if (c->u.shared_bus_user.client)
+ ret = tegra_clk_shared_bus_update(c->parent);
+ if (!ret && c->u.shared_bus_user.client)
ret = clk_enable(c->u.shared_bus_user.client);
- if (c->cross_clk_mutex && clk_cansleep(c))
+ if (!ret && c->cross_clk_mutex && clk_cansleep(c))
tegra_clk_shared_bus_migrate_users(c);
return ret;
}
-static void tegra_clk_shared_bus_disable(struct clk *c)
+static void tegra_clk_shared_bus_user_disable(struct clk *c)
{
if (c->u.shared_bus_user.client)
clk_disable(c->u.shared_bus_user.client);
tegra_clk_shared_bus_migrate_users(c);
}
-static void tegra_clk_shared_bus_reset(struct clk *c, bool assert)
+static void tegra_clk_shared_bus_user_reset(struct clk *c, bool assert)
{
if (c->u.shared_bus_user.client) {
if (c->u.shared_bus_user.client->ops &&
}
}
-static struct clk_ops tegra_clk_shared_bus_ops = {
- .init = tegra_clk_shared_bus_init,
- .enable = tegra_clk_shared_bus_enable,
- .disable = tegra_clk_shared_bus_disable,
- .set_parent = tegra_clk_shared_bus_set_parent,
- .set_rate = tegra_clk_shared_bus_set_rate,
- .round_rate = tegra_clk_shared_bus_round_rate,
- .reset = tegra_clk_shared_bus_reset,
+static struct clk_ops tegra_clk_shared_bus_user_ops = {
+ .init = tegra_clk_shared_bus_user_init,
+ .enable = tegra_clk_shared_bus_user_enable,
+ .disable = tegra_clk_shared_bus_user_disable,
+ .set_parent = tegra_clk_shared_bus_user_set_parent,
+ .set_rate = tegra_clk_shared_bus_user_set_rate,
+ .round_rate = tegra_clk_shared_bus_user_round_rate,
+ .reset = tegra_clk_shared_bus_user_reset,
};
+/* coupled gate ops */
+/*
+ * Some clocks may have common enable/disable control, but run at different
+ * rates, and have different dvfs tables. Coupled gate clock synchronize
+ * enable/disable operations for such clocks.
+ */
+
+static int tegra11_clk_coupled_gate_enable(struct clk *c)
+{
+ int ret;
+ const struct clk_mux_sel *sel;
+
+ BUG_ON(!c->inputs);
+ pr_debug("%s on clock %s\n", __func__, c->name);
+
+ for (sel = c->inputs; sel->input != NULL; sel++) {
+ if (sel->input == c->parent)
+ continue;
+
+ ret = clk_enable(sel->input);
+ if (ret) {
+ while(sel != c->inputs) {
+ sel--;
+ if (sel->input == c->parent)
+ continue;
+ clk_disable(sel->input);
+ }
+ return ret;
+ }
+ }
+
+ return tegra11_periph_clk_enable(c);
+}
+
+static void tegra11_clk_coupled_gate_disable(struct clk *c)
+{
+ const struct clk_mux_sel *sel;
+
+ BUG_ON(!c->inputs);
+ pr_debug("%s on clock %s\n", __func__, c->name);
+
+ tegra11_periph_clk_disable(c);
+
+ if (!c->refcnt) /* happens only on boot clean-up: don't propagate */
+ return;
+
+ for (sel = c->inputs; sel->input != NULL; sel++) {
+ if (sel->input == c->parent)
+ continue;
+
+ if (sel->input->set) /* enforce coupling after boot only */
+ clk_disable(sel->input);
+ }
+}
+
+static struct clk_ops tegra_clk_coupled_gate_ops = {
+ .init = tegra11_periph_clk_init,
+ .enable = tegra11_clk_coupled_gate_enable,
+ .disable = tegra11_clk_coupled_gate_disable,
+ .reset = &tegra11_periph_clk_reset,
+};
+
+
/* Clock definitions */
static struct clk tegra_clk_32k = {
.name = "clk_32k",
};
static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+ { 12000000, 624000000, 104, 1, 2},
{ 12000000, 600000000, 100, 1, 2},
{ 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
{ 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
static struct clk tegra_pll_c_out1 = {
.name = "pll_c_out1",
.ops = &tegra_pll_div_ops,
- .flags = DIV_U71 | PERIPH_ON_CBUS,
+#ifdef CONFIG_TEGRA_DUAL_CBUS
+ .flags = DIV_U71 | DIV_U71_INT,
+#else
+ .flags = DIV_U71 | DIV_U71_INT | PERIPH_ON_CBUS,
+#endif
.parent = &tegra_pll_c,
.reg = 0x84,
.reg_shift = 0,
.input_max = 48000000,
.cf_min = 12000000,
.cf_max = 19200000,
- .vco_min = 739000000,
- .vco_max = 1200000000,
+ .vco_min = 624000000,
+ .vco_max = 1248000000,
.freq_table = tegra_pll_cx_freq_table,
.lock_delay = 300,
.misc1 = 0x4f0 - 0x4e8,
.input_max = 48000000,
.cf_min = 12000000,
.cf_max = 19200000,
- .vco_min = 739000000,
- .vco_max = 1200000000,
+ .vco_min = 624000000,
+ .vco_max = 1248000000,
.freq_table = tegra_pll_cx_freq_table,
.lock_delay = 300,
.misc1 = 0x504 - 0x4fc,
.ops = &tegra_pllm_ops,
.reg = 0x90,
.parent = &tegra_pll_ref,
- .max_rate = 800000000,
+ .max_rate = 1066000000,
.u.pll = {
.input_min = 12000000,
.input_max = 500000000,
.cf_min = 12000000,
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
.vco_min = 400000000,
- .vco_max = 800000000,
+ .vco_max = 1066000000,
.freq_table = tegra_pll_m_freq_table,
.lock_delay = 300,
.misc1 = 0x98 - 0x90,
static struct clk tegra_pll_m_out1 = {
.name = "pll_m_out1",
.ops = &tegra_pll_div_ops,
- .flags = DIV_U71,
+ .flags = DIV_U71 | DIV_U71_INT,
.parent = &tegra_pll_m,
.reg = 0x94,
.reg_shift = 0,
- .max_rate = 600000000,
+ .max_rate = 1066000000,
};
static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
.input_max = 31000000,
.cf_min = 1000000,
.cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1400000000,
+ .vco_min = 200000000,
+ .vco_max = 700000000,
.freq_table = tegra_pll_p_freq_table,
.lock_delay = 300,
},
static struct clk tegra_pll_p_out2 = {
.name = "pll_p_out2",
.ops = &tegra_pll_div_ops,
- .flags = DIV_U71 | DIV_U71_FIXED,
+ .flags = DIV_U71 | DIV_U71_FIXED | DIV_U71_INT,
.parent = &tegra_pll_p,
.reg = 0xa4,
.reg_shift = 16,
};
static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
- { 9600000, 564480000, 294, 5, 1, 4},
- { 9600000, 552960000, 288, 5, 1, 4},
- { 9600000, 24000000, 5, 2, 1, 1},
+ { 9600000, 282240000, 147, 5, 1, 4},
+ { 9600000, 368640000, 192, 5, 1, 4},
+ { 9600000, 240000000, 200, 8, 1, 8},
- { 28800000, 56448000, 49, 25, 1, 1},
- { 28800000, 73728000, 64, 25, 1, 1},
- { 28800000, 24000000, 5, 6, 1, 1},
+ { 28800000, 282240000, 245, 25, 1, 8},
+ { 28800000, 368640000, 320, 25, 1, 8},
+ { 28800000, 240000000, 200, 24, 1, 8},
{ 0, 0, 0, 0, 0, 0 },
};
.input_max = 31000000,
.cf_min = 1000000,
.cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1400000000,
+ .vco_min = 200000000,
+ .vco_max = 700000000,
.freq_table = tegra_pll_a_freq_table,
.lock_delay = 300,
},
};
static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
- { 12000000, 216000000, 216, 12, 1, 4},
- { 13000000, 216000000, 216, 13, 1, 4},
- { 16800000, 216000000, 180, 14, 1, 4},
- { 19200000, 216000000, 180, 16, 1, 4},
- { 26000000, 216000000, 216, 26, 1, 4},
-
- { 12000000, 594000000, 594, 12, 1, 8},
- { 13000000, 594000000, 594, 13, 1, 8},
- { 16800000, 594000000, 495, 14, 1, 8},
- { 19200000, 594000000, 495, 16, 1, 8},
- { 26000000, 594000000, 594, 26, 1, 8},
+ { 12000000, 216000000, 864, 12, 4, 12},
+ { 13000000, 216000000, 864, 13, 4, 12},
+ { 16800000, 216000000, 720, 14, 4, 12},
+ { 19200000, 216000000, 720, 16, 4, 12},
+ { 26000000, 216000000, 864, 26, 4, 12},
+
+ { 12000000, 594000000, 99, 2, 1, 8},
+ { 13000000, 594000000, 594, 13, 1, 12},
+ { 16800000, 594000000, 495, 14, 1, 12},
+ { 19200000, 594000000, 495, 16, 1, 12},
+ { 26000000, 594000000, 594, 26, 1, 12},
{ 12000000, 1000000000, 1000, 12, 1, 12},
{ 13000000, 1000000000, 1000, 13, 1, 12},
- { 19200000, 1000000000, 625, 12, 1, 8},
+ { 19200000, 1000000000, 625, 12, 1, 12},
{ 26000000, 1000000000, 1000, 26, 1, 12},
{ 0, 0, 0, 0, 0, 0 },
.input_max = 40000000,
.cf_min = 1000000,
.cf_max = 6000000,
- .vco_min = 40000000,
+ .vco_min = 500000000,
.vco_max = 1000000000,
.freq_table = tegra_pll_d_freq_table,
.lock_delay = 1000,
.input_max = 40000000,
.cf_min = 1000000,
.cf_max = 6000000,
- .vco_min = 40000000,
+ .vco_min = 500000000,
.vco_max = 1000000000,
.freq_table = tegra_pll_d_freq_table,
.lock_delay = 1000,
.vco_max = 960000000,
.freq_table = tegra_pll_u_freq_table,
.lock_delay = 1000,
+ .cpcon_default = 12,
},
};
static struct clk tegra_pll_u_480M = {
.name = "pll_u_480M",
.flags = PLLU,
+ .ops = &tegra_pll_div_ops,
+ .reg = 0xc0,
+ .reg_shift = 22,
.parent = &tegra_pll_u,
.mul = 1,
.div = 1,
- .state = ON,
.max_rate = 480000000,
};
static struct clk tegra_pll_u_60M = {
.name = "pll_u_60M",
.flags = PLLU,
+ .ops = &tegra_pll_div_ops,
+ .reg = 0xc0,
+ .reg_shift = 23,
.parent = &tegra_pll_u,
.mul = 1,
.div = 8,
- .state = ON,
.max_rate = 60000000,
};
static struct clk tegra_pll_u_48M = {
.name = "pll_u_48M",
.flags = PLLU,
+ .ops = &tegra_pll_div_ops,
+ .reg = 0xc0,
+ .reg_shift = 25,
.parent = &tegra_pll_u,
.mul = 1,
.div = 10,
- .state = ON,
.max_rate = 48000000,
};
+static struct clk tegra_pll_u_12M = {
+ .name = "pll_u_12M",
+ .flags = PLLU,
+ .ops = &tegra_pll_div_ops,
+ .reg = 0xc0,
+ .reg_shift = 21,
+ .parent = &tegra_pll_u,
+ .mul = 1,
+ .div = 40,
+ .max_rate = 12000000,
+};
+
static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
/* 1 GHz */
{ 12000000, 1000000000, 83, 1, 1}, /* actual: 996.0 MHz */
.cf_min = 12000000,
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
.vco_min = 700000000,
- .vco_max = 1800000000,
+ .vco_max = 2400000000U,
.freq_table = tegra_pll_x_freq_table,
.lock_delay = 300,
.misc1 = 0x510 - 0xe0,
};
/* FIXME: remove; for now, should be always checked-in as "0" */
-#define USE_IRAM_TO_TEST_DFLL 0
#define USE_LP_CPU_TO_TEST_DFLL 0
-static struct tegra_cl_dvfs cpu_cl_dvfs = {
-#if USE_IRAM_TO_TEST_DFLL
- .cl_base = (u32)IO_ADDRESS(TEGRA_IRAM_BASE + 0x3f000),
-#else
- .cl_base = (u32)IO_ADDRESS(TEGRA_CL_DVFS_BASE),
-#endif
-};
-
static struct clk tegra_dfll_cpu = {
.name = "dfll_cpu",
.flags = DFLL,
.ops = &tegra_dfll_ops,
.reg = 0x2f4,
- .max_rate = 1800000000,
- .u.dfll = {
- .cl_dvfs = &cpu_cl_dvfs,
- },
+ .max_rate = 2000000000,
};
-static int tegra11_dfll_cpu_late_init(void)
-{
-#if !USE_IRAM_TO_TEST_DFLL
-#ifndef CONFIG_TEGRA_SILICON_PLATFORM
- u32 netlist, patchid;
- tegra_get_netlist_revision(&netlist, &patchid);
- if (netlist < 12) {
- pr_err("%s: CL-DVFS is not available on net %d\n",
- __func__, netlist);
- return -ENOSYS;
- }
-#endif
-#endif
- return tegra_init_cl_dvfs(&tegra_dfll_cpu);
-}
-late_initcall(tegra11_dfll_cpu_late_init);
-
static struct clk tegra_pll_re_vco = {
.name = "pll_re_vco",
.flags = PLL_ALT_MISC_REG,
.ops = &tegra_pllre_ops,
.reg = 0x4c4,
.parent = &tegra_pll_ref,
- .max_rate = 600000000,
+ .max_rate = 672000000,
.u.pll = {
.input_min = 12000000,
.input_max = 1000000000,
.cf_min = 12000000,
.cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
.vco_min = 300000000,
- .vco_max = 600000000,
+ .vco_max = 672000000,
.lock_delay = 300,
.round_p_to_pdiv = pllre_round_p_to_pdiv,
},
.ops = &tegra_pllre_out_ops,
.parent = &tegra_pll_re_vco,
.reg = 0x4c4,
- .max_rate = 600000000,
+ .max_rate = 672000000,
};
static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
/* PLLE special case: use cpcon field to store cml divider value */
- { 12000000, 100000000, 150, 1, 18, 11},
- { 216000000, 100000000, 200, 18, 24, 13},
-#ifndef CONFIG_TEGRA_SILICON_PLATFORM
- { 13000000, 100000000, 200, 1, 26, 13},
-#endif
+ { 336000000, 100000000, 100, 21, 16, 11},
+ { 312000000, 100000000, 200, 26, 24, 13},
+ { 12000000, 100000000, 200, 1, 24, 13},
{ 0, 0, 0, 0, 0, 0 },
};
.max_rate = 100000000,
.u.pll = {
.input_min = 12000000,
- .input_max = 216000000,
+ .input_max = 1000000000,
.cf_min = 12000000,
- .cf_max = 12000000,
- .vco_min = 1200000000,
+ .cf_max = 75000000,
+ .vco_min = 1600000000,
.vco_max = 2400000000U,
.freq_table = tegra_pll_e_freq_table,
.lock_delay = 300,
},
};
-static struct clk tegra_cml0_clk = {
- .name = "cml0",
- .parent = &tegra_pll_e,
- .ops = &tegra_cml_clk_ops,
- .reg = PLLE_AUX,
- .max_rate = 100000000,
- .u.periph = {
- .clk_num = 0,
- },
-};
-
-static struct clk tegra_cml1_clk = {
- .name = "cml1",
- .parent = &tegra_pll_e,
- .ops = &tegra_cml_clk_ops,
- .reg = PLLE_AUX,
- .max_rate = 100000000,
- .u.periph = {
- .clk_num = 1,
- },
-};
-
static struct clk tegra_pciex_clk = {
.name = "pciex",
.parent = &tegra_pll_e,
};
/* Audio sync clocks */
-#define SYNC_SOURCE(_id) \
+#define SYNC_SOURCE(_id, _dev) \
{ \
.name = #_id "_sync", \
+ .lookup = { \
+ .dev_id = #_dev , \
+ .con_id = "ext_audio_sync", \
+ }, \
.rate = 24000000, \
.max_rate = 24000000, \
.ops = &tegra_sync_source_ops \
}
static struct clk tegra_sync_source_list[] = {
- SYNC_SOURCE(spdif_in),
- SYNC_SOURCE(i2s0),
- SYNC_SOURCE(i2s1),
- SYNC_SOURCE(i2s2),
- SYNC_SOURCE(i2s3),
- SYNC_SOURCE(i2s4),
- SYNC_SOURCE(vimclk),
+ SYNC_SOURCE(spdif_in, tegra30-spdif),
+ SYNC_SOURCE(i2s0, tegra30-i2s.0),
+ SYNC_SOURCE(i2s1, tegra30-i2s.1),
+ SYNC_SOURCE(i2s2, tegra30-i2s.2),
+ SYNC_SOURCE(i2s3, tegra30-i2s.3),
+ SYNC_SOURCE(i2s4, tegra30-i2s.4),
+ SYNC_SOURCE(vimclk, vimclk),
};
static struct clk_mux_sel mux_d_audio_clk[] = {
{ 0, 0 }
};
-#define AUDIO_SYNC_CLK(_id, _index) \
+#define AUDIO_SYNC_CLK(_id, _dev, _index) \
{ \
.name = #_id, \
+ .lookup = { \
+ .dev_id = #_dev, \
+ .con_id = "audio_sync", \
+ }, \
.inputs = mux_audio_sync_clk, \
.reg = 0x4A0 + (_index) * 4, \
.max_rate = 24000000, \
.ops = &tegra_audio_sync_clk_ops \
}
static struct clk tegra_clk_audio_list[] = {
- AUDIO_SYNC_CLK(audio0, 0),
- AUDIO_SYNC_CLK(audio1, 1),
- AUDIO_SYNC_CLK(audio2, 2),
- AUDIO_SYNC_CLK(audio3, 3),
- AUDIO_SYNC_CLK(audio4, 4),
- AUDIO_SYNC_CLK(audio, 5), /* SPDIF */
+ AUDIO_SYNC_CLK(audio0, tegra30-i2s.0, 0),
+ AUDIO_SYNC_CLK(audio1, tegra30-i2s.1, 1),
+ AUDIO_SYNC_CLK(audio2, tegra30-i2s.2, 2),
+ AUDIO_SYNC_CLK(audio3, tegra30-i2s.3, 3),
+ AUDIO_SYNC_CLK(audio4, tegra30-i2s.4, 4),
+ AUDIO_SYNC_CLK(audio, tegra30-spdif, 5), /* SPDIF */
};
-#define AUDIO_SYNC_2X_CLK(_id, _index) \
+#define AUDIO_SYNC_2X_CLK(_id, _dev, _index) \
{ \
.name = #_id "_2x", \
+ .lookup = { \
+ .dev_id = #_dev, \
+ .con_id = "audio_sync_2x" \
+ }, \
.flags = PERIPH_NO_RESET, \
.max_rate = 48000000, \
.ops = &tegra_clk_double_ops, \
}, \
}
static struct clk tegra_clk_audio_2x_list[] = {
- AUDIO_SYNC_2X_CLK(audio0, 0),
- AUDIO_SYNC_2X_CLK(audio1, 1),
- AUDIO_SYNC_2X_CLK(audio2, 2),
- AUDIO_SYNC_2X_CLK(audio3, 3),
- AUDIO_SYNC_2X_CLK(audio4, 4),
- AUDIO_SYNC_2X_CLK(audio, 5), /* SPDIF */
+ AUDIO_SYNC_2X_CLK(audio0, tegra30-i2s.0, 0),
+ AUDIO_SYNC_2X_CLK(audio1, tegra30-i2s.1, 1),
+ AUDIO_SYNC_2X_CLK(audio2, tegra30-i2s.2, 2),
+ AUDIO_SYNC_2X_CLK(audio3, tegra30-i2s.3, 3),
+ AUDIO_SYNC_2X_CLK(audio4, tegra30-i2s.4, 4),
+ AUDIO_SYNC_2X_CLK(audio, tegra30-spdif, 5), /* SPDIF */
};
#define MUX_I2S_SPDIF(_id, _index) \
mux_clkm_clkm2_clkm4_extern3,
};
-#define CLK_OUT_CLK(_id) \
+#define CLK_OUT_CLK(_id, _max_rate) \
{ \
.name = "clk_out_" #_id, \
.lookup = { \
.reg = 0x1a8, \
.inputs = mux_clkm_clkm2_clkm4_extern##_id, \
.flags = MUX_CLK_OUT, \
- .max_rate = 216000000, \
+ .max_rate = _max_rate, \
.u.periph = { \
.clk_num = (_id - 1) * 8 + 2, \
}, \
}
static struct clk tegra_clk_out_list[] = {
- CLK_OUT_CLK(1),
- CLK_OUT_CLK(2),
- CLK_OUT_CLK(3),
+ CLK_OUT_CLK(1, 12288000),
+ CLK_OUT_CLK(2, 40800000),
+ CLK_OUT_CLK(3, 12288000),
};
/* called after peripheral external clocks are initialized */
{ .input = &tegra_clk_m, .value = 0},
{ .input = &tegra_pll_c_out1, .value = 1},
{ .input = &tegra_pll_p_out4, .value = 2},
- { .input = &tegra_pll_p_out3, .value = 3},
+ { .input = &tegra_pll_p, .value = 3},
{ .input = &tegra_pll_p_out2, .value = 4},
/* { .input = &tegra_clk_d, .value = 5}, - no use on tegra11x */
{ .input = &tegra_clk_32k, .value = 6},
.inputs = mux_cclk_g,
.reg = 0x368,
.ops = &tegra_super_ops,
- .max_rate = 1800000000,
+ .max_rate = 2000000000,
};
static struct clk tegra_clk_cclk_lp = {
.inputs = mux_cclk_lp,
.reg = 0x370,
.ops = &tegra_super_ops,
- .max_rate = 620000000,
+ .max_rate = 816000000,
};
static struct clk tegra_clk_sclk = {
.inputs = mux_sclk,
.reg = 0x28,
.ops = &tegra_super_ops,
- .max_rate = 334000000,
- .min_rate = 40000000,
+ .max_rate = 384000000,
+ .min_rate = 12000000,
};
static struct clk tegra_clk_virtual_cpu_g = {
.name = "cpu_g",
.parent = &tegra_clk_cclk_g,
.ops = &tegra_cpu_ops,
- .max_rate = 1800000000,
+ .max_rate = 2000000000,
.u.cpu = {
.main = &tegra_pll_x,
.backup = &tegra_pll_p_out4,
.name = "cpu_lp",
.parent = &tegra_clk_cclk_lp,
.ops = &tegra_cpu_ops,
- .max_rate = 620000000,
+ .max_rate = 816000000,
.u.cpu = {
.main = &tegra_pll_x,
.backup = &tegra_pll_p_out4,
.name = "cpu",
.inputs = mux_cpu_cmplx,
.ops = &tegra_cpu_cmplx_ops,
- .max_rate = 1800000000,
+ .max_rate = 2000000000,
};
static struct clk tegra_clk_cop = {
.name = "cop",
.parent = &tegra_clk_sclk,
.ops = &tegra_cop_ops,
- .max_rate = 334000000,
+ .max_rate = 384000000,
};
static struct clk tegra_clk_hclk = {
.reg = 0x30,
.reg_shift = 4,
.ops = &tegra_bus_ops,
- .max_rate = 334000000,
- .min_rate = 40000000,
+ .max_rate = 384000000,
+ .min_rate = 12000000,
};
static struct clk tegra_clk_pclk = {
.reg = 0x30,
.reg_shift = 0,
.ops = &tegra_bus_ops,
- .max_rate = 167000000,
- .min_rate = 40000000,
+ .max_rate = 192000000,
+ .min_rate = 12000000,
};
static struct raw_notifier_head sbus_rate_change_nh;
.pclk = &tegra_clk_pclk,
.hclk = &tegra_clk_hclk,
.sclk_low = &tegra_pll_p_out2,
+#ifdef CONFIG_TEGRA_PLLM_SCALED
+ .sclk_high = &tegra_pll_c_out1,
+#else
.sclk_high = &tegra_pll_m_out1,
+#endif
},
.rate_change_nh = &sbus_rate_change_nh,
};
};
/* EMC muxes */
-/* FIXME: update main EMC mux to match h/w, and add EMC latency mux*/
+/* FIXME: add EMC latency mux */
static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
{ .input = &tegra_pll_m, .value = 0},
- /* { .input = &tegra_pll_c, .value = 1}, not used on tegra11x */
+ { .input = &tegra_pll_c, .value = 1},
{ .input = &tegra_pll_p, .value = 2},
{ .input = &tegra_clk_m, .value = 3},
+ { .input = &tegra_pll_m, .value = 4}, /* low jitter PLLM input */
{ 0, 0},
};
{ 0, 0},
};
+static struct clk_mux_sel mux_clkm_pllp_pllc_pllre[] = {
+ { .input = &tegra_clk_m, .value = 0},
+ { .input = &tegra_pll_p, .value = 1},
+ { .input = &tegra_pll_c, .value = 3},
+ { .input = &tegra_pll_re_vco, .value = 5},
+ { 0, 0},
+};
+
+static struct clk_mux_sel mux_clkm_48M_pllp_480M[] = {
+ { .input = &tegra_clk_m, .value = 0},
+ { .input = &tegra_pll_u_48M, .value = 1},
+ { .input = &tegra_pll_p, .value = 2},
+ { .input = &tegra_pll_u_480M, .value = 3},
+ { 0, 0},
+};
+
+static struct clk_mux_sel mux_clkm_pllre_clk32_480M_pllc_ref[] = {
+ { .input = &tegra_clk_m, .value = 0},
+ { .input = &tegra_pll_re_vco, .value = 1},
+ { .input = &tegra_clk_32k, .value = 2},
+ { .input = &tegra_pll_u_480M, .value = 3},
+ { .input = &tegra_pll_c, .value = 4},
+ { .input = &tegra_pll_ref, .value = 7},
+ { 0, 0},
+};
+
/* Single clock source ("fake") muxes */
static struct clk_mux_sel mux_clk_m[] = {
{ .input = &tegra_clk_m, .value = 0},
{ 0, 0},
};
+/* xusb_hs has an alternative source, that is not used - therefore, xusb_hs
+ is modeled as a single source mux */
+static struct clk_mux_sel mux_pllu_60M[] = {
+ { .input = &tegra_pll_u_60M, .value = 1},
+ { 0, 0},
+};
+
static struct raw_notifier_head emc_rate_change_nh;
static struct clk tegra_clk_emc = {
.name = "emc",
.ops = &tegra_emc_clk_ops,
.reg = 0x19c,
- .max_rate = 800000000,
- .min_rate = 25000000,
+ .max_rate = 1066000000,
+ .min_rate = 12750000,
.inputs = mux_pllm_pllc_pllp_clkm,
- .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
+ .flags = MUX | MUX8 | DIV_U71 | PERIPH_EMC_ENB,
.u.periph = {
.clk_num = 57,
},
};
#ifdef CONFIG_TEGRA_DUAL_CBUS
+
+static struct raw_notifier_head c2bus_rate_change_nh;
+static struct raw_notifier_head c3bus_rate_change_nh;
+
static struct clk tegra_clk_c2bus = {
.name = "c2bus",
.parent = &tegra_pll_c2,
.ops = &tegra_clk_cbus_ops,
- .max_rate = 600000000,
+ .max_rate = 700000000,
.mul = 1,
.div = 1,
.flags = PERIPH_ON_CBUS,
.shared_bus_backup = {
.input = &tegra_pll_p,
- }
+ },
+ .rate_change_nh = &c2bus_rate_change_nh,
};
static struct clk tegra_clk_c3bus = {
.name = "c3bus",
.parent = &tegra_pll_c3,
.ops = &tegra_clk_cbus_ops,
- .max_rate = 600000000,
+ .max_rate = 700000000,
.mul = 1,
.div = 1,
.flags = PERIPH_ON_CBUS,
.shared_bus_backup = {
.input = &tegra_pll_p,
- }
+ },
+ .rate_change_nh = &c3bus_rate_change_nh,
};
+#ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
static DEFINE_MUTEX(cbus_mutex);
+#define CROSS_CBUS_MUTEX (&cbus_mutex)
+#else
+#define CROSS_CBUS_MUTEX NULL
+#endif
+
static struct clk_mux_sel mux_clk_cbus[] = {
{ .input = &tegra_clk_c2bus, .value = 0},
.dev_id = _dev, \
.con_id = _con, \
}, \
- .ops = &tegra_clk_shared_bus_ops, \
+ .ops = &tegra_clk_shared_bus_user_ops, \
.parent = _parent, \
.inputs = mux_clk_cbus, \
.flags = MUX, \
.client_div = _div, \
.mode = _mode, \
}, \
- .cross_clk_mutex = &cbus_mutex, \
+ .cross_clk_mutex = CROSS_CBUS_MUTEX, \
}
#else
+
+static struct raw_notifier_head cbus_rate_change_nh;
+
static struct clk tegra_clk_cbus = {
.name = "cbus",
.parent = &tegra_pll_c,
.ops = &tegra_clk_cbus_ops,
- .max_rate = 600000000,
+ .max_rate = 700000000,
.mul = 1,
.div = 2,
.flags = PERIPH_ON_CBUS,
.shared_bus_backup = {
.input = &tegra_pll_p,
- }
+ },
+ .rate_change_nh = &cbus_rate_change_nh,
};
#endif
.dev_id = _dev, \
.con_id = _con, \
}, \
- .ops = &tegra_clk_shared_bus_ops, \
+ .ops = &tegra_clk_shared_bus_user_ops, \
.parent = _parent, \
.u.shared_bus_user = { \
.client_id = _id, \
}, \
}
struct clk tegra_list_clks[] = {
- PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 26000000, mux_clk_m, 0),
+ PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
- PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 24576000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 24576000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 24576000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 24576000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 24576000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 24576000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 48000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
D_AUDIO_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
- D_AUDIO_CLK("dam0", "tegra30-dam.0", "dam.0", 108, 0x3d8, 48000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
- D_AUDIO_CLK("dam1", "tegra30-dam.1", "dam.1", 109, 0x3dc, 48000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
- D_AUDIO_CLK("dam2", "tegra30-dam.2", "dam.2", 110, 0x3e0, 48000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 108000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 108000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ D_AUDIO_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
+ D_AUDIO_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
+ D_AUDIO_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 19910000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 19910000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
- PERIPH_CLK("sbc1", "tegra11-spi.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc2", "tegra11-spi.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc3", "tegra11-spi.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc4", "tegra11-spi.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc5", "tegra11-spi.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc6", "tegra11-spi.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
+ PERIPH_CLK("sbc1", "spi-tegra114.0", NULL, 41, 0x134, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc2", "spi-tegra114.1", NULL, 44, 0x118, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc3", "spi-tegra114.2", NULL, 46, 0x11c, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc4", "spi-tegra114.3", NULL, 68, 0x1b4, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc5", "spi-tegra114.4", NULL, 104, 0x3c8, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc6", "spi-tegra114.5", NULL, 105, 0x3cc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB, &tegra_nand_clk_ops),
PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
+ PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 102000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
+ PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("trace", "trace", NULL, 77, 0x634, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 12000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2c1", "tegra11-i2c.0", "i2c-div", 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c2", "tegra11-i2c.1", "i2c-div", 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c3", "tegra11-i2c.2", "i2c-div", 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c4", "tegra11-i2c.3", "i2c-div", 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c5", "tegra11-i2c.4", "i2c-div", 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c1-fast", "tegra11-i2c.0", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c2-fast", "tegra11-i2c.1", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c3-fast", "tegra11-i2c.2", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c4-fast", "tegra11-i2c.3", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c5-fast", "tegra11-i2c.4", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
+ PERIPH_CLK("i2c1", "tegra11-i2c.0", "div-clk", 12, 0x124, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
+ PERIPH_CLK("i2c2", "tegra11-i2c.1", "div-clk", 54, 0x198, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
+ PERIPH_CLK("i2c3", "tegra11-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
+ PERIPH_CLK("i2c4", "tegra11-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
+ PERIPH_CLK("i2c5", "tegra11-i2c.4", "div-clk", 47, 0x128, 64000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
+ PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, 0),
PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartd", "tegra_uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
- PERIPH_CLK("uarta_dbg", "serial8250.0", "uarta",6, 0x178, 800000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
- PERIPH_CLK("uartb_dbg", "serial8250.0", "uartb",7, 0x17c, 800000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
- PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc",55, 0x1a0, 800000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
- PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd",65, 0x1c0, 800000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
- PERIPH_CLK("uarte_dbg", "serial8250.0", "uarte",66, 0x1c4, 800000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
- PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
- PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
- PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
- PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
+ PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
+ PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
+ PERIPH_CLK_EX("vi", "vi", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
+ PERIPH_CLK("vi_sensor", "vi", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
+ PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
PERIPH_CLK("msenc", "msenc", NULL, 60, 0x170, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
#else
- PERIPH_CLK("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
+ PERIPH_CLK_EX("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops),
#endif
PERIPH_CLK("tsec", "tsec", NULL, 83, 0x1f4, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
- PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 300000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
+ PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 384000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops),
- PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
+ PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 297000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
PERIPH_CLK("usbd", "tegra-udc.0", NULL, 22, 0, 480000000, mux_clk_m, 0),
PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0x4b8, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops),
PERIPH_CLK("dsi1-fixed", "tegradc.0", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
PERIPH_CLK("dsi2-fixed", "tegradc.1", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
- PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
- PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
- PERIPH_CLK("cilab", "tegra_camera", "cilab", 144, 0x614, 200000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
- PERIPH_CLK("cilcd", "tegra_camera", "cilcd", 145, 0x618, 200000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
- PERIPH_CLK("cile", "tegra_camera", "cile", 146, 0x61c, 200000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
- PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 100000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
- PERIPH_CLK("dsiblp", "tegradc.1", "dsiblp", 148, 0x624, 100000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
-
- PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("csi", "vi", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
+ PERIPH_CLK("isp", "vi", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
+ PERIPH_CLK("csus", "vi", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
+ PERIPH_CLK("cilab", "vi", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+ PERIPH_CLK("cilcd", "vi", "cilcd", 145, 0x618, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+ PERIPH_CLK("cile", "vi", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+ PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+ PERIPH_CLK("dsiblp", "tegradc.1", "dsiblp", 148, 0x624, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+
+ PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 12000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("se", "se", NULL, 127, 0x42c, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
- PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 108000000, mux_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs", "ref", 155, 0x62c, 54000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
- PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs", "soc", 155, 0x630, 54000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
+ PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 102000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT),
+ PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs", "ref", 155, 0x62c, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
+ PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs", "soc", 155, 0x630, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
PERIPH_CLK("soc_therm", "soc_therm", NULL, 78, 0x644, 136000000, mux_pllm_pllc_pllp_plla, MUX | MUX8 | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("dds", "dds", NULL, 150, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
+ PERIPH_CLK("dp2", "dp2", NULL, 152, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
+
SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_CLK("camera.sclk", "vi", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("cap.throttle.sclk", "cap_throttle", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
SHARED_CLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_CLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
SHARED_CLK("sbc1.sclk", "tegra11-spi.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("sbc2.sclk", "tegra11-spi.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("sbc3.sclk", "tegra11-spi.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0),
SHARED_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0),
SHARED_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("cap.throttle.emc", "cap_throttle", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
SHARED_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc, NULL, 0, 0),
SHARED_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, 0),
+ SHARED_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
SHARED_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0),
+ SHARED_CLK("sdmmc4.emc", "sdhci-tegra.3", "emc", &tegra_clk_emc, NULL, 0, 0),
+ SHARED_CLK("camera.emc", "vi", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
+ SHARED_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
SHARED_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0),
+ SHARED_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE),
+ SHARED_CLK("edp.emc", "edp.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("battery.emc", "battery_edp", "emc", &tegra_clk_emc, NULL, 0, SHARED_CEILING),
#ifdef CONFIG_TEGRA_DUAL_CBUS
DUAL_CBUS_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_c2bus, "3d", 0, 0),
DUAL_CBUS_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_c2bus, "2d", 0, 0),
+ DUAL_CBUS_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_c2bus, "epp", 0, 0),
SHARED_CLK("cap.c2bus", "cap.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("cap.throttle.c2bus", "cap_throttle", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
SHARED_CLK("floor.c2bus", "floor.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0),
+ SHARED_CLK("override.c2bus", "override.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_OVERRIDE),
+ SHARED_CLK("edp.c2bus", "edp.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("battery.c2bus", "battery_edp", "gpu", &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("cap.profile.c2bus", "profile.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
- DUAL_CBUS_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_c3bus, "epp", 0, 0),
DUAL_CBUS_CLK("msenc.cbus", "tegra_msenc", "msenc", &tegra_clk_c3bus, "msenc", 0, 0),
DUAL_CBUS_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_c3bus, "tsec", 0, 0),
DUAL_CBUS_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_c3bus, "vde", 0, 0),
DUAL_CBUS_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_c3bus, "se", 0, 0),
SHARED_CLK("cap.c3bus", "cap.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("cap.throttle.c3bus", "cap_throttle", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
SHARED_CLK("floor.c3bus", "floor.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, 0),
+ SHARED_CLK("override.c3bus", "override.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_OVERRIDE),
#else
SHARED_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_cbus, "3d", 0, 0),
SHARED_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_cbus, "2d", 0, 0),
SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0),
SHARED_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_cbus, "se", 0, 0),
SHARED_CLK("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("cap.throttle.cbus", "cap_throttle", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
SHARED_CLK("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0),
+ SHARED_CLK("override.cbus", "override.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_OVERRIDE),
+ SHARED_CLK("edp.cbus", "edp.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("battery.cbus", "battery_edp", "gpu", &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("cap.profile.cbus", "profile.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
#endif
};
+
+/* XUSB clocks */
+#define XUSB_ID "tegra-xhci"
+
+static struct clk tegra_xusb_source_clks[] = {
+ PERIPH_CLK("xusb_host_src", XUSB_ID, "host_src", 143, 0x600, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
+ PERIPH_CLK("xusb_falcon_src", XUSB_ID, "falcon_src", 143, 0x604, 350000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
+ PERIPH_CLK("xusb_fs_src", XUSB_ID, "fs_src", 143, 0x608, 48000000, mux_clkm_48M_pllp_480M, MUX | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
+ PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 120000000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
+ PERIPH_CLK("xusb_dev_src", XUSB_ID, "dev_src", 95, 0x60c, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
+ {
+ .name = "xusb_hs_src",
+ .lookup = {
+ .dev_id = XUSB_ID,
+ .con_id = "hs_src",
+ },
+ .ops = &tegra_periph_clk_ops,
+ .reg = 0x610,
+ .inputs = mux_pllu_60M,
+ .flags = PLLU | PERIPH_NO_ENB,
+ .max_rate = 60000000,
+ .u.periph = {
+ .src_mask = 0x1 << 25,
+ .src_shift = 25,
+ },
+ },
+ SHARED_CLK("xusb.emc", "XUSB_ID", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
+};
+
+static struct clk_mux_sel mux_xusb_host[] = {
+ { .input = &tegra_xusb_source_clks[0], .value = 0},
+ { .input = &tegra_xusb_source_clks[1], .value = 1},
+ { .input = &tegra_xusb_source_clks[2], .value = 2},
+ { .input = &tegra_xusb_source_clks[5], .value = 5},
+ { 0, 0},
+};
+
+static struct clk_mux_sel mux_xusb_ss[] = {
+ { .input = &tegra_xusb_source_clks[3], .value = 3},
+ { .input = &tegra_xusb_source_clks[0], .value = 0},
+ { .input = &tegra_xusb_source_clks[1], .value = 1},
+ { 0, 0},
+};
+
+static struct clk_mux_sel mux_xusb_dev[] = {
+ { .input = &tegra_xusb_source_clks[4], .value = 4},
+ { .input = &tegra_xusb_source_clks[2], .value = 2},
+ { .input = &tegra_xusb_source_clks[3], .value = 3},
+ { 0, 0},
+};
+
+static struct clk tegra_xusb_coupled_clks[] = {
+ PERIPH_CLK_EX("xusb_host", XUSB_ID, "host", 89, 0, 350000000, mux_xusb_host, 0, &tegra_clk_coupled_gate_ops),
+ PERIPH_CLK_EX("xusb_ss", XUSB_ID, "ss", 156, 0, 350000000, mux_xusb_ss, 0, &tegra_clk_coupled_gate_ops),
+ PERIPH_CLK_EX("xusb_dev", XUSB_ID, "dev", 95, 0, 120000000, mux_xusb_dev, 0, &tegra_clk_coupled_gate_ops),
+};
+
+
#define CLK_DUPLICATE(_name, _dev, _con) \
{ \
.name = _name, \
* table under two names.
*/
struct clk_duplicate tegra_clk_duplicates[] = {
+ CLK_DUPLICATE("uarta", "serial8250.0", NULL),
+ CLK_DUPLICATE("uartb", "serial8250.1", NULL),
+ CLK_DUPLICATE("uartc", "serial8250.2", NULL),
+ CLK_DUPLICATE("uartd", "serial8250.3", NULL),
+ CLK_DUPLICATE("uarte", "serial8250.4", NULL),
+ CLK_DUPLICATE("usbd", XUSB_ID, "utmip-pad"),
CLK_DUPLICATE("usbd", "utmip-pad", NULL),
CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
CLK_DUPLICATE("usbd", "tegra-otg", NULL),
CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.1", "dsia"),
CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.0", "dsialp"),
CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.1", "dsialp"),
- CLK_DUPLICATE("dsi1_fixed", "tegra_dc_dsi_vs1.0", "dsi_fixed"),
- CLK_DUPLICATE("dsi1_fixed", "tegra_dc_dsi_vs1.1", "dsi_fixed"),
- CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
- CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
- CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
- CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
+ CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.0", "dsi-fixed"),
+ CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.1", "dsi-fixed"),
CLK_DUPLICATE("cop", "tegra-avp", "cop"),
CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
CLK_DUPLICATE("cop", "nvavp", "cop"),
CLK_DUPLICATE("vde", "tegra-aes", "vde"),
CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
CLK_DUPLICATE("bsea", "nvavp", "bsea"),
- CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
- CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
+ CLK_DUPLICATE("clk_m", NULL, "apb_pclk"),
CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
+ CLK_DUPLICATE("cl_dvfs_soc", "tegra11-i2c.4", NULL),
+ CLK_DUPLICATE("cl_dvfs_ref", "tegra11-i2c.4", NULL),
CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL),
CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL),
CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL),
CLK_DUPLICATE("avp.emc", "nvavp", "emc"),
CLK_DUPLICATE("vde.cbus", "nvavp", "vde"),
CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
+ CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
CLK_DUPLICATE("host1x", "tegra_host1x", "host1x"),
-
+ CLK_DUPLICATE("epp.cbus", "tegra_isp", "epp"),
};
struct clk *tegra_ptr_clks[] = {
&tegra_pll_u_480M,
&tegra_pll_u_60M,
&tegra_pll_u_48M,
+ &tegra_pll_u_12M,
&tegra_pll_x,
&tegra_pll_x_out0,
&tegra_dfll_cpu,
&tegra_pll_re_vco,
&tegra_pll_re_out,
&tegra_pll_e,
- &tegra_cml0_clk,
- &tegra_cml1_clk,
&tegra_pciex_clk,
&tegra_clk_cclk_g,
&tegra_clk_cclk_lp,
clkdev_add(&c->lookup);
}
-bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
+/* Direct access to CPU clock sources fot CPU idle driver */
+int tegra11_cpu_g_idle_rate_exchange(unsigned long *rate)
{
- /* No policy limitations for now */
- return true;
+ int ret = 0;
+ struct clk *dfll = tegra_clk_cpu_cmplx.parent->u.cpu.dynamic;
+ unsigned long old_rate, new_rate, flags;
+
+ if (!dfll || !tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail))
+ return -EPERM;
+
+ /* Clipping min to oscillator rate is pretty much arbitrary */
+ new_rate = max(*rate, tegra_clk_m.rate);
+
+ clk_lock_save(dfll, &flags);
+
+ old_rate = clk_get_rate_locked(dfll);
+ *rate = old_rate;
+ if (new_rate != old_rate)
+ ret = clk_set_rate_locked(dfll, new_rate);
+
+ clk_unlock_restore(dfll, &flags);
+ return ret;
}
-void __init tegra11x_init_clocks(void)
+int tegra11_cpu_lp_idle_rate_exchange(unsigned long *rate)
{
- int i;
- struct clk *c;
+ int ret = 0;
+ struct clk *backup = tegra_clk_cpu_cmplx.parent->u.cpu.backup;
+ unsigned long old_rate, flags;
+ unsigned long new_rate = min(
+ *rate, tegra_clk_cpu_cmplx.parent->u.cpu.backup_rate);
- for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
- tegra11_init_one_clock(tegra_ptr_clks[i]);
+ clk_lock_save(backup, &flags);
- for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
- tegra11_init_one_clock(&tegra_list_clks[i]);
+ old_rate = clk_get_rate_locked(backup);
+ *rate = old_rate;
+ if (new_rate != old_rate)
+ ret = clk_set_rate_locked(backup, new_rate);
- for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
- c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
- if (!c) {
- pr_err("%s: Unknown duplicate clock %s\n", __func__,
- tegra_clk_duplicates[i].name);
- continue;
- }
+ clk_unlock_restore(backup, &flags);
+ return ret;
+}
- tegra_clk_duplicates[i].lookup.clk = c;
- clkdev_add(&tegra_clk_duplicates[i].lookup);
+void tegra_edp_throttle_cpu_now(u8 factor)
+{
+ /* empty definition for tegra11 */
+ return;
+}
+
+bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
+{
+ /*
+ * Most of the Tegra11 multimedia and peripheral muxes include pll_c2
+ * and pll_c3 as possible inputs. However, per clock policy these plls
+ * are allowed to be used only by handful devices aggregated on cbus.
+ * For all others, instead of enforcing policy at run-time in this
+ * function, we simply stripped out pll_c2 and pll_c3 options from the
+ * respective muxes statically.
+ */
+
+ /*
+ * In configuration with dual cbus pll_c can be used as a scaled clock
+ * source for EMC only when pll_m is fixed, or as a general fixed rate
+ * clock source for EMC and other peripherals if pll_m is scaled. In
+ * configuration with single cbus pll_c can be used as a scaled cbus
+ * clock source only. No direct use for pll_c by super clocks.
+ */
+ if ((p == &tegra_pll_c) && (c != &tegra_pll_c_out1)) {
+ if (c->ops == &tegra_super_ops)
+ return false;
+#ifdef CONFIG_TEGRA_DUAL_CBUS
+#ifndef CONFIG_TEGRA_PLLM_SCALED
+ return c->flags & PERIPH_EMC_ENB;
+#endif
+#else
+ return c->flags & PERIPH_ON_CBUS;
+#endif
}
- for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
- tegra11_init_one_clock(&tegra_sync_source_list[i]);
- for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
- tegra11_init_one_clock(&tegra_clk_audio_list[i]);
- for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
- tegra11_init_one_clock(&tegra_clk_audio_2x_list[i]);
+ /*
+ * In any configuration pll_m must not be used as a clock source for
+ * cbus modules. If pll_m is scaled it can be used as EMC source only.
+ * Otherwise fixed rate pll_m can be used as clock source for EMC and
+ * other peripherals. No direct use for pll_m by super clocks.
+ */
+ if ((p == &tegra_pll_m) && (c != &tegra_pll_m_out1)) {
+ if (c->ops == &tegra_super_ops)
+ return false;
+
+ if (c->flags & PERIPH_ON_CBUS)
+ return false;
+#ifdef CONFIG_TEGRA_PLLM_SCALED
+ return c->flags & PERIPH_EMC_ENB;
+#endif
+ }
+ return true;
+}
- init_clk_out_mux();
- for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
- tegra11_init_one_clock(&tegra_clk_out_list[i]);
+/* Internal LA may request some clocks to be enabled on init via TRANSACTION
+ SCRATCH register settings */
+void __init tegra11x_clk_init_la(void)
+{
+ struct clk *c;
+ u32 reg = readl(misc_gp_base + MISC_GP_TRANSACTOR_SCRATCH_0);
- /* Initialize to default */
- tegra_init_cpu_edp_limits(0);
+ if (!(reg & MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE))
+ return;
+
+ c = tegra_get_clock_by_name("la");
+ if (WARN(!c, "%s: could not find la clk\n", __func__))
+ return;
+ clk_enable(c);
+
+ if (reg & MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE) {
+ c = tegra_get_clock_by_name("dds");
+ if (WARN(!c, "%s: could not find la clk\n", __func__))
+ return;
+ clk_enable(c);
+ }
+ if (reg & MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE) {
+ c = tegra_get_clock_by_name("dp2");
+ if (WARN(!c, "%s: could not find la clk\n", __func__))
+ return;
+ clk_enable(c);
+
+ c = tegra_get_clock_by_name("hdmi");
+ if (WARN(!c, "%s: could not find la clk\n", __func__))
+ return;
+ clk_enable(c);
+ }
}
#ifdef CONFIG_CPU_FREQ
* Frequency table index must be sequential starting at 0 and frequencies
* must be ascending.
*/
+#define CPU_FREQ_STEP 102000 /* 102MHz cpu_g table step */
+#define CPU_FREQ_TABLE_MAX_SIZE (2 * MAX_DVFS_FREQS + 1)
-static struct cpufreq_frequency_table freq_table_300MHz[] = {
- { 0, 204000 },
- { 1, 300000 },
- { 2, CPUFREQ_TABLE_END },
-};
-
-static struct cpufreq_frequency_table freq_table_1p0GHz[] = {
- { 0, 102000 },
- { 1, 204000 },
- { 2, 312000 },
- { 3, 456000 },
- { 4, 608000 },
- { 5, 760000 },
- { 6, 816000 },
- { 7, 912000 },
- { 8, 1000000 },
- { 9, CPUFREQ_TABLE_END },
-};
-
-static struct cpufreq_frequency_table freq_table_1p3GHz[] = {
- { 0, 102000 },
- { 1, 204000 },
- { 2, 340000 },
- { 3, 475000 },
- { 4, 640000 },
- { 5, 760000 },
- { 6, 880000 },
- { 7, 1000000 },
- { 8, 1100000 },
- { 9, 1200000 },
- {10, 1300000 },
- {11, CPUFREQ_TABLE_END },
-};
-
-static struct cpufreq_frequency_table freq_table_1p4GHz[] = {
- { 0, 102000 },
- { 1, 204000 },
- { 2, 370000 },
- { 3, 475000 },
- { 4, 620000 },
- { 5, 760000 },
- { 6, 880000 },
- { 7, 1000000 },
- { 8, 1100000 },
- { 9, 1200000 },
- {10, 1300000 },
- {11, 1400000 },
- {12, CPUFREQ_TABLE_END },
-};
-
-static struct tegra_cpufreq_table_data cpufreq_tables[] = {
- { freq_table_300MHz, 0, 1 },
- { freq_table_1p0GHz, 2, 7, 2},
- { freq_table_1p3GHz, 2, 9, 2},
- { freq_table_1p4GHz, 2, 10, 2},
-};
-
-static int clip_cpu_rate_limits(
- struct cpufreq_frequency_table *freq_table,
- struct cpufreq_policy *policy,
- struct clk *cpu_clk_g,
- struct clk *cpu_clk_lp)
-{
- int idx, ret;
-
- /* clip CPU G mode maximum frequency to table entry */
- ret = cpufreq_frequency_table_target(policy, freq_table,
- cpu_clk_g->max_rate / 1000, CPUFREQ_RELATION_H, &idx);
- if (ret) {
- pr_err("%s: G CPU max rate %lu outside of cpufreq table",
- __func__, cpu_clk_g->max_rate);
- return ret;
- }
- cpu_clk_g->max_rate = freq_table[idx].frequency * 1000;
- if (cpu_clk_g->max_rate < cpu_clk_lp->max_rate) {
- pr_err("%s: G CPU max rate %lu is below LP CPU max rate %lu",
- __func__, cpu_clk_g->max_rate, cpu_clk_lp->max_rate);
- return -EINVAL;
- }
-
- /* clip CPU LP mode maximum frequency to table entry, and
- set CPU G mode minimum frequency one table step below */
- ret = cpufreq_frequency_table_target(policy, freq_table,
- cpu_clk_lp->max_rate / 1000, CPUFREQ_RELATION_H, &idx);
- if (ret || !idx) {
- pr_err("%s: LP CPU max rate %lu %s of cpufreq table", __func__,
- cpu_clk_lp->max_rate, ret ? "outside" : "at the bottom");
- return ret;
- }
- cpu_clk_lp->max_rate = freq_table[idx].frequency * 1000;
- cpu_clk_g->min_rate = freq_table[idx-1].frequency * 1000;
- return 0;
-}
+static struct cpufreq_frequency_table freq_table[CPU_FREQ_TABLE_MAX_SIZE];
+static struct tegra_cpufreq_table_data freq_table_data;
struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void)
{
- int i, ret;
- unsigned long selection_rate;
+ int i, j;
+ bool g_vmin_done = false;
+ unsigned int freq, lp_backup_freq, g_vmin_freq, g_start_freq, max_freq;
struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g");
struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp");
- /* For table selection use top cpu_g rate in dvfs ladder; selection
- rate may exceed cpu max_rate (e.g., because of edp limitations on
- cpu voltage) - in any case max_rate will be clipped to the table */
- if (cpu_clk_g->dvfs && cpu_clk_g->dvfs->num_freqs)
- selection_rate =
- cpu_clk_g->dvfs->freqs[cpu_clk_g->dvfs->num_freqs - 1];
- else
- selection_rate = cpu_clk_g->max_rate;
-
- for (i = 0; i < ARRAY_SIZE(cpufreq_tables); i++) {
- struct cpufreq_policy policy;
- policy.cpu = 0; /* any on-line cpu */
- ret = cpufreq_frequency_table_cpuinfo(
- &policy, cpufreq_tables[i].freq_table);
- if (!ret) {
- if ((policy.max * 1000) == selection_rate) {
- ret = clip_cpu_rate_limits(
- cpufreq_tables[i].freq_table,
- &policy, cpu_clk_g, cpu_clk_lp);
- if (!ret)
- return &cpufreq_tables[i];
- }
+ /* Initialize once */
+ if (freq_table_data.freq_table)
+ return &freq_table_data;
+
+ /* Clean table */
+ for (i = 0; i < CPU_FREQ_TABLE_MAX_SIZE; i++) {
+ freq_table[i].index = i;
+ freq_table[i].frequency = CPUFREQ_TABLE_END;
+ }
+
+ lp_backup_freq = cpu_clk_lp->u.cpu.backup_rate / 1000;
+ if (!lp_backup_freq) {
+ WARN(1, "%s: cannot make cpufreq table: no LP CPU backup rate\n",
+ __func__);
+ return NULL;
+ }
+ if (!cpu_clk_lp->dvfs) {
+ WARN(1, "%s: cannot make cpufreq table: no LP CPU dvfs\n",
+ __func__);
+ return NULL;
+ }
+ if (!cpu_clk_g->dvfs) {
+ WARN(1, "%s: cannot make cpufreq table: no G CPU dvfs\n",
+ __func__);
+ return NULL;
+ }
+ g_vmin_freq = cpu_clk_g->dvfs->freqs[0] / 1000;
+ if (g_vmin_freq <= lp_backup_freq) {
+ WARN(1, "%s: cannot make cpufreq table: LP CPU backup rate"
+ " exceeds G CPU rate at Vmin\n", __func__);
+ return NULL;
+ }
+
+ /* Start with backup frequencies */
+ i = 0;
+ freq = lp_backup_freq;
+ freq_table[i++].frequency = freq/4;
+ freq_table[i++].frequency = freq/2;
+ freq_table[i++].frequency = freq;
+
+ /* Throttle low index at backup level*/
+ freq_table_data.throttle_lowest_index = i - 1;
+
+ /*
+ * Next, set table steps along LP CPU dvfs ladder, but make sure G CPU
+ * dvfs rate at minimum voltage is not missed (if it happens to be below
+ * LP maximum rate)
+ */
+ max_freq = cpu_clk_lp->max_rate / 1000;
+ for (j = 0; j < cpu_clk_lp->dvfs->num_freqs; j++) {
+ freq = cpu_clk_lp->dvfs->freqs[j] / 1000;
+ if (freq <= lp_backup_freq)
+ continue;
+
+ if (!g_vmin_done && (freq >= g_vmin_freq)) {
+ g_vmin_done = true;
+ if (freq > g_vmin_freq)
+ freq_table[i++].frequency = g_vmin_freq;
}
+ freq_table[i++].frequency = freq;
+
+ if (freq == max_freq)
+ break;
}
- WARN(1, "%s: No cpufreq table matching G & LP cpu ranges", __func__);
- return NULL;
+
+ /* Set G CPU min rate at least one table step below LP maximum */
+ cpu_clk_g->min_rate = min(freq_table[i-2].frequency, g_vmin_freq)*1000;
+
+ /* Suspend index at max LP CPU */
+ freq_table_data.suspend_index = i - 1;
+
+ /* Fill in "hole" (if any) between LP CPU maximum rate and G CPU dvfs
+ ladder rate at minimum voltage */
+ if (freq < g_vmin_freq) {
+ int n = (g_vmin_freq - freq) / CPU_FREQ_STEP;
+ for (j = 0; j <= n; j++) {
+ freq = g_vmin_freq - CPU_FREQ_STEP * (n - j);
+ freq_table[i++].frequency = freq;
+ }
+ }
+
+ /* Now, step along the rest of G CPU dvfs ladder */
+ g_start_freq = freq;
+ max_freq = cpu_clk_g->max_rate / 1000;
+ for (j = 0; j < cpu_clk_g->dvfs->num_freqs; j++) {
+ freq = cpu_clk_g->dvfs->freqs[j] / 1000;
+ if (freq > g_start_freq)
+ freq_table[i++].frequency = freq;
+ if (freq == max_freq)
+ break;
+ }
+
+ /* Throttle high index one step below maximum */
+ BUG_ON(i >= CPU_FREQ_TABLE_MAX_SIZE);
+ freq_table_data.throttle_highest_index = i - 2;
+ freq_table_data.freq_table = freq_table;
+ return &freq_table_data;
}
unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate)
/* Vote on memory bus frequency based on cpu frequency;
cpu rate is in kHz, emc rate is in Hz */
- if (cpu_rate >= 750000)
- return emc_max_rate; /* cpu >= 750 MHz, emc max */
- else if (cpu_rate >= 450000)
- return emc_max_rate/2; /* cpu >= 500 MHz, emc max/2 */
- else if (cpu_rate >= 250000)
- return 100000000; /* cpu >= 250 MHz, emc 100 MHz */
+ if (cpu_rate >= 1300000)
+ return emc_max_rate; /* cpu >= 1.3GHz, emc max */
+ else if (cpu_rate >= 975000)
+ return 400000000; /* cpu >= 975 MHz, emc 400 MHz */
+ else if (cpu_rate >= 725000)
+ return 200000000; /* cpu >= 725 MHz, emc 200 MHz */
+ else if (cpu_rate >= 500000)
+ return 100000000; /* cpu >= 500 MHz, emc 100 MHz */
+ else if (cpu_rate >= 275000)
+ return 50000000; /* cpu >= 275 MHz, emc 50 MHz */
else
return 0; /* emc min */
}
+
+int tegra_update_mselect_rate(unsigned long cpu_rate)
+{
+ static struct clk *mselect = NULL;
+
+ unsigned long mselect_rate;
+
+ if (!mselect) {
+ mselect = tegra_get_clock_by_name("mselect");
+ if (!mselect)
+ return -ENODEV;
+ }
+
+ /* Vote on mselect frequency based on cpu frequency:
+ keep mselect at half of cpu rate up to 102 MHz;
+ cpu rate is in kHz, mselect rate is in Hz */
+ mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000;
+ mselect_rate = min(mselect_rate, 102000000UL);
+
+ if (mselect_rate != clk_get_rate(mselect))
+ return clk_set_rate(mselect, mselect_rate);
+
+ return 0;
+}
#endif
#ifdef CONFIG_PM_SLEEP
static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
- PERIPH_CLK_SOURCE_NUM + 22];
+ PERIPH_CLK_SOURCE_NUM + 25];
-void tegra_clk_suspend(void)
+static int tegra11_clk_suspend(void)
{
unsigned long off;
u32 *ctx = clk_rst_suspend;
*ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
*ctx++ = clk_readl(CPU_SOFTRST_CTRL);
- *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
- *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
+ *ctx++ = clk_readl(CPU_SOFTRST_CTRL1);
+ *ctx++ = clk_readl(CPU_SOFTRST_CTRL2);
+
+ *ctx++ = clk_readl(tegra_pll_p_out1.reg);
+ *ctx++ = clk_readl(tegra_pll_p_out3.reg);
+
*ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
*ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
*ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
*ctx++ = clk_readl(tegra_pll_a_out0.reg);
*ctx++ = clk_readl(tegra_pll_c_out1.reg);
- *ctx++ = clk_readl(tegra_clk_cclk_g.reg);
- *ctx++ = clk_readl(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
*ctx++ = clk_readl(tegra_clk_cclk_lp.reg);
*ctx++ = clk_readl(tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) {
*ctx++ = clk_readl(off);
}
- for (off = PERIPH_CLK_SOURCE_XUSB; off <= PERIPH_CLK_SOURCE_DDS_UART;
- off += 4) {
+ for (off = PERIPH_CLK_SOURCE_XUSB_HOST;
+ off <= PERIPH_CLK_SOURCE_SOC_THERM; off += 4)
*ctx++ = clk_readl(off);
- }
*ctx++ = clk_readl(RST_DEVICES_L);
*ctx++ = clk_readl(RST_DEVICES_H);
*ctx++ = clk_readl(RST_DEVICES_U);
*ctx++ = clk_readl(RST_DEVICES_V);
*ctx++ = clk_readl(RST_DEVICES_W);
+ *ctx++ = clk_readl(RST_DEVICES_X);
*ctx++ = clk_readl(CLK_OUT_ENB_L);
*ctx++ = clk_readl(CLK_OUT_ENB_H);
*ctx++ = clk_readl(CLK_OUT_ENB_U);
*ctx++ = clk_readl(CLK_OUT_ENB_V);
*ctx++ = clk_readl(CLK_OUT_ENB_W);
+ *ctx++ = clk_readl(CLK_OUT_ENB_X);
+ *ctx++ = clk_readl(tegra_clk_cclk_g.reg);
+ *ctx++ = clk_readl(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
+
+ *ctx++ = clk_readl(SPARE_REG);
*ctx++ = clk_readl(MISC_CLK_ENB);
*ctx++ = clk_readl(CLK_MASK_ARM);
+
+ return 0;
}
-void tegra_clk_resume(void)
+static void tegra11_clk_resume(void)
{
unsigned long off;
const u32 *ctx = clk_rst_suspend;
u32 val;
- u32 pllc_base;
u32 plla_base;
u32 plld_base;
u32 plld2_base;
+ u32 pll_p_out12, pll_p_out34;
+ u32 pll_a_out0, pll_m_out1, pll_c_out1;
struct clk *p;
+ /* FIXME: OSC_CTRL already restored by warm boot code? */
val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
val |= *ctx++;
clk_writel(val, OSC_CTRL);
clk_writel(*ctx++, CPU_SOFTRST_CTRL);
-
- /* Since we are going to reset devices in this function, pllc/a is
- * required to be enabled. The actual value will be restore back later.
+ clk_writel(*ctx++, CPU_SOFTRST_CTRL1);
+ clk_writel(*ctx++, CPU_SOFTRST_CTRL2);
+
+ /* FIXME: DFLL? */
+ /* Since we are going to reset devices and switch clock sources in this
+ * function, plls and secondary dividers is required to be enabled. The
+ * actual value will be restored back later. Note that boot plls: pllm,
+ * pllp, and pllu are already configured and enabled
*/
- pllc_base = *ctx++;
- clk_writel(pllc_base | PLL_BASE_ENABLE, tegra_pll_c.reg + PLL_BASE);
- clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
+ val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
+ val |= val << 16;
+ pll_p_out12 = *ctx++;
+ clk_writel(pll_p_out12 | val, tegra_pll_p_out1.reg);
+ pll_p_out34 = *ctx++;
+ clk_writel(pll_p_out34 | val, tegra_pll_p_out3.reg);
+
+ tegra11_pllcx_clk_resume_enable(&tegra_pll_c2);
+ tegra11_pllcx_clk_resume_enable(&tegra_pll_c3);
+ tegra11_pllxc_clk_resume_enable(&tegra_pll_c);
+ tegra11_pllxc_clk_resume_enable(&tegra_pll_x);
+ tegra11_pllre_clk_resume_enable(&tegra_pll_re_out);
plla_base = *ctx++;
- clk_writel(plla_base | PLL_BASE_ENABLE, tegra_pll_a.reg + PLL_BASE);
clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
+ clk_writel(plla_base | PLL_BASE_ENABLE, tegra_pll_a.reg + PLL_BASE);
plld_base = *ctx++;
- clk_writel(plld_base | PLL_BASE_ENABLE, tegra_pll_d.reg + PLL_BASE);
clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
+ clk_writel(plld_base | PLL_BASE_ENABLE, tegra_pll_d.reg + PLL_BASE);
plld2_base = *ctx++;
- clk_writel(plld2_base | PLL_BASE_ENABLE, tegra_pll_d2.reg + PLL_BASE);
clk_writel(*ctx++, tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2));
+ clk_writel(plld2_base | PLL_BASE_ENABLE, tegra_pll_d2.reg + PLL_BASE);
udelay(1000);
- clk_writel(*ctx++, tegra_pll_m_out1.reg);
- clk_writel(*ctx++, tegra_pll_a_out0.reg);
- clk_writel(*ctx++, tegra_pll_c_out1.reg);
+ val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
+ pll_m_out1 = *ctx++;
+ clk_writel(pll_m_out1 | val, tegra_pll_m_out1.reg);
+ pll_a_out0 = *ctx++;
+ clk_writel(pll_a_out0 | val, tegra_pll_a_out0.reg);
+ pll_c_out1 = *ctx++;
+ clk_writel(pll_c_out1 | val, tegra_pll_c_out1.reg);
- clk_writel(*ctx++, tegra_clk_cclk_g.reg);
- clk_writel(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
- clk_writel(*ctx++, tegra_clk_cclk_lp.reg);
+ val = *ctx++;
+ tegra11_super_clk_resume(&tegra_clk_cclk_lp,
+ tegra_clk_virtual_cpu_lp.u.cpu.backup, val);
clk_writel(*ctx++, tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
clk_writel(*ctx++, tegra_clk_sclk.reg);
/* enable all clocks before configuring clock sources */
clk_writel(0xfdfffff1ul, CLK_OUT_ENB_L);
- clk_writel(0xfefff7f7ul, CLK_OUT_ENB_H);
- clk_writel(0x75f79bfful, CLK_OUT_ENB_U);
+ clk_writel(0xffddfff7ul, CLK_OUT_ENB_H);
+ clk_writel(0xfbfffbfeul, CLK_OUT_ENB_U);
clk_writel(0xfffffffful, CLK_OUT_ENB_V);
- clk_writel(0x00003ffful, CLK_OUT_ENB_W);
+ clk_writel(0xff7ffffful, CLK_OUT_ENB_W);
wmb();
for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) {
clk_writel(*ctx++, off);
}
- for (off = PERIPH_CLK_SOURCE_XUSB; off <= PERIPH_CLK_SOURCE_DDS_UART;
- off += 4) {
+ for (off = PERIPH_CLK_SOURCE_XUSB_HOST;
+ off <= PERIPH_CLK_SOURCE_SOC_THERM; off += 4)
clk_writel(*ctx++, off);
- }
+
clk_writel(*ctx++, RST_DEVICES_L);
clk_writel(*ctx++, RST_DEVICES_H);
clk_writel(*ctx++, RST_DEVICES_U);
-
- /* For LP0 resume, don't reset lpcpu, since we are running from it */
- val = *ctx++;
- val &= ~RST_DEVICES_V_SWR_CPULP_RST_DIS;
- clk_writel(val, RST_DEVICES_V);
-
+ clk_writel(*ctx++, RST_DEVICES_V);
clk_writel(*ctx++, RST_DEVICES_W);
+ clk_writel(*ctx++, RST_DEVICES_X);
wmb();
clk_writel(*ctx++, CLK_OUT_ENB_L);
clk_writel(*ctx++, CLK_OUT_ENB_U);
/* For LP0 resume, clk to lpcpu is required to be on */
+ /* FIXME: should be saved as on? */
val = *ctx++;
val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN;
clk_writel(val, CLK_OUT_ENB_V);
clk_writel(*ctx++, CLK_OUT_ENB_W);
+ clk_writel(*ctx++, CLK_OUT_ENB_X);
wmb();
+ /* DFLL resume after cl_dvfs and i2c5 clocks are resumed */
+ tegra11_dfll_clk_resume(&tegra_dfll_cpu);
+
+ /* CPU G clock restored after DFLL and PLLs */
+ clk_writel(*ctx++, tegra_clk_cclk_g.reg);
+ clk_writel(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
+
+ clk_writel(*ctx++, SPARE_REG);
clk_writel(*ctx++, MISC_CLK_ENB);
clk_writel(*ctx++, CLK_MASK_ARM);
- /* Restore back the actual pllc/a value */
- /* FIXME: need to root cause why pllc is required to be on
- * clk_writel(pllc_base, tegra_pll_c.reg + PLL_BASE);
- */
+ /* Restore back the actual pll and secondary divider values */
+ clk_writel(pll_p_out12, tegra_pll_p_out1.reg);
+ clk_writel(pll_p_out34, tegra_pll_p_out3.reg);
+
+ p = &tegra_pll_c2;
+ if (p->state == OFF)
+ tegra11_pllcx_clk_disable(p);
+ p = &tegra_pll_c3;
+ if (p->state == OFF)
+ tegra11_pllcx_clk_disable(p);
+ p = &tegra_pll_c;
+ if (p->state == OFF)
+ tegra11_pllxc_clk_disable(p);
+ p = &tegra_pll_x;
+ if (p->state == OFF)
+ tegra11_pllxc_clk_disable(p);
+ p = &tegra_pll_re_vco;
+ if (p->state == OFF)
+ tegra11_pllre_clk_disable(p);
+
clk_writel(plla_base, tegra_pll_a.reg + PLL_BASE);
clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE);
clk_writel(plld2_base, tegra_pll_d2.reg + PLL_BASE);
+ clk_writel(pll_m_out1, tegra_pll_m_out1.reg);
+ clk_writel(pll_a_out0, tegra_pll_a_out0.reg);
+ clk_writel(pll_c_out1, tegra_pll_c_out1.reg);
+
/* Since EMC clock is not restored, and may not preserve parent across
suspend, update current state, and mark EMC DFS as out of sync */
p = tegra_clk_emc.parent;
if (p != tegra_clk_emc.parent) {
/* FIXME: old parent is left enabled here even if EMC was its
- only child before suspend (never happens on tegra11x) */
+ only child before suspend (may happen on Tegra11 !!) */
pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)",
p->name, p->refcnt, tegra_clk_emc.parent->name,
tegra_clk_emc.parent->refcnt);
tegra_emc_timing_invalidate();
tegra11_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */
+ tegra11_plle_clk_resume(&tegra_pll_e); /* Restore plle parent as pll_re_vco */
tegra11_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */
}
+
+static struct syscore_ops tegra_clk_syscore_ops = {
+ .suspend = tegra11_clk_suspend,
+ .resume = tegra11_clk_resume,
+};
#endif
+
+/* Tegra11 CPU clock and reset control functions */
+static void tegra11_wait_cpu_in_reset(u32 cpu)
+{
+ unsigned int reg;
+
+ do {
+ reg = readl(reg_clk_base +
+ TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+ cpu_relax();
+ } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
+
+ return;
+}
+
+static void tegra11_put_cpu_in_reset(u32 cpu)
+{
+ writel(CPU_RESET(cpu),
+ reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+ dmb();
+}
+
+static void tegra11_cpu_out_of_reset(u32 cpu)
+{
+ writel(CPU_RESET(cpu),
+ reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+ wmb();
+}
+
+static void tegra11_enable_cpu_clock(u32 cpu)
+{
+ unsigned int reg;
+
+ writel(CPU_CLOCK(cpu),
+ reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+ reg = readl(reg_clk_base +
+ TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+}
+static void tegra11_disable_cpu_clock(u32 cpu)
+{
+}
+
+static struct tegra_cpu_car_ops tegra11_cpu_car_ops = {
+ .wait_for_reset = tegra11_wait_cpu_in_reset,
+ .put_in_reset = tegra11_put_cpu_in_reset,
+ .out_of_reset = tegra11_cpu_out_of_reset,
+ .enable_clock = tegra11_enable_cpu_clock,
+ .disable_clock = tegra11_disable_cpu_clock,
+};
+
+static void __init tegra11_cpu_car_ops_init(void)
+{
+ tegra_cpu_car_ops = &tegra11_cpu_car_ops;
+}
+
+void __init tegra11x_init_clocks(void)
+{
+ int i;
+ struct clk *c;
+
+ for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+ tegra11_init_one_clock(tegra_ptr_clks[i]);
+
+ for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+ tegra11_init_one_clock(&tegra_list_clks[i]);
+
+ for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
+ tegra11_init_one_clock(&tegra_sync_source_list[i]);
+ for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
+ tegra11_init_one_clock(&tegra_clk_audio_list[i]);
+ for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
+ tegra11_init_one_clock(&tegra_clk_audio_2x_list[i]);
+
+ init_clk_out_mux();
+ for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
+ tegra11_init_one_clock(&tegra_clk_out_list[i]);
+
+ for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
+ tegra11_init_one_clock(&tegra_xusb_source_clks[i]);
+
+ for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
+ tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]);
+
+ for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+ c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+ if (!c) {
+ pr_err("%s: Unknown duplicate clock %s\n", __func__,
+ tegra_clk_duplicates[i].name);
+ continue;
+ }
+
+ tegra_clk_duplicates[i].lookup.clk = c;
+ clkdev_add(&tegra_clk_duplicates[i].lookup);
+ }
+
+ /* Initialize to default */
+ tegra_init_cpu_edp_limits(0);
+
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+ /* To be ready for DFLL late init */
+ tegra_dfll_cpu.ops->init = tegra11_dfll_cpu_late_init;
+#endif
+
+ tegra11_cpu_car_ops_init();
+
+#ifdef CONFIG_PM_SLEEP
+ register_syscore_ops(&tegra_clk_syscore_ops);
+#endif
+}