ARM: tegra: clock: Update CPU cluster switch clock control
[linux-3.10.git] / arch / arm / mach-tegra / tegra11_clocks.c
index 0b725ab..eb412a8 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/tegra11_clocks.c
  *
- * Copyright (C) 2011-2012 NVIDIA Corporation
+ * Copyright (C) 2011-2013 NVIDIA Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
 #include <linux/cpufreq.h>
 #include <linux/syscore_ops.h>
 #include <linux/platform_device.h>
+#include <linux/clk/tegra.h>
 
 #include <asm/clkdev.h>
 
-#include <mach/iomap.h>
 #include <mach/edp.h>
 #include <mach/hardware.h>
 #include <mach/mc.h>
 
 #include "clock.h"
 #include "fuse.h"
+#include "iomap.h"
 #include "dvfs.h"
 #include "pm.h"
 #include "sleep.h"
        ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 
 #define PLLCX_MISC_DIV_LOW_RANGE       \
-       ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
-#define PLLCX_MISC_DIV_HIGH_RANGE      \
        ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
+#define PLLCX_MISC_DIV_HIGH_RANGE      \
+       ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 
 #define PLLCX_MISC_DEFAULT_VALUE       ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \
                                        PLLCX_MISC_KOEF_LOW_RANGE | \
 #define UTMIP_PLL_CFG2_STABLE_COUNT(x)                 (((x) & 0xfff) << 6)
 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x)             (((x) & 0x3f) << 18)
 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN       (1 << 0)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP         (1 << 1)
 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN       (1 << 2)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP         (1 << 3)
 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN       (1 << 4)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP         (1 << 5)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN       (1 << 24)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP         (1 << 25)
 
 #define UTMIP_PLL_CFG1                                 0x484
 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x)             (((x) & 0x1f) << 27)
 #define PLLE_MISC_VREG_CTRL_MASK       (0x3<<PLLE_MISC_VREG_CTRL_SHIFT)
 
 #define PLLE_SS_CTRL                   0x68
+#define        PLLE_SS_INCINTRV_SHIFT          24
+#define        PLLE_SS_INCINTRV_MASK           (0x3f<<PLLE_SS_INCINTRV_SHIFT)
+#define        PLLE_SS_INC_SHIFT               16
+#define        PLLE_SS_INC_MASK                (0xff<<PLLE_SS_INC_SHIFT)
 #define        PLLE_SS_CNTL_SSC_BYP            (0x1 << 12)
 #define        PLLE_SS_CNTL_INTERP_RESET       (0x1 << 11)
 #define        PLLE_SS_CNTL_BYPASS_SS          (0x1 << 10)
+#define        PLLE_SS_MAX_SHIFT               0
+#define        PLLE_SS_MAX_MASK                (0x1ff<<PLLE_SS_MAX_SHIFT)
+#define PLLE_SS_COEFFICIENTS_MASK      \
+       (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
+#define PLLE_SS_COEFFICIENTS_VAL       \
+       ((0x20<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
+        (0x25<<PLLE_SS_MAX_SHIFT))
 #define PLLE_SS_DISABLE                        (PLLE_SS_CNTL_SSC_BYP |\
        PLLE_SS_CNTL_INTERP_RESET | PLLE_SS_CNTL_BYPASS_SS)
-#define PLLE_SS_COEFFICIENTS_MASK       (~PLLE_SS_DISABLE)
 
 #define PLLE_AUX                       0x48c
 #define PLLE_AUX_PLLRE_SEL             (1<<28)
 #define PLLE_AUX_SEQ_STATE_SHIFT       26
 #define PLLE_AUX_SEQ_STATE_MASK                (0x3<<PLLE_AUX_SEQ_STATE_SHIFT)
+#define PLLE_AUX_SEQ_START_STATE       (1<<25)
 #define PLLE_AUX_SEQ_ENABLE            (1<<24)
+#define PLLE_AUX_SS_SWCTL              (1<<6)
 #define PLLE_AUX_ENABLE_SWCTL          (1<<4)
 #define PLLE_AUX_USE_LOCKDET           (1<<3)
 #define PLLE_AUX_PLLP_SEL              (1<<2)
 
 /* USB PLLs PD HW controls */
 #define XUSBIO_PLL_CFG0                                0x51c
+#define XUSBIO_PLL_CFG0_SEQ_START_STATE                (1<<25)
 #define XUSBIO_PLL_CFG0_SEQ_ENABLE             (1<<24)
 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET     (1<<6)
 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL       (1<<2)
 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL     (1<<0)
 
+/* XUSB PLL PAD controls */
+#define XUSB_PADCTL_IOPHY_PLL0_CTL1                    0x30
+#define XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD       (1<<3)
+#define XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ           (1<<0)
+
 #define UTMIPLL_HW_PWRDN_CFG0                  0x52c
 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE  (1<<25)
 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE       (1<<24)
 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL       (1<<0)
 
 #define PLLU_HW_PWRDN_CFG0                     0x530
+#define PLLU_HW_PWRDN_CFG0_SEQ_START_STATE     (1<<25)
 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE          (1<<24)
 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET         (1<<6)
 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL    (1<<2)
 #define USB_PLLS_USE_LOCKDET                   (1<<6)
 #define USB_PLLS_ENABLE_SWCTL                  ((1<<2) | (1<<0))
 
+/* CPU clock trimmers */
+#define CPU_FINETRIM_BYP                       0x4d0
+#define CPU_FINETRIM_SELECT                    0x4d4
+#define CPU_FINETRIM_DR                                0x4d8
+#define CPU_FINETRIM_DF                                0x4dc
+#define CPU_FINETRIM_F                         0x4e0
+#define CPU_FINETRIM_R                         0x4e4
+
 /* DFLL */
 #define DFLL_BASE                              0x2f4
 #define DFLL_BASE_RESET                                (1<<0)
 #define ROUND_DIVIDER_DOWN     1
 #define DIVIDER_1_5_ALLOWED    0
 
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX         0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET     0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR     0x344
+#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR   0x34c
+#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS    0x470
+
 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
 #define CPU_RESET(cpu) (0x111001ul << (cpu))
 
 /* PLLP default fixed rate in h/w controlled mode */
 #define PLLP_DEFAULT_FIXED_RATE                216000000
 
+/* Use PLL_RE as PLLE input (default - OSC via pll reference divider) */
+#define USE_PLLE_INPUT_PLLRE   0
+
 static bool tegra11_is_dyn_ramp(struct clk *c,
                                unsigned long rate, bool from_vco_min);
 static void tegra11_pllp_init_dependencies(unsigned long pllp_rate);
-static unsigned long tegra11_clk_shared_bus_update(
-       struct clk *bus, struct clk **bus_top, struct clk **bus_slow);
+static unsigned long tegra11_clk_shared_bus_update(struct clk *bus,
+       struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap);
+static unsigned long tegra11_clk_cap_shared_bus(struct clk *bus,
+       unsigned long rate, unsigned long ceiling);
 
 static bool detach_shared_bus;
 module_param(detach_shared_bus, bool, 0644);
@@ -518,6 +563,7 @@ static const struct utmi_clk_param utmi_parameters[] =
 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
+static void __iomem *reg_xusb_padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
 
 #define MISC_GP_HIDREV                         0x804
 #define MISC_GP_TRANSACTOR_SCRATCH_0           0x864
@@ -534,19 +580,23 @@ static DEFINE_SPINLOCK(periph_refcount_lock);
 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
 
 #define clk_writel(value, reg) \
-       __raw_writel(value, (u32)reg_clk_base + (reg))
+       __raw_writel(value, reg_clk_base + (reg))
 #define clk_readl(reg) \
-       __raw_readl((u32)reg_clk_base + (reg))
+       __raw_readl(reg_clk_base + (reg))
 #define pmc_writel(value, reg) \
-       __raw_writel(value, (u32)reg_pmc_base + (reg))
+       __raw_writel(value, reg_pmc_base + (reg))
 #define pmc_readl(reg) \
-       __raw_readl((u32)reg_pmc_base + (reg))
+       __raw_readl(reg_pmc_base + (reg))
 #define chipid_readl() \
-       __raw_readl((u32)misc_gp_base + MISC_GP_HIDREV)
+       __raw_readl(misc_gp_base + MISC_GP_HIDREV)
+#define xusb_padctl_writel(value, reg) \
+       __raw_writel(value, reg_xusb_padctl_base + (reg))
+#define xusb_padctl_readl(reg) \
+       __raw_readl(reg_xusb_padctl_base + (reg))
 
 #define clk_writel_delay(value, reg)                                   \
        do {                                                            \
-               __raw_writel((value), (u32)reg_clk_base + (reg));       \
+               __raw_writel((value), reg_clk_base + (reg));    \
                udelay(2);                                              \
        } while (0)
 
@@ -1107,8 +1157,10 @@ static int tegra11_cpu_clk_dfll_on(struct clk *c, unsigned long rate,
                        }
                }
 
+               tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
                ret = clk_set_parent(c->parent, dfll);
                if (ret) {
+                       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
                        pr_err("Failed to switch cpu to %s\n", dfll->name);
                        return ret;
                }
@@ -1117,6 +1169,7 @@ static int tegra11_cpu_clk_dfll_on(struct clk *c, unsigned long rate,
 
                /* prevent legacy dvfs voltage scaling */
                tegra_dvfs_dfll_mode_set(c->dvfs, rate);
+               tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        }
        return 0;
 }
@@ -1131,7 +1184,23 @@ static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
 
        rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost);
        pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main;
+       dfll_rate_min = max(rate, dfll_rate_min);
+
+       /* set target rate last time in dfll mode */
+       if (old_rate != dfll_rate_min) {
+               ret = tegra_dvfs_set_rate(c, dfll_rate_min);
+               if (!ret)
+                       ret = clk_set_rate(dfll, dfll_rate_min);
+
+               if (ret) {
+                       pr_err("Failed to set cpu rate %lu on source %s\n",
+                              dfll_rate_min, dfll->name);
+                       return ret;
+               }
+       }
 
+       /* unlock dfll - release volatge rail control */
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
        ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
        if (ret) {
                pr_err("Failed to unlock %s\n", dfll->name);
@@ -1139,7 +1208,7 @@ static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
        }
 
        /* restore legacy dvfs operations and set appropriate voltage */
-       ret = tegra_dvfs_dfll_mode_clear(c->dvfs, max(rate, dfll_rate_min));
+       ret = tegra_dvfs_dfll_mode_clear(c->dvfs, dfll_rate_min);
        if (ret) {
                pr_err("Failed to set cpu rail for rate %lu\n", rate);
                goto back_to_dfll;
@@ -1163,11 +1232,13 @@ static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
        if (old_rate <= rate)
                tegra_dvfs_set_rate(c, rate);
 
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return 0;
 
 back_to_dfll:
        tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
        tegra_dvfs_dfll_mode_set(c->dvfs, old_rate);
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return ret;
 }
 
@@ -1184,7 +1255,8 @@ static int tegra11_cpu_clk_set_rate(struct clk *c, unsigned long rate)
        if (c->dvfs) {
                if (!c->dvfs->dvfs_rail)
                        return -ENOSYS;
-               else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate)) {
+               else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate) &&
+                        (c->boot_rate < rate)) {
                        WARN(1, "Increasing CPU rate while regulator is not"
                                " ready is not allowed\n");
                        return -ENOSYS;
@@ -1205,7 +1277,7 @@ static long tegra11_cpu_clk_round_rate(struct clk *c, unsigned long rate)
        unsigned long max_rate = c->max_rate;
 
        /* Remove dfll boost to maximum rate when running on PLL */
-       if (!c->dvfs || !tegra_dvfs_is_dfll_scale(c->dvfs, rate))
+       if (c->dvfs && !tegra_dvfs_is_dfll_scale(c->dvfs, rate))
                max_rate -= c->dvfs->dfll_data.max_rate_boost;
 
        if (rate > max_rate)
@@ -1288,6 +1360,7 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
        const struct clk_mux_sel *sel;
        unsigned long rate = clk_get_rate(c->parent);
        struct clk *dfll = c->parent->u.cpu.dynamic ? : p->u.cpu.dynamic;
+       struct clk *p_source_old = NULL;
        struct clk *p_source;
 
        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
@@ -1345,6 +1418,7 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                return 0;       /* already switched - exit */
        }
 
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
        if (c->parent->parent->parent == dfll) {
                /* G (DFLL selected as clock source) => LP switch:
                 * turn DFLL into open loop mode ("release" VDD_CPU rail)
@@ -1354,28 +1428,38 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                if (ret)
                        goto abort;
 
+               ret = tegra_dvfs_rail_dfll_mode_set_cold(tegra_cpu_rail);
+               if (ret)
+                       goto abort;
+
                p_source = rate <= p->u.cpu.backup_rate ?
                        p->u.cpu.backup : p->u.cpu.main;
                ret = clk_set_rate(p_source, rate);
                if (ret)
                        goto abort;
-       } else if (p->parent->parent == dfll) {
+       } else if ((p->parent->parent == dfll) || ((p->u.cpu.dynamic == dfll) &&
+                       (dfll->state != UNINITIALIZED) && use_dfll)) {
                /* LP => G (DFLL selected as clock source) switch:
                 * set DFLL rate ready (DFLL is still disabled)
                 * (set target p_source as dfll, G source is already selected)
                 */
                p_source = dfll;
-               ret = clk_set_rate(p_source, rate);
+               ret = clk_set_rate(dfll,
+                       tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail) ? rate :
+                       max(rate, p->dvfs->dfll_data.use_dfll_rate_min));
                if (ret)
                        goto abort;
        } else
-               /* DFLL is not selcted on either side of the switch:
+               /* DFLL is not selected on either side of the switch:
                 * set target p_source equal to current clock source
                 */
                p_source = c->parent->parent->parent;
 
        /* Switch new parent to target clock source if necessary */
        if (p->parent->parent != p_source) {
+               clk_enable(p->parent->parent);
+               clk_enable(p->parent);
+               p_source_old = p->parent->parent;
                ret = clk_set_parent(p->parent, p_source);
                if (ret) {
                        pr_err("%s: Failed to set parent %s for %s\n",
@@ -1400,21 +1484,50 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
        }
 
        /* Disabling old parent scales old mode voltage rail */
-       if (c->refcnt && c->parent)
+       if (c->refcnt)
                clk_disable(c->parent);
+       if (p_source_old) {
+               clk_disable(p->parent);
+               clk_disable(p_source_old);
+       }
 
        clk_reparent(c, p);
 
-       /* Lock DFLL now (resume closed loop VDD_CPU control) */
-       if (p_source == dfll)
-               tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+       /*
+        * Lock DFLL now (resume closed loop VDD_CPU control).
+        * G CPU operations are always resumed on DFLL if it can be used, even
+        * when autoswitch between PLL and DFLL is allowed, and resume rate is
+        * low enough to run on PLL. This makes CPU clock source ready for
+        * speedy ramp with cl_dvfs controlling volatge (and that ramp is the
+        * most likely reason for going to G CPU in the 1st place)
+        */
+       if (p_source == dfll) {
+               if (tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail)) {
+                       tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+               } else {
+                       clk_set_rate(dfll, rate);
+                       tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+                       tegra_dvfs_dfll_mode_set(p->dvfs, rate);
+               }
+       }
 
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return 0;
 
 abort:
        /* Re-lock DFLL if necessary after aborted switch */
-       if (c->parent->parent->parent == dfll)
+       if (c->parent->parent->parent == dfll) {
+               clk_set_rate(dfll, rate);
                tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+       }
+       if (p_source_old) {
+               clk_disable(p->parent);
+               clk_disable(p_source_old);
+       }
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
+
+       pr_err("%s: aborted switch from %s to %s\n",
+              __func__, c->parent->name, p->name);
        return ret;
 }
 
@@ -1530,7 +1643,8 @@ static void tegra11_sbus_cmplx_init(struct clk *c)
  * recursive calls. Lost 1Hz is added in tegra11_sbus_cmplx_set_rate before
  * actually setting divider rate.
  */
-static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
+static long tegra11_sbus_cmplx_round_updown(struct clk *c, unsigned long rate,
+                                           bool up)
 {
        int divider;
        unsigned long source_rate, round_rate;
@@ -1543,9 +1657,9 @@ static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
        source_rate = clk_get_rate(new_parent->parent);
 
        divider = clk_div71_get_divider(source_rate, rate,
-               new_parent->flags, ROUND_DIVIDER_DOWN);
+               new_parent->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
        if (divider < 0)
-               return divider;
+               return c->min_rate;
 
        if (divider == 1)
                divider = 0;
@@ -1567,6 +1681,11 @@ static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
        return round_rate;
 }
 
+static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
+{
+       return tegra11_sbus_cmplx_round_updown(c, rate, true);
+}
+
 static int tegra11_sbus_cmplx_set_rate(struct clk *c, unsigned long rate)
 {
        int ret;
@@ -1622,8 +1741,7 @@ static int tegra11_clk_sbus_update(struct clk *bus)
        if (detach_shared_bus)
                return 0;
 
-       rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
-       rate = clk_round_rate_locked(bus, rate);
+       rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL);
 
        old_rate = clk_get_rate_locked(bus);
        if (rate == old_rate)
@@ -1636,6 +1754,7 @@ static struct clk_ops tegra_sbus_cmplx_ops = {
        .init = tegra11_sbus_cmplx_init,
        .set_rate = tegra11_sbus_cmplx_set_rate,
        .round_rate = tegra11_sbus_cmplx_round_rate,
+       .round_rate_updown = tegra11_sbus_cmplx_round_updown,
        .shared_bus_update = tegra11_clk_sbus_update,
 };
 
@@ -1728,15 +1847,28 @@ static int tegra11_pll_clk_wait_for_lock(
 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
 #if USE_PLL_LOCK_BITS
        int i;
+       u32 val = 0;
+
        for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) {
                udelay(PLL_PRE_LOCK_DELAY);
-               if ((clk_readl(lock_reg) & lock_bits) == lock_bits) {
+               val = clk_readl(lock_reg);
+               if ((val & lock_bits) == lock_bits) {
                        udelay(PLL_POST_LOCK_DELAY);
                        return 0;
                }
        }
-       pr_err("Timed out waiting for lock bit on pll %s\n", c->name);
-       return -1;
+
+       /* PLLCX lock bits may fluctuate after the lock - don't report timeout
+          in this case (phase lock bit happens to uniquely identify PLLCX) */
+       if (lock_bits & PLLCX_BASE_PHASE_LOCK) {
+               pr_debug("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+                        c->name, lock_reg, val);
+               return 0;
+       } else {
+               pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+                      c->name, lock_reg, val);
+               return -ETIMEDOUT;
+       }
 #endif
        udelay(c->u.pll.lock_delay);
 #endif
@@ -1746,7 +1878,7 @@ static int tegra11_pll_clk_wait_for_lock(
 static void usb_plls_hw_control_enable(u32 reg)
 {
        u32 val = clk_readl(reg);
-       val |= USB_PLLS_USE_LOCKDET;
+       val |= USB_PLLS_USE_LOCKDET | USB_PLLS_SEQ_START_STATE;
        val &= ~USB_PLLS_ENABLE_SWCTL;
        val |= USB_PLLS_SEQ_START_STATE;
        pll_writel_delay(val, reg);
@@ -1787,9 +1919,14 @@ static void tegra11_utmi_param_configure(struct clk *c)
                        utmi_parameters[i].active_delay_count);
 
        /* Remove power downs from UTMIP PLL control bits */
+       reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
+       reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
+       reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP;
+       reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
+       reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
 
        clk_writel(reg, UTMIP_PLL_CFG2);
 
@@ -1829,7 +1966,7 @@ static void tegra11_utmi_param_configure(struct clk *c)
           ports are assigned to USB2 */
        reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
        reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
-       reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
+       reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
        clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
 
        udelay(1);
@@ -1888,6 +2025,12 @@ static void tegra11_pll_clk_init(struct clk *c)
                val = clk_readl(c->reg + PLL_BASE);
                val &= ~PLLU_BASE_OVERRIDE;
                clk_writel(val, c->reg + PLL_BASE);
+
+               /* Set XUSB PLL pad pwr override and iddq */
+               val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL0_CTL1);
+               val |= XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD;
+               val |= XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ;
+               xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL0_CTL1);
        }
 }
 
@@ -1897,6 +2040,12 @@ static int tegra11_pll_clk_enable(struct clk *c)
        pr_debug("%s on clock %s\n", __func__, c->name);
 
 #if USE_PLL_LOCK_BITS
+       /* toggle lock enable bit to reset lock detection circuit (couple
+          register reads provide enough duration for reset pulse) */
+       val = clk_readl(c->reg + PLL_MISC(c));
+       val &= ~PLL_MISC_LOCK_ENABLE(c);
+       clk_writel(val, c->reg + PLL_MISC(c));
+       val = clk_readl(c->reg + PLL_MISC(c));
        val = clk_readl(c->reg + PLL_MISC(c));
        val |= PLL_MISC_LOCK_ENABLE(c);
        clk_writel(val, c->reg + PLL_MISC(c));
@@ -1921,6 +2070,21 @@ static void tegra11_pll_clk_disable(struct clk *c)
        clk_writel(val, c->reg);
 }
 
+static u8 get_pll_cpcon(struct clk *c, u16 n)
+{
+       if (c->flags & PLLD) {
+               if (n >= 600)
+                       return 12;
+               else if (n >= 300)
+                       return 8;
+               else if (n >= 50)
+                       return 3;
+               else
+                       return 2;
+       }
+       return c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
+}
+
 static int tegra11_pll_clk_set_rate(struct clk *c, unsigned long rate)
 {
        u32 val, p_div, old_base;
@@ -1998,7 +2162,7 @@ static int tegra11_pll_clk_set_rate(struct clk *c, unsigned long rate)
                cfg.p = 0x1 << p_div;
                cfg.m = input_rate / cfreq;
                cfg.n = cfg.output_rate / cfreq;
-               cfg.cpcon = c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
+               cfg.cpcon = get_pll_cpcon(c, cfg.n);
 
                if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
                    (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
@@ -2930,7 +3094,6 @@ static struct clk_ops tegra_pllm_ops = {
 };
 
 
-/* FIXME: pllre suspend/resume */
 /* non-monotonic mapping below is not a typo */
 static u8 pllre_p[PLLRE_PDIV_MAX + 1] = {
 /* PDIV: 0, 1, 2, 3, 4, 5, 6,  7,  8,  9, 10, 11, 12, 13, 14 */
@@ -3136,16 +3299,66 @@ static struct clk_ops tegra_pllre_out_ops = {
        .set_rate               = tegra11_pllre_out_clk_set_rate,
 };
 
-/* FIXME: plle suspend/resume */
+#ifdef CONFIG_PM_SLEEP
+/* Resume both pllre_vco and pllre_out */
+static void tegra11_pllre_clk_resume_enable(struct clk *c)
+{
+       u32 pdiv;
+       u32 val = clk_readl(c->reg + PLL_BASE);
+       unsigned long rate = clk_get_rate_all_locked(c->parent->parent);
+       enum clk_state state = c->parent->state;
+
+       if (val & PLL_BASE_ENABLE)
+               return;         /* already resumed */
+
+       /* temporarily sync h/w and s/w states, final sync happens
+          in tegra_clk_resume later */
+       c->parent->state = OFF;
+       pllre_set_defaults(c->parent, rate);
+
+       /* restore PLLRE VCO feedback loop (m, n) */
+       rate = clk_get_rate_all_locked(c->parent) + 1;
+       tegra11_pllre_clk_set_rate(c->parent, rate);
+
+       /* restore PLLRE post-divider */
+       c->parent->u.pll.round_p_to_pdiv(c->div, &pdiv);
+       val = clk_readl(c->reg);
+       val &= ~PLLRE_BASE_DIVP_MASK;
+       val |= pdiv << PLLRE_BASE_DIVP_SHIFT;
+       clk_writel(val, c->reg);
+
+       tegra11_pllre_clk_enable(c->parent);
+       c->parent->state = state;
+}
+#endif
+
 /* non-monotonic mapping below is not a typo */
 static u8 plle_p[PLLE_CMLDIV_MAX + 1] = {
 /* CMLDIV: 0, 1, 2, 3, 4, 5, 6,  7,  8,  9, 10, 11, 12, 13, 14 */
 /* p: */   1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
 
+static inline void select_pll_e_input(u32 aux_reg)
+{
+#if USE_PLLE_INPUT_PLLRE
+       aux_reg |= PLLE_AUX_PLLRE_SEL;
+#else
+       aux_reg &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
+#endif
+       clk_writel(aux_reg, PLLE_AUX);
+}
+
 static void tegra11_plle_clk_init(struct clk *c)
 {
        u32 val, p;
-       struct clk *ref = tegra_get_clock_by_name("pll_re_vco");
+       struct clk *pll_ref = tegra_get_clock_by_name("pll_ref");
+       struct clk *re_vco = tegra_get_clock_by_name("pll_re_vco");
+       struct clk *pllp = tegra_get_clock_by_name("pllp");
+#if USE_PLLE_INPUT_PLLRE
+       struct clk *ref = re_vco;
+#else
+       struct clk *ref = pll_ref;
+#endif
+
 
        val = clk_readl(c->reg + PLL_BASE);
        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
@@ -3155,18 +3368,15 @@ static void tegra11_plle_clk_init(struct clk *c)
        c->div *= plle_p[p];
 
        val = clk_readl(PLLE_AUX);
-       c->parent = (val & PLLE_AUX_PLLRE_SEL) ? ref :
-                       (val & PLLE_AUX_PLLP_SEL) ?
-                               tegra_get_clock_by_name("pll_p") :
-                               tegra_get_clock_by_name("pll_ref");
+       c->parent = (val & PLLE_AUX_PLLRE_SEL) ? re_vco :
+               (val & PLLE_AUX_PLLP_SEL) ? pllp : pll_ref;
        if (c->parent != ref) {
                if (c->state == ON) {
                        WARN(1, "%s: pll_e is left enabled with %s input\n",
                             __func__, c->parent->name);
                } else {
                        c->parent = ref;
-                       val |= PLLE_AUX_PLLRE_SEL;
-                       clk_writel(val, PLLE_AUX);
+                       select_pll_e_input(val);
                }
        }
 }
@@ -3216,11 +3426,6 @@ static int tegra11_plle_clk_enable(struct clk *c)
        val &= ~PLLE_BASE_LOCK_OVERRIDE;
        clk_writel(val, c->reg + PLL_BASE);
 
-       val = clk_readl(PLLE_AUX);
-       val |= PLLE_AUX_ENABLE_SWCTL;
-       val &= ~PLLE_AUX_SEQ_ENABLE;
-       pll_writel_delay(val, PLLE_AUX);
-
        val = clk_readl(c->reg + PLL_MISC(c));
        val |= PLLE_MISC_LOCK_ENABLE;
        val |= PLLE_MISC_IDDQ_SW_CTRL;
@@ -3251,7 +3456,14 @@ static int tegra11_plle_clk_enable(struct clk *c)
        tegra11_pll_clk_wait_for_lock(
                c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
 #if USE_PLLE_SS
-       /* FIXME: enable SS if necessary */
+       val = clk_readl(PLLE_SS_CTRL);
+       val &= ~PLLE_SS_COEFFICIENTS_MASK;
+       val |= PLLE_SS_COEFFICIENTS_VAL;
+       clk_writel(val, PLLE_SS_CTRL);
+       val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
+       pll_writel_delay(val, PLLE_SS_CTRL);
+       val &= ~PLLE_SS_CNTL_INTERP_RESET;
+       pll_writel_delay(val, PLLE_SS_CTRL);
 #endif
 #if !USE_PLLE_SWCTL
        /* switch pll under h/w control */
@@ -3260,18 +3472,37 @@ static int tegra11_plle_clk_enable(struct clk *c)
        clk_writel(val, c->reg + PLL_MISC(c));
 
        val = clk_readl(PLLE_AUX);
-       val |= PLLE_AUX_USE_LOCKDET;
-       val &= ~PLLE_AUX_ENABLE_SWCTL;
+       val |= PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE;
+       val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
        pll_writel_delay(val, PLLE_AUX);
        val |= PLLE_AUX_SEQ_ENABLE;
        pll_writel_delay(val, PLLE_AUX);
 #endif
+       /* clear XUSB PLL pad pwr override and iddq */
+       val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL0_CTL1);
+       val &= ~XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD;
+       val &= ~XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ;
+       xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL0_CTL1);
+
        /* enable hw control of xusb brick pll */
        usb_plls_hw_control_enable(XUSBIO_PLL_CFG0);
 
        return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static void tegra11_plle_clk_resume(struct clk *c)
+{
+       u32 val = clk_readl(c->reg + PLL_BASE);
+       if (val & PLL_BASE_ENABLE)
+               return;         /* already resumed */
+
+       /* Restore parent */
+       val = clk_readl(PLLE_AUX);
+       select_pll_e_input(val);
+}
+#endif
+
 static struct clk_ops tegra_plle_ops = {
        .init                   = tegra11_plle_clk_init,
        .enable                 = tegra11_plle_clk_enable,
@@ -3287,12 +3518,35 @@ static struct clk_ops tegra_plle_ops = {
  * basically cl-dvfs wrappers.
  */
 
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
 /* DFLL operations */
+static void tune_cpu_trimmers(bool trim_high)
+{
+       if (trim_high) {
+               clk_writel(0, CPU_FINETRIM_SELECT);
+               clk_writel(0, CPU_FINETRIM_DR);
+               clk_writel(0, CPU_FINETRIM_R);
+       } else {
+               clk_writel(0x3F, CPU_FINETRIM_SELECT);
+               clk_writel(0x3F, CPU_FINETRIM_DR);
+               clk_writel(0xFFF, CPU_FINETRIM_R);
+       }
+       wmb();
+       clk_readl(CPU_FINETRIM_R);
+}
+
 static void __init tegra11_dfll_cpu_late_init(struct clk *c)
 {
 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
        int ret;
-       struct clk *cpu = tegra_get_clock_by_name("cpu");
+       struct clk *cpu = tegra_get_clock_by_name("cpu_g");
+
+       if (!cpu || !cpu->dvfs) {
+               pr_err("%s: CPU dvfs is not present\n", __func__);
+               return;
+       }
+       if (cpu->dvfs->speedo_id > 0)   /* A01P and above parts */
+               tegra_dvfs_set_dfll_tune_trimmers(cpu->dvfs, tune_cpu_trimmers);
 
 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
        u32 netlist, patchid;
@@ -3312,11 +3566,12 @@ static void __init tegra11_dfll_cpu_late_init(struct clk *c)
                c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device);
 
                use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
-               tegra_dvfs_set_dfll_range(cpu->parent->dvfs, use_dfll);
+               tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll);
                pr_info("Tegra CPU DFLL is initialized\n");
        }
 #endif
 }
+#endif
 
 static int tegra11_dfll_clk_enable(struct clk *c)
 {
@@ -3359,8 +3614,10 @@ static void tegra11_dfll_clk_resume(struct clk *c)
        if (!(clk_readl(c->reg) & DFLL_BASE_RESET))
                return;         /* already resumed */
 
-       tegra_periph_reset_deassert(c);
-       tegra_cl_dvfs_resume(c->u.dfll.cl_dvfs);
+       if (c->state != UNINITIALIZED) {
+               tegra_periph_reset_deassert(c);
+               tegra_cl_dvfs_resume(c->u.dfll.cl_dvfs);
+       }
 }
 #endif
 
@@ -4135,20 +4392,25 @@ static void tegra11_emc_clk_init(struct clk *c)
 {
        tegra11_periph_clk_init(c);
        tegra_emc_dram_type_init(c);
-       c->max_rate = clk_get_rate(c->parent);
 }
 
-static long tegra11_emc_clk_round_rate(struct clk *c, unsigned long rate)
+static long tegra11_emc_clk_round_updown(struct clk *c, unsigned long rate,
+                                        bool up)
 {
        long new_rate = max(rate, c->min_rate);
 
-       new_rate = tegra_emc_round_rate(new_rate);
+       new_rate = tegra_emc_round_rate_updown(new_rate, up);
        if (new_rate < 0)
                new_rate = c->max_rate;
 
        return new_rate;
 }
 
+static long tegra11_emc_clk_round_rate(struct clk *c, unsigned long rate)
+{
+       return tegra11_emc_clk_round_updown(c, rate, true);
+}
+
 static int tegra11_emc_clk_set_rate(struct clk *c, unsigned long rate)
 {
        int ret;
@@ -4197,8 +4459,7 @@ static int tegra11_clk_emc_bus_update(struct clk *bus)
        if (detach_shared_bus)
                return 0;
 
-       rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
-       rate = clk_round_rate_locked(bus, rate);
+       rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL);
 
        old_rate = clk_get_rate_locked(bus);
        if (rate == old_rate)
@@ -4246,6 +4507,7 @@ static struct clk_ops tegra_emc_clk_ops = {
        .disable                = &tegra11_periph_clk_disable,
        .set_rate               = &tegra11_emc_clk_set_rate,
        .round_rate             = &tegra11_emc_clk_round_rate,
+       .round_rate_updown      = &tegra11_emc_clk_round_updown,
        .reset                  = &tegra11_periph_clk_reset,
        .shared_bus_update      = &tegra11_clk_emc_bus_update,
 };
@@ -4388,7 +4650,8 @@ static int tegra11_clk_cbus_enable(struct clk *c)
        return 0;
 }
 
-static long tegra11_clk_cbus_round_rate(struct clk *c, unsigned long rate)
+static long tegra11_clk_cbus_round_updown(struct clk *c, unsigned long rate,
+                                         bool up)
 {
        int i;
 
@@ -4412,15 +4675,24 @@ static long tegra11_clk_cbus_round_rate(struct clk *c, unsigned long rate)
        }
        rate = max(rate, c->min_rate);
 
-       for (i = 0; i < (c->dvfs->num_freqs - 1); i++) {
+       for (i = 0; ; i++) {
                unsigned long f = c->dvfs->freqs[i];
                int mv = c->dvfs->millivolts[i];
-               if ((f >= rate) || (mv >= c->dvfs->max_millivolts))
+               if ((f >= rate) || (mv >= c->dvfs->max_millivolts) ||
+                   ((i + 1) >=  c->dvfs->num_freqs)) {
+                       if (!up && i && (f > rate))
+                               i--;
                        break;
+               }
        }
        return c->dvfs->freqs[i];
 }
 
+static long tegra11_clk_cbus_round_rate(struct clk *c, unsigned long rate)
+{
+       return tegra11_clk_cbus_round_updown(c, rate, true);
+}
+
 static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort)
 {
        int ret = 0;
@@ -4581,11 +4853,12 @@ static int tegra11_clk_cbus_update(struct clk *bus)
        struct clk *top = NULL;
        unsigned long rate;
        unsigned long old_rate;
+       unsigned long ceiling;
 
        if (detach_shared_bus)
                return 0;
 
-       rate = tegra11_clk_shared_bus_update(bus, &top, &slow);
+       rate = tegra11_clk_shared_bus_update(bus, &top, &slow, &ceiling);
 
        /* use dvfs table of the slowest enabled client as cbus dvfs table */
        if (bus->dvfs && slow && (slow != bus->u.cbus.slow_user)) {
@@ -4604,7 +4877,7 @@ static int tegra11_clk_cbus_update(struct clk *bus)
        bus->u.cbus.slow_user = slow;
        bus->u.cbus.top_user = top;
 
-       rate = bus->ops->round_rate(bus, rate);
+       rate = tegra11_clk_cap_shared_bus(bus, rate, ceiling);
        mv = tegra_dvfs_predict_millivolts(bus, rate);
        if (IS_ERR_VALUE(mv))
                return -EINVAL;
@@ -4619,7 +4892,7 @@ static int tegra11_clk_cbus_update(struct clk *bus)
        }
 
        old_rate = clk_get_rate_locked(bus);
-       if (old_rate != rate) {
+       if (IS_ENABLED(CONFIG_TEGRA_MIGRATE_CBUS_USERS) || (old_rate != rate)) {
                ret = bus->ops->set_rate(bus, rate);
                if (ret)
                        return ret;
@@ -4644,8 +4917,7 @@ static int tegra11_clk_cbus_update(struct clk *bus)
        if (detach_shared_bus)
                return 0;
 
-       rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
-       rate = clk_round_rate_locked(bus, rate);
+       rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL);
 
        old_rate = clk_get_rate_locked(bus);
        if (rate == old_rate)
@@ -4710,6 +4982,7 @@ static struct clk_ops tegra_clk_cbus_ops = {
        .enable = tegra11_clk_cbus_enable,
        .set_rate = tegra11_clk_cbus_set_rate,
        .round_rate = tegra11_clk_cbus_round_rate,
+       .round_rate_updown = tegra11_clk_cbus_round_updown,
        .shared_bus_update = tegra11_clk_cbus_update,
 };
 
@@ -4720,10 +4993,17 @@ static struct clk_ops tegra_clk_cbus_ops = {
  * clock to each user.  The frequency of the bus is set to the highest
  * enabled shared_bus_user clock, with a minimum value set by the
  * shared bus.
+ *
+ * Optionally shared bus may support users migration. Since shared bus and
+ * its * children (users) have reversed rate relations: user rates determine
+ * bus rate, * switching user from one parent/bus to another may change rates
+ * of both parents. Therefore we need a cross-bus lock on top of individual
+ * user and bus locks. For now, limit bus switch support to cbus only if
+ * CONFIG_TEGRA_MIGRATE_CBUS_USERS is set.
  */
 
-static unsigned long tegra11_clk_shared_bus_update(
-       struct clk *bus, struct clk **bus_top, struct clk **bus_slow)
+static unsigned long tegra11_clk_shared_bus_update(struct clk *bus,
+       struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap)
 {
        struct clk *c;
        struct clk *slow = NULL;
@@ -4767,7 +5047,8 @@ static unsigned long tegra11_clk_shared_bus_update(
                        case SHARED_FLOOR:
                        default:
                                rate = max(request_rate, rate);
-                               if (c->u.shared_bus_user.client) {
+                               if (c->u.shared_bus_user.client
+                                                       && request_rate) {
                                        if (top_rate < request_rate) {
                                                top_rate = request_rate;
                                                top = c;
@@ -4789,15 +5070,37 @@ static unsigned long tegra11_clk_shared_bus_update(
                bw = (bw < bus->max_rate / 100) ? (bw * 100) : bus->max_rate;
        }
 
-       rate = override_rate ? : min(max(rate, bw), ceiling);
+       rate = override_rate ? : max(rate, bw);
+       ceiling = override_rate ? bus->max_rate : ceiling;
 
-       if (bus_top)
+       if (bus_top && bus_slow && rate_cap) {
+               /* If dynamic bus dvfs table, let the caller to complete
+                  rounding and aggregation */
                *bus_top = top;
-       if (bus_slow)
                *bus_slow = slow;
+               *rate_cap = ceiling;
+       } else {
+               /* If satic bus dvfs table, complete rounding and aggregation */
+               rate = tegra11_clk_cap_shared_bus(bus, rate, ceiling);
+       }
+
        return rate;
 };
 
+static unsigned long tegra11_clk_cap_shared_bus(struct clk *bus,
+       unsigned long rate, unsigned long ceiling)
+{
+       if (bus->ops && bus->ops->round_rate_updown)
+               ceiling = bus->ops->round_rate_updown(bus, ceiling, false);
+
+       rate = min(rate, ceiling);
+
+       if (bus->ops && bus->ops->round_rate)
+               rate = bus->ops->round_rate(bus, rate);
+
+       return rate;
+}
+
 static int tegra_clk_shared_bus_migrate_users(struct clk *user)
 {
        if (detach_shared_bus)
@@ -4816,6 +5119,11 @@ static void tegra_clk_shared_bus_user_init(struct clk *c)
        c->state = OFF;
        c->set = true;
 
+       if (c->u.shared_bus_user.mode == SHARED_CEILING) {
+               c->state = ON;
+               c->refcnt++;
+       }
+
        if (c->u.shared_bus_user.client_id) {
                c->u.shared_bus_user.client =
                        tegra_get_clock_by_name(c->u.shared_bus_user.client_id);
@@ -4835,15 +5143,9 @@ static void tegra_clk_shared_bus_user_init(struct clk *c)
                &c->parent->shared_bus_list);
 }
 
-/*
- * Shared bus and its children/users have reversed rate relations - user rates
- * determine bus rate. Hence switching user from one parent/bus to another may
- * change rates of both parents. Therefore we need a cross-bus lock on top of
- * individual user and bus locks. For now limit bus switch support to cansleep
- * users with cross-clock mutex only.
- */
 static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
 {
+       int ret;
        const struct clk_mux_sel *sel;
 
        if (detach_shared_bus)
@@ -4866,10 +5168,18 @@ static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
                clk_enable(p);
 
        list_move_tail(&c->u.shared_bus_user.node, &p->shared_bus_list);
-       tegra_clk_shared_bus_update(p);
+       ret = tegra_clk_shared_bus_update(p);
+       if (ret) {
+               list_move_tail(&c->u.shared_bus_user.node,
+                              &c->parent->shared_bus_list);
+               tegra_clk_shared_bus_update(c->parent);
+               clk_disable(p);
+               return ret;
+       }
+
        tegra_clk_shared_bus_update(c->parent);
 
-       if (c->refcnt && c->parent)
+       if (c->refcnt)
                clk_disable(c->parent);
 
        clk_reparent(c, p);
@@ -4879,13 +5189,15 @@ static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
 
 static int tegra_clk_shared_bus_user_set_rate(struct clk *c, unsigned long rate)
 {
+       int ret;
+
        c->u.shared_bus_user.rate = rate;
-       tegra_clk_shared_bus_update(c->parent);
+       ret = tegra_clk_shared_bus_update(c->parent);
 
-       if (c->cross_clk_mutex && clk_cansleep(c))
+       if (!ret && c->cross_clk_mutex && clk_cansleep(c))
                tegra_clk_shared_bus_migrate_users(c);
 
-       return 0;
+       return ret;
 }
 
 static long tegra_clk_shared_bus_user_round_rate(
@@ -4911,14 +5223,14 @@ static long tegra_clk_shared_bus_user_round_rate(
 
 static int tegra_clk_shared_bus_user_enable(struct clk *c)
 {
-       int ret = 0;
+       int ret;
 
        c->u.shared_bus_user.enabled = true;
-       tegra_clk_shared_bus_update(c->parent);
-       if (c->u.shared_bus_user.client)
+       ret = tegra_clk_shared_bus_update(c->parent);
+       if (!ret && c->u.shared_bus_user.client)
                ret = clk_enable(c->u.shared_bus_user.client);
 
-       if (c->cross_clk_mutex && clk_cansleep(c))
+       if (!ret && c->cross_clk_mutex && clk_cansleep(c))
                tegra_clk_shared_bus_migrate_users(c);
 
        return ret;
@@ -4998,6 +5310,9 @@ static void tegra11_clk_coupled_gate_disable(struct clk *c)
 
        tegra11_periph_clk_disable(c);
 
+       if (!c->refcnt) /* happens only on boot clean-up: don't propagate */
+               return;
+
        for (sel = c->inputs; sel->input != NULL; sel++) {
                if (sel->input == c->parent)
                        continue;
@@ -5093,7 +5408,11 @@ static struct clk tegra_pll_c = {
 static struct clk tegra_pll_c_out1 = {
        .name      = "pll_c_out1",
        .ops       = &tegra_pll_div_ops,
-       .flags     = DIV_U71 | PERIPH_ON_CBUS,
+#ifdef CONFIG_TEGRA_DUAL_CBUS
+       .flags     = DIV_U71 | DIV_U71_INT,
+#else
+       .flags     = DIV_U71 | DIV_U71_INT | PERIPH_ON_CBUS,
+#endif
        .parent    = &tegra_pll_c,
        .reg       = 0x84,
        .reg_shift = 0,
@@ -5121,8 +5440,8 @@ static struct clk tegra_pll_c2 = {
                .input_max = 48000000,
                .cf_min    = 12000000,
                .cf_max    = 19200000,
-               .vco_min   = 600000000,
-               .vco_max   = 1200000000,
+               .vco_min   = 624000000,
+               .vco_max   = 1248000000,
                .freq_table = tegra_pll_cx_freq_table,
                .lock_delay = 300,
                .misc1 = 0x4f0 - 0x4e8,
@@ -5142,8 +5461,8 @@ static struct clk tegra_pll_c3 = {
                .input_max = 48000000,
                .cf_min    = 12000000,
                .cf_max    = 19200000,
-               .vco_min   = 600000000,
-               .vco_max   = 1200000000,
+               .vco_min   = 624000000,
+               .vco_max   = 1248000000,
                .freq_table = tegra_pll_cx_freq_table,
                .lock_delay = 300,
                .misc1 = 0x504 - 0x4fc,
@@ -5188,7 +5507,7 @@ static struct clk tegra_pll_m_out1 = {
        .parent    = &tegra_pll_m,
        .reg       = 0x94,
        .reg_shift = 0,
-       .max_rate  = 600000000,
+       .max_rate  = 1066000000,
 };
 
 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
@@ -5306,7 +5625,7 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
        { 19200000, 216000000, 720, 16, 4, 12},
        { 26000000, 216000000, 864, 26, 4, 12},
 
-       { 12000000, 594000000, 594, 12, 1, 12},
+       { 12000000, 594000000,  99,  2, 1,  8},
        { 13000000, 594000000, 594, 13, 1, 12},
        { 16800000, 594000000, 495, 14, 1, 12},
        { 19200000, 594000000, 495, 16, 1, 12},
@@ -5336,7 +5655,6 @@ static struct clk tegra_pll_d = {
                .vco_max   = 1000000000,
                .freq_table = tegra_pll_d_freq_table,
                .lock_delay = 1000,
-               .cpcon_default = 8,
        },
 };
 
@@ -5364,7 +5682,6 @@ static struct clk tegra_pll_d2 = {
                .vco_max   = 1000000000,
                .freq_table = tegra_pll_d_freq_table,
                .lock_delay = 1000,
-               .cpcon_default = 12,
        },
 };
 
@@ -5510,14 +5827,14 @@ static struct clk tegra_pll_re_vco = {
        .ops       = &tegra_pllre_ops,
        .reg       = 0x4c4,
        .parent    = &tegra_pll_ref,
-       .max_rate  = 600000000,
+       .max_rate  = 672000000,
        .u.pll = {
                .input_min = 12000000,
                .input_max = 1000000000,
                .cf_min    = 12000000,
                .cf_max    = 19200000,  /* s/w policy, h/w capability 38 MHz */
                .vco_min   = 300000000,
-               .vco_max   = 600000000,
+               .vco_max   = 672000000,
                .lock_delay = 300,
                .round_p_to_pdiv = pllre_round_p_to_pdiv,
        },
@@ -5528,13 +5845,14 @@ static struct clk tegra_pll_re_out = {
        .ops       = &tegra_pllre_out_ops,
        .parent    = &tegra_pll_re_vco,
        .reg       = 0x4c4,
-       .max_rate  = 600000000,
+       .max_rate  = 672000000,
 };
 
 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
        /* PLLE special case: use cpcon field to store cml divider value */
        { 336000000, 100000000, 100, 21,  16, 11},
        { 312000000, 100000000, 200, 26,  24, 13},
+       {  12000000, 100000000, 200,  1,  24, 13},
        { 0, 0, 0, 0, 0, 0 },
 };
 
@@ -5774,7 +6092,7 @@ static struct clk_mux_sel mux_sclk[] = {
        { .input = &tegra_clk_m,        .value = 0},
        { .input = &tegra_pll_c_out1,   .value = 1},
        { .input = &tegra_pll_p_out4,   .value = 2},
-       { .input = &tegra_pll_p_out3,   .value = 3},
+       { .input = &tegra_pll_p,        .value = 3},
        { .input = &tegra_pll_p_out2,   .value = 4},
        /* { .input = &tegra_clk_d,     .value = 5}, - no use on tegra11x */
        { .input = &tegra_clk_32k,      .value = 6},
@@ -5889,7 +6207,11 @@ static struct clk tegra_clk_sbus_cmplx = {
                .pclk = &tegra_clk_pclk,
                .hclk = &tegra_clk_hclk,
                .sclk_low = &tegra_pll_p_out2,
+#ifdef CONFIG_TEGRA_PLLM_SCALED
+               .sclk_high = &tegra_pll_c_out1,
+#else
                .sclk_high = &tegra_pll_m_out1,
+#endif
        },
        .rate_change_nh = &sbus_rate_change_nh,
 };
@@ -6028,7 +6350,7 @@ static struct clk_mux_sel mux_clkm_pllp_pllc_pllre[] = {
        { .input = &tegra_clk_m,  .value = 0},
        { .input = &tegra_pll_p,  .value = 1},
        { .input = &tegra_pll_c,  .value = 3},
-       { .input = &tegra_pll_re_out,  .value = 5},
+       { .input = &tegra_pll_re_vco,  .value = 5},
        { 0, 0},
 };
 
@@ -6042,7 +6364,7 @@ static struct clk_mux_sel mux_clkm_48M_pllp_480M[] = {
 
 static struct clk_mux_sel mux_clkm_pllre_clk32_480M_pllc_ref[] = {
        { .input = &tegra_clk_m,      .value = 0},
-       { .input = &tegra_pll_re_out, .value = 1},
+       { .input = &tegra_pll_re_vco, .value = 1},
        { .input = &tegra_clk_32k,    .value = 2},
        { .input = &tegra_pll_u_480M, .value = 3},
        { .input = &tegra_pll_c,      .value = 4},
@@ -6121,7 +6443,13 @@ static struct clk tegra_clk_c3bus = {
        .rate_change_nh = &c3bus_rate_change_nh,
 };
 
+#ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
 static DEFINE_MUTEX(cbus_mutex);
+#define CROSS_CBUS_MUTEX (&cbus_mutex)
+#else
+#define CROSS_CBUS_MUTEX NULL
+#endif
+
 
 static struct clk_mux_sel mux_clk_cbus[] = {
        { .input = &tegra_clk_c2bus, .value = 0},
@@ -6145,7 +6473,7 @@ static struct clk_mux_sel mux_clk_cbus[] = {
                        .client_div = _div,             \
                        .mode = _mode,                  \
                },                                      \
-               .cross_clk_mutex = &cbus_mutex,         \
+               .cross_clk_mutex = CROSS_CBUS_MUTEX,    \
        }
 
 #else
@@ -6262,15 +6590,12 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("hda",       "tegra30-hda",          "hda",          125,    0x428,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("hda2codec_2x",      "tegra30-hda",  "hda2codec",    111,    0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("hda2hdmi",  "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   PERIPH_ON_APB),
-       PERIPH_CLK("sbc1",      "tegra11-spi.0",        NULL,   41,     0x134,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc2",      "tegra11-spi.1",        NULL,   44,     0x118,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc3",      "tegra11-spi.2",        NULL,   46,     0x11c,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc4",      "tegra11-spi.3",        NULL,   68,     0x1b4,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc5",      "tegra11-spi.4",        NULL,   104,    0x3c8,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc6",      "tegra11-spi.5",        NULL,   105,    0x3cc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata_oob",  "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata",      "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata_cold", "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   PERIPH_ON_APB),
+       PERIPH_CLK("sbc1",      "spi-tegra114.0",       NULL,   41,     0x134,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc2",      "spi-tegra114.1",       NULL,   44,     0x118,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc3",      "spi-tegra114.2",       NULL,   46,     0x11c,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc4",      "spi-tegra114.3",       NULL,   68,     0x1b4,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc5",      "spi-tegra114.4",       NULL,   104,    0x3c8,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc6",      "spi-tegra114.5",       NULL,   105,    0x3cc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK_EX("ndflash", "tegra_nand",          NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB,  &tegra_nand_clk_ops),
        PERIPH_CLK("ndspeed",   "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
@@ -6292,7 +6617,7 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("i2c2",      "tegra11-i2c.1",        "div-clk",      54,     0x198,  136000000, mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
        PERIPH_CLK("i2c3",      "tegra11-i2c.2",        "div-clk",      67,     0x1b8,  136000000, mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
        PERIPH_CLK("i2c4",      "tegra11-i2c.3",        "div-clk",      103,    0x3c4,  136000000, mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
-       PERIPH_CLK("i2c5",      "tegra11-i2c.4",        "div-clk",      47,     0x128,  58300000,  mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
+       PERIPH_CLK("i2c5",      "tegra11-i2c.4",        "div-clk",      47,     0x128,  64000000,  mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
        PERIPH_CLK("mipi-cal",  "mipi-cal",             NULL,   56,     0,      60000000,  mux_clk_m,   0),
        PERIPH_CLK("uarta",     "tegra_uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
        PERIPH_CLK("uartb",     "tegra_uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
@@ -6301,8 +6626,8 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("uarte",     "tegra_uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
-       PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
-       PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
+       PERIPH_CLK_EX("vi",     "vi",                   "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
+       PERIPH_CLK("vi_sensor", "vi",                   "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
        PERIPH_CLK("msenc",     "msenc",                NULL,   60,     0x170,  600000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
@@ -6322,12 +6647,12 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK_EX("dsib",   "tegradc.1",            "dsib", 82,     0x4b8,  500000000, mux_plld_out0_plld2_out0,    MUX | PLLD,     &tegra_dsi_clk_ops),
        PERIPH_CLK("dsi1-fixed", "tegradc.0",           "dsi-fixed",    0,      0,      108000000, mux_pllp_out3,       PERIPH_NO_ENB),
        PERIPH_CLK("dsi2-fixed", "tegradc.1",           "dsi-fixed",    0,      0,      108000000, mux_pllp_out3,       PERIPH_NO_ENB),
-       PERIPH_CLK("csi",       "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0),
-       PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
-       PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
-       PERIPH_CLK("cilab",     "tegra_camera",         "cilab", 144,   0x614,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
-       PERIPH_CLK("cilcd",     "tegra_camera",         "cilcd", 145,   0x618,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
-       PERIPH_CLK("cile",      "tegra_camera",         "cile",  146,   0x61c,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
+       PERIPH_CLK("csi",       "vi",                   "csi",  52,     0,      102000000, mux_pllp_out3,               0),
+       PERIPH_CLK("isp",       "vi",                   "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
+       PERIPH_CLK("csus",      "vi",                   "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
+       PERIPH_CLK("cilab",     "vi",                   "cilab", 144,   0x614,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
+       PERIPH_CLK("cilcd",     "vi",                   "cilcd", 145,   0x618,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
+       PERIPH_CLK("cile",      "vi",                   "cile",  146,   0x61c,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
        PERIPH_CLK("dsialp",    "tegradc.0",            "dsialp", 147,  0x620,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
        PERIPH_CLK("dsiblp",    "tegradc.1",            "dsiblp", 148,  0x624,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
 
@@ -6355,8 +6680,10 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("usb2.sclk", "tegra-ehci.1",         "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("usb3.sclk", "tegra-ehci.2",         "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("wake.sclk", "wake_sclk",            "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("camera.sclk",       "vi",           "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("mon.avp",   "tegra_actmon",         "avp",  &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("cap.sclk",  "cap_sclk",             NULL,   &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
+       SHARED_CLK("cap.throttle.sclk", "cap_throttle", NULL,   &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
        SHARED_CLK("floor.sclk", "floor_sclk",          NULL,   &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("override.sclk", "override_sclk",    NULL,   &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
        SHARED_CLK("sbc1.sclk", "tegra11-spi.0",        "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
@@ -6377,31 +6704,37 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("usb3.emc",  "tegra-ehci.2",         "emc",  &tegra_clk_emc, NULL, 0, 0),
        SHARED_CLK("mon.emc",   "tegra_actmon",         "emc",  &tegra_clk_emc, NULL, 0, 0),
        SHARED_CLK("cap.emc",   "cap.emc",              NULL,   &tegra_clk_emc, NULL, 0, SHARED_CEILING),
+       SHARED_CLK("cap.throttle.emc", "cap_throttle",  NULL,   &tegra_clk_emc, NULL, 0, SHARED_CEILING),
        SHARED_CLK("3d.emc",    "tegra_gr3d",           "emc",  &tegra_clk_emc, NULL, 0, 0),
        SHARED_CLK("2d.emc",    "tegra_gr2d",           "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("msenc.emc", "tegra_msenc",          "emc",  &tegra_clk_emc, NULL, 0, 0),
+       SHARED_CLK("msenc.emc", "tegra_msenc",          "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
        SHARED_CLK("tsec.emc",  "tegra_tsec",           "emc",  &tegra_clk_emc, NULL, 0, 0),
        SHARED_CLK("sdmmc4.emc", "sdhci-tegra.3",       "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("camera.emc", "tegra_camera",        "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
+       SHARED_CLK("camera.emc", "vi",                  "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
        SHARED_CLK("iso.emc",   "iso",                  "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
        SHARED_CLK("floor.emc", "floor.emc",            NULL,   &tegra_clk_emc, NULL, 0, 0),
        SHARED_CLK("override.emc", "override.emc",      NULL,   &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE),
        SHARED_CLK("edp.emc",   "edp.emc",              NULL,   &tegra_clk_emc, NULL, 0, SHARED_CEILING),
+       SHARED_CLK("battery.emc", "battery_edp",        "emc",  &tegra_clk_emc, NULL, 0, SHARED_CEILING),
 
 #ifdef CONFIG_TEGRA_DUAL_CBUS
        DUAL_CBUS_CLK("3d.cbus",        "tegra_gr3d",           "gr3d", &tegra_clk_c2bus, "3d",  0, 0),
        DUAL_CBUS_CLK("2d.cbus",        "tegra_gr2d",           "gr2d", &tegra_clk_c2bus, "2d",  0, 0),
        DUAL_CBUS_CLK("epp.cbus",       "tegra_gr2d",           "epp",  &tegra_clk_c2bus, "epp", 0, 0),
        SHARED_CLK("cap.c2bus",         "cap.c2bus",            NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.throttle.c2bus", "cap_throttle",        NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
        SHARED_CLK("floor.c2bus",       "floor.c2bus",          NULL,   &tegra_clk_c2bus, NULL,  0, 0),
        SHARED_CLK("override.c2bus",    "override.c2bus",       NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_OVERRIDE),
        SHARED_CLK("edp.c2bus",         "edp.c2bus",            NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("battery.c2bus",     "battery_edp",          "gpu",  &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.profile.c2bus", "profile.c2bus",        NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
 
        DUAL_CBUS_CLK("msenc.cbus",     "tegra_msenc",          "msenc",  &tegra_clk_c3bus, "msenc", 0, 0),
        DUAL_CBUS_CLK("tsec.cbus",      "tegra_tsec",           "tsec",   &tegra_clk_c3bus, "tsec", 0, 0),
        DUAL_CBUS_CLK("vde.cbus",       "tegra-avp",            "vde",    &tegra_clk_c3bus, "vde", 0, 0),
        DUAL_CBUS_CLK("se.cbus",        "tegra11-se",           NULL,     &tegra_clk_c3bus, "se",  0, 0),
        SHARED_CLK("cap.c3bus",         "cap.c3bus",            NULL,   &tegra_clk_c3bus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.throttle.c3bus", "cap_throttle",        NULL,   &tegra_clk_c3bus, NULL,  0, SHARED_CEILING),
        SHARED_CLK("floor.c3bus",       "floor.c3bus",          NULL,   &tegra_clk_c3bus, NULL,  0, 0),
        SHARED_CLK("override.c3bus",    "override.c3bus",       NULL,   &tegra_clk_c3bus, NULL,  0, SHARED_OVERRIDE),
 #else
@@ -6413,15 +6746,18 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("vde.cbus",  "tegra-avp",            "vde",  &tegra_clk_cbus, "vde", 0, 0),
        SHARED_CLK("se.cbus",   "tegra11-se",           NULL,   &tegra_clk_cbus, "se",  0, 0),
        SHARED_CLK("cap.cbus",  "cap.cbus",             NULL,   &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.throttle.cbus", "cap_throttle", NULL,   &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
        SHARED_CLK("floor.cbus", "floor.cbus",          NULL,   &tegra_clk_cbus, NULL,  0, 0),
        SHARED_CLK("override.cbus", "override.cbus",    NULL,   &tegra_clk_cbus, NULL,  0, SHARED_OVERRIDE),
        SHARED_CLK("edp.cbus",  "edp.cbus",             NULL,   &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("battery.cbus", "battery_edp",       "gpu",  &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.profile.cbus", "profile.cbus",  NULL,   &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
 #endif
 };
 
 
 /* XUSB clocks */
-#define XUSB_ID "tegra_xhci"
+#define XUSB_ID "tegra-xhci"
 
 static struct clk tegra_xusb_source_clks[] = {
        PERIPH_CLK("xusb_host_src",     XUSB_ID, "host_src",    143,    0x600,  120000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
@@ -6496,6 +6832,7 @@ struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
+       CLK_DUPLICATE("usbd", XUSB_ID, "utmip-pad"),
        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
@@ -6523,11 +6860,14 @@ struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
        CLK_DUPLICATE("bsea", "nvavp", "bsea"),
        CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
+       CLK_DUPLICATE("clk_m", NULL, "apb_pclk"),
        CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
        CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
        CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
        CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
        CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
+       CLK_DUPLICATE("cl_dvfs_soc", "tegra11-i2c.4", NULL),
+       CLK_DUPLICATE("cl_dvfs_ref", "tegra11-i2c.4", NULL),
        CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL),
        CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL),
        CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL),
@@ -6707,6 +7047,49 @@ static void tegra11_init_one_clock(struct clk *c)
        clkdev_add(&c->lookup);
 }
 
+/* Direct access to CPU clock sources fot CPU idle driver */
+int tegra11_cpu_g_idle_rate_exchange(unsigned long *rate)
+{
+       int ret = 0;
+       struct clk *dfll = tegra_clk_cpu_cmplx.parent->u.cpu.dynamic;
+       unsigned long old_rate, new_rate, flags;
+
+       if (!dfll || !tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail))
+               return -EPERM;
+
+       /* Clipping min to oscillator rate is pretty much arbitrary */
+       new_rate = max(*rate, tegra_clk_m.rate);
+
+       clk_lock_save(dfll, &flags);
+
+       old_rate = clk_get_rate_locked(dfll);
+       *rate = old_rate;
+       if (new_rate != old_rate)
+               ret = clk_set_rate_locked(dfll, new_rate);
+
+       clk_unlock_restore(dfll, &flags);
+       return ret;
+}
+
+int tegra11_cpu_lp_idle_rate_exchange(unsigned long *rate)
+{
+       int ret = 0;
+       struct clk *backup = tegra_clk_cpu_cmplx.parent->u.cpu.backup;
+       unsigned long old_rate, flags;
+       unsigned long new_rate = min(
+               *rate, tegra_clk_cpu_cmplx.parent->u.cpu.backup_rate);
+
+       clk_lock_save(backup, &flags);
+
+       old_rate = clk_get_rate_locked(backup);
+       *rate = old_rate;
+       if (new_rate != old_rate)
+               ret = clk_set_rate_locked(backup, new_rate);
+
+       clk_unlock_restore(backup, &flags);
+       return ret;
+}
+
 void tegra_edp_throttle_cpu_now(u8 factor)
 {
        /* empty definition for tegra11 */
@@ -6724,15 +7107,41 @@ bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
         * respective muxes statically.
         */
 
-       /* pll_c can be used as a clock source for EMC only on configuration
-          with dual cbus, or as a clock source for single cbus */
-       if (p == &tegra_pll_c) {
+       /*
+        * In configuration with dual cbus pll_c can be used as a scaled clock
+        * source for EMC only when pll_m is fixed, or as a general fixed rate
+        * clock source for EMC and other peripherals if pll_m is scaled. In
+        * configuration with single cbus pll_c can be used as a scaled cbus
+        * clock source only. No direct use for pll_c by super clocks.
+        */
+       if ((p == &tegra_pll_c) && (c != &tegra_pll_c_out1)) {
+               if (c->ops == &tegra_super_ops)
+                       return false;
 #ifdef CONFIG_TEGRA_DUAL_CBUS
+#ifndef CONFIG_TEGRA_PLLM_SCALED
                return c->flags & PERIPH_EMC_ENB;
+#endif
 #else
                return c->flags & PERIPH_ON_CBUS;
 #endif
        }
+
+       /*
+        * In any configuration pll_m must not be used as a clock source for
+        * cbus modules. If pll_m is scaled it can be used as EMC source only.
+        * Otherwise fixed rate pll_m can be used as clock source for EMC and
+        * other peripherals. No direct use for pll_m by super clocks.
+        */
+       if ((p == &tegra_pll_m) && (c != &tegra_pll_m_out1)) {
+               if (c->ops == &tegra_super_ops)
+                       return false;
+
+               if (c->flags & PERIPH_ON_CBUS)
+                       return false;
+#ifdef CONFIG_TEGRA_PLLM_SCALED
+               return c->flags & PERIPH_EMC_ENB;
+#endif
+       }
        return true;
 }
 
@@ -7051,6 +7460,7 @@ static void tegra11_clk_resume(void)
        tegra11_pllcx_clk_resume_enable(&tegra_pll_c3);
        tegra11_pllxc_clk_resume_enable(&tegra_pll_c);
        tegra11_pllxc_clk_resume_enable(&tegra_pll_x);
+       tegra11_pllre_clk_resume_enable(&tegra_pll_re_out);
 
        plla_base = *ctx++;
        clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
@@ -7157,6 +7567,9 @@ static void tegra11_clk_resume(void)
        p = &tegra_pll_x;
        if (p->state == OFF)
                tegra11_pllxc_clk_disable(p);
+       p = &tegra_pll_re_vco;
+       if (p->state == OFF)
+               tegra11_pllre_clk_disable(p);
 
        clk_writel(plla_base, tegra_pll_a.reg + PLL_BASE);
        clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE);
@@ -7190,6 +7603,7 @@ static void tegra11_clk_resume(void)
        tegra_emc_timing_invalidate();
 
        tegra11_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */
+       tegra11_plle_clk_resume(&tegra_pll_e); /* Restore plle parent as pll_re_vco */
        tegra11_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */
 }
 
@@ -7199,10 +7613,60 @@ static struct syscore_ops tegra_clk_syscore_ops = {
 };
 #endif
 
+/* Tegra11 CPU clock and reset control functions */
+static void tegra11_wait_cpu_in_reset(u32 cpu)
+{
+       unsigned int reg;
+
+       do {
+               reg = readl(reg_clk_base +
+                           TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+               cpu_relax();
+       } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
+
+       return;
+}
+
+static void tegra11_put_cpu_in_reset(u32 cpu)
+{
+       writel(CPU_RESET(cpu),
+              reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+       dmb();
+}
+
+static void tegra11_cpu_out_of_reset(u32 cpu)
+{
+       writel(CPU_RESET(cpu),
+              reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+       wmb();
+}
+
+static void tegra11_enable_cpu_clock(u32 cpu)
+{
+       unsigned int reg;
+
+       writel(CPU_CLOCK(cpu),
+              reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+       reg = readl(reg_clk_base +
+                   TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+}
 static void tegra11_disable_cpu_clock(u32 cpu)
 {
 }
 
+static struct tegra_cpu_car_ops tegra11_cpu_car_ops = {
+       .wait_for_reset = tegra11_wait_cpu_in_reset,
+       .put_in_reset   = tegra11_put_cpu_in_reset,
+       .out_of_reset   = tegra11_cpu_out_of_reset,
+       .enable_clock   = tegra11_enable_cpu_clock,
+       .disable_clock  = tegra11_disable_cpu_clock,
+};
+
+static void __init tegra11_cpu_car_ops_init(void)
+{
+       tegra_cpu_car_ops = &tegra11_cpu_car_ops;
+}
+
 void __init tegra11x_init_clocks(void)
 {
        int i;
@@ -7214,18 +7678,6 @@ void __init tegra11x_init_clocks(void)
        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
                tegra11_init_one_clock(&tegra_list_clks[i]);
 
-       for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
-               c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
-               if (!c) {
-                       pr_err("%s: Unknown duplicate clock %s\n", __func__,
-                               tegra_clk_duplicates[i].name);
-                       continue;
-               }
-
-               tegra_clk_duplicates[i].lookup.clk = c;
-               clkdev_add(&tegra_clk_duplicates[i].lookup);
-       }
-
        for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
                tegra11_init_one_clock(&tegra_sync_source_list[i]);
        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
@@ -7243,11 +7695,27 @@ void __init tegra11x_init_clocks(void)
        for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
                tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]);
 
+       for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+               c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+               if (!c) {
+                       pr_err("%s: Unknown duplicate clock %s\n", __func__,
+                               tegra_clk_duplicates[i].name);
+                       continue;
+               }
+
+               tegra_clk_duplicates[i].lookup.clk = c;
+               clkdev_add(&tegra_clk_duplicates[i].lookup);
+       }
+
        /* Initialize to default */
        tegra_init_cpu_edp_limits(0);
 
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
        /* To be ready for DFLL late init */
        tegra_dfll_cpu.ops->init = tegra11_dfll_cpu_late_init;
+#endif
+
+       tegra11_cpu_car_ops_init();
 
 #ifdef CONFIG_PM_SLEEP
        register_syscore_ops(&tegra_clk_syscore_ops);