/*
* arch/arm/mach-tegra/tegra11_clocks.c
*
- * Copyright (C) 2011-2013 NVIDIA Corporation
+ * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <mach/edp.h>
#include <mach/hardware.h>
#include <mach/mc.h>
+#include <mach/powergate.h>
#include "clock.h"
#include "fuse.h"
#define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
#define PLLE_SS_INC_SHIFT 16
#define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
+#define PLLE_SS_CNTL_INVERT (0x1 << 15)
+#define PLLE_SS_CNTL_CENTER (0x1 << 14)
#define PLLE_SS_CNTL_SSC_BYP (0x1 << 12)
#define PLLE_SS_CNTL_INTERP_RESET (0x1 << 11)
#define PLLE_SS_CNTL_BYPASS_SS (0x1 << 10)
#define USB_PLLS_USE_LOCKDET (1<<6)
#define USB_PLLS_ENABLE_SWCTL ((1<<2) | (1<<0))
+/* CPU clock trimmers */
+#define CPU_FINETRIM_BYP 0x4d0
+#define CPU_FINETRIM_SELECT 0x4d4
+#define CPU_FINETRIM_DR 0x4d8
+#define CPU_FINETRIM_DF 0x4dc
+#define CPU_FINETRIM_F 0x4e0
+#define CPU_FINETRIM_R 0x4e4
+
/* DFLL */
#define DFLL_BASE 0x2f4
#define DFLL_BASE_RESET (1<<0)
c->mul = 2;
c->div = 2;
- /* Make sure 7.1 divider is 1:1, clear s/w skipper control */
- /* FIXME: set? preserve? thermal h/w skipper control */
+ /*
+ * Make sure 7.1 divider is 1:1; clear h/w skipper control -
+ * it will be enabled by soctherm later
+ */
val = clk_readl(c->reg + SUPER_CLK_DIVIDER);
BUG_ON(val & SUPER_CLOCK_DIV_U71_MASK);
val = 0;
}
}
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
ret = clk_set_parent(c->parent, dfll);
if (ret) {
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
pr_err("Failed to switch cpu to %s\n", dfll->name);
return ret;
}
/* prevent legacy dvfs voltage scaling */
tegra_dvfs_dfll_mode_set(c->dvfs, rate);
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
}
return 0;
}
rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost);
pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main;
+ dfll_rate_min = max(rate, dfll_rate_min);
+
+ /* set target rate last time in dfll mode */
+ if (old_rate != dfll_rate_min) {
+ ret = tegra_dvfs_set_rate(c, dfll_rate_min);
+ if (!ret)
+ ret = clk_set_rate(dfll, dfll_rate_min);
+
+ if (ret) {
+ pr_err("Failed to set cpu rate %lu on source %s\n",
+ dfll_rate_min, dfll->name);
+ return ret;
+ }
+ }
+ /* unlock dfll - release volatge rail control */
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
if (ret) {
pr_err("Failed to unlock %s\n", dfll->name);
}
/* restore legacy dvfs operations and set appropriate voltage */
- ret = tegra_dvfs_dfll_mode_clear(c->dvfs, max(rate, dfll_rate_min));
+ ret = tegra_dvfs_dfll_mode_clear(c->dvfs, dfll_rate_min);
if (ret) {
pr_err("Failed to set cpu rail for rate %lu\n", rate);
goto back_to_dfll;
if (old_rate <= rate)
tegra_dvfs_set_rate(c, rate);
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
return 0;
back_to_dfll:
tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
tegra_dvfs_dfll_mode_set(c->dvfs, old_rate);
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
return ret;
}
if (c->dvfs) {
if (!c->dvfs->dvfs_rail)
return -ENOSYS;
- else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate)) {
+ else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate) &&
+ (c->boot_rate < rate)) {
WARN(1, "Increasing CPU rate while regulator is not"
" ready is not allowed\n");
return -ENOSYS;
const struct clk_mux_sel *sel;
unsigned long rate = clk_get_rate(c->parent);
struct clk *dfll = c->parent->u.cpu.dynamic ? : p->u.cpu.dynamic;
+ struct clk *p_source_old = NULL;
struct clk *p_source;
pr_debug("%s: %s %s\n", __func__, c->name, p->name);
return 0; /* already switched - exit */
}
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
if (c->parent->parent->parent == dfll) {
/* G (DFLL selected as clock source) => LP switch:
* turn DFLL into open loop mode ("release" VDD_CPU rail)
ret = clk_set_rate(p_source, rate);
if (ret)
goto abort;
- } else if (p->parent->parent == dfll) {
+ } else if ((p->parent->parent == dfll) || ((p->u.cpu.dynamic == dfll) &&
+ (dfll->state != UNINITIALIZED) && use_dfll)) {
/* LP => G (DFLL selected as clock source) switch:
* set DFLL rate ready (DFLL is still disabled)
* (set target p_source as dfll, G source is already selected)
*/
p_source = dfll;
- ret = clk_set_rate(p_source, rate);
+ ret = clk_set_rate(dfll,
+ tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail) ? rate :
+ max(rate, p->dvfs->dfll_data.use_dfll_rate_min));
+ if (ret)
+ goto abort;
+
+ ret = tegra_dvfs_rail_dfll_mode_set_cold(tegra_cpu_rail);
if (ret)
goto abort;
+
} else
- /* DFLL is not selcted on either side of the switch:
+ /* DFLL is not selected on either side of the switch:
* set target p_source equal to current clock source
*/
p_source = c->parent->parent->parent;
/* Switch new parent to target clock source if necessary */
if (p->parent->parent != p_source) {
+ clk_enable(p->parent->parent);
+ clk_enable(p->parent);
+ p_source_old = p->parent->parent;
ret = clk_set_parent(p->parent, p_source);
if (ret) {
pr_err("%s: Failed to set parent %s for %s\n",
/* Disabling old parent scales old mode voltage rail */
if (c->refcnt)
clk_disable(c->parent);
+ if (p_source_old) {
+ clk_disable(p->parent);
+ clk_disable(p_source_old);
+ }
clk_reparent(c, p);
- /* Lock DFLL now (resume closed loop VDD_CPU control) */
- if (p_source == dfll)
- tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+ /*
+ * Lock DFLL now (resume closed loop VDD_CPU control).
+ * G CPU operations are always resumed on DFLL if it can be used, even
+ * when autoswitch between PLL and DFLL is allowed, and resume rate is
+ * low enough to run on PLL. This makes CPU clock source ready for
+ * speedy ramp with cl_dvfs controlling volatge (and that ramp is the
+ * most likely reason for going to G CPU in the 1st place)
+ */
+ if (p_source == dfll) {
+ if (tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail)) {
+ tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+ } else {
+ clk_set_rate(dfll, rate);
+ tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+ tegra_dvfs_dfll_mode_set(p->dvfs, rate);
+ }
+ }
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
return 0;
abort:
/* Re-lock DFLL if necessary after aborted switch */
- if (c->parent->parent->parent == dfll)
+ if (c->parent->parent->parent == dfll) {
+ clk_set_rate(dfll, rate);
tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+ }
+ if (p_source_old) {
+ clk_disable(p->parent);
+ clk_disable(p_source_old);
+ }
+ tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
+
pr_err("%s: aborted switch from %s to %s\n",
__func__, c->parent->name, p->name);
return ret;
#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
#if USE_PLL_LOCK_BITS
int i;
+ u32 val = 0;
+
for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) {
udelay(PLL_PRE_LOCK_DELAY);
- if ((clk_readl(lock_reg) & lock_bits) == lock_bits) {
+ val = clk_readl(lock_reg);
+ if ((val & lock_bits) == lock_bits) {
udelay(PLL_POST_LOCK_DELAY);
return 0;
}
}
- pr_err("Timed out waiting for lock bit on pll %s\n", c->name);
- return -1;
+
+ /* PLLCX lock bits may fluctuate after the lock - don't report timeout
+ in this case (phase lock bit happens to uniquely identify PLLCX) */
+ if (lock_bits & PLLCX_BASE_PHASE_LOCK) {
+ pr_debug("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+ c->name, lock_reg, val);
+ return 0;
+ } else if ((c->flags & PLLD) &&
+ tegra_powergate_check_clamping(TEGRA_POWERGATE_DISA)) {
+ pr_debug("Waiting for %s lock.\n", c->name);
+ } else {
+ pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+ c->name, lock_reg, val);
+ return -ETIMEDOUT;
+ }
#endif
udelay(c->u.pll.lock_delay);
#endif
return c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
}
+/* Special comparison frequency selection for PLLD at 12MHz refrence rate */
+unsigned long get_pll_cfreq_special(struct clk *c, unsigned long input_rate,
+ unsigned long rate, unsigned long *vco)
+{
+ if (!(c->flags & PLLD) || (input_rate != 12000000))
+ return 0;
+
+ *vco = c->u.pll.vco_min;
+
+ if (rate <= 250000000)
+ return 4000000;
+ else if (rate <= 500000000)
+ return 2000000;
+ else
+ return 1000000;
+}
+
+/* Common comparison frequency selection */
+unsigned long get_pll_cfreq_common(struct clk *c, unsigned long input_rate,
+ unsigned long rate, unsigned long *vco)
+{
+ unsigned long cfreq = 0;
+
+ switch (input_rate) {
+ case 12000000:
+ case 26000000:
+ cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
+ break;
+ case 13000000:
+ cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
+ break;
+ case 16800000:
+ case 19200000:
+ cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
+ break;
+ default:
+ if (c->parent->flags & DIV_U71_FIXED) {
+ /* PLLP_OUT1 rate is not in PLLA table */
+ pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
+ __func__, c->name, input_rate, rate);
+ cfreq = input_rate/(input_rate/1000000);
+ break;
+ }
+ pr_err("%s: Unexpected reference rate %lu\n",
+ __func__, input_rate);
+ BUG();
+ }
+
+ /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */
+ *vco = max(200 * cfreq, c->u.pll.vco_min);
+ return cfreq;
+}
+
static int tegra11_pll_clk_set_rate(struct clk *c, unsigned long rate)
{
u32 val, p_div, old_base;
BUG_ON(c->flags & PLLU);
sel = &cfg;
- switch (input_rate) {
- case 12000000:
- case 26000000:
- cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
- break;
- case 13000000:
- cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
- break;
- case 16800000:
- case 19200000:
- cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
- break;
- default:
- if (c->parent->flags & DIV_U71_FIXED) {
- /* PLLP_OUT1 rate is not in PLLA table */
- pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
- __func__, c->name, input_rate, rate);
- cfreq = input_rate/(input_rate/1000000);
- break;
- }
- pr_err("%s: Unexpected reference rate %lu\n",
- __func__, input_rate);
- BUG();
- }
+ /* If available, use pll specific algorithm to select comparison
+ frequency, and vco target */
+ cfreq = get_pll_cfreq_special(c, input_rate, rate, &vco);
+ if (!cfreq)
+ cfreq = get_pll_cfreq_common(c, input_rate, rate, &vco);
- /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */
- vco = max(200 * cfreq, c->u.pll.vco_min);
for (cfg.output_rate = rate; cfg.output_rate < vco; p_div++)
cfg.output_rate <<= 1;
c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
#if USE_PLLE_SS
val = clk_readl(PLLE_SS_CTRL);
+ val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
val &= ~PLLE_SS_COEFFICIENTS_MASK;
val |= PLLE_SS_COEFFICIENTS_VAL;
clk_writel(val, PLLE_SS_CTRL);
* basically cl-dvfs wrappers.
*/
-#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
/* DFLL operations */
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+static void tune_cpu_trimmers(bool trim_high)
+{
+ if (trim_high) {
+ clk_writel(0, CPU_FINETRIM_SELECT);
+ clk_writel(0, CPU_FINETRIM_DR);
+ clk_writel(0, CPU_FINETRIM_R);
+ } else {
+ clk_writel(0x3F, CPU_FINETRIM_SELECT);
+ clk_writel(0x3F, CPU_FINETRIM_DR);
+ clk_writel(0xFFF, CPU_FINETRIM_R);
+ }
+ wmb();
+ clk_readl(CPU_FINETRIM_R);
+}
+#endif
+
static void __init tegra11_dfll_cpu_late_init(struct clk *c)
{
#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
int ret;
- struct clk *cpu = tegra_get_clock_by_name("cpu");
+ struct clk *cpu = tegra_get_clock_by_name("cpu_g");
+
+ if (!cpu || !cpu->dvfs) {
+ pr_err("%s: CPU dvfs is not present\n", __func__);
+ return;
+ }
+ if (cpu->dvfs->speedo_id > 0) /* A01P and above parts */
+ tegra_dvfs_set_dfll_tune_trimmers(cpu->dvfs, tune_cpu_trimmers);
#ifdef CONFIG_TEGRA_FPGA_PLATFORM
u32 netlist, patchid;
c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device);
use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
- tegra_dvfs_set_dfll_range(cpu->parent->dvfs, use_dfll);
+ tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll);
+ tegra_cl_dvfs_debug_init(c);
pr_info("Tegra CPU DFLL is initialized\n");
}
#endif
}
-#endif
+
+static void tegra11_dfll_clk_init(struct clk *c)
+{
+ c->ops->init = tegra11_dfll_cpu_late_init;
+}
static int tegra11_dfll_clk_enable(struct clk *c)
{
#endif
static struct clk_ops tegra_dfll_ops = {
+ .init = tegra11_dfll_clk_init,
.enable = tegra11_dfll_clk_enable,
.disable = tegra11_dfll_clk_disable,
.set_rate = tegra11_dfll_clk_set_rate,
static void tegra11_pll_div_clk_init(struct clk *c)
{
if (c->flags & DIV_U71) {
- u32 divu71;
- u32 val = clk_readl(c->reg);
+ u32 val, divu71;
+ if (c->parent->state == OFF)
+ c->ops->disable(c);
+
+ val = clk_readl(c->reg);
val >>= c->reg_shift;
c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
if (!(val & PLL_OUT_RESET_DISABLE))
c->parent = mux->input;
} else {
if (c->flags & PLLU) {
- /* for xusb_hs clock enforce PLLU source during init */
+ /* for xusb_hs clock enforce SS div2 source */
val &= ~periph_clk_source_mask(c);
- val |= c->inputs[0].value << periph_clk_source_shift(c);
clk_writel_delay(val, c->reg);
}
c->parent = c->inputs[0].input;
clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) {
if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) {
- udelay(5); /* reset propagation delay */
+ udelay(RESET_PROPAGATION_DELAY);
clk_writel(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_RST_CLR_REG(c));
}
}
.reset = &tegra11_periph_clk_reset,
};
+/* 1x shared bus ops */
+static long tegra11_1xbus_round_updown(struct clk *c, unsigned long rate,
+ bool up)
+{
+ int divider;
+ unsigned long source_rate, round_rate;
+ struct clk *new_parent;
+
+ rate = max(rate, c->min_rate);
+
+ new_parent = (rate <= c->u.periph.threshold) ?
+ c->u.periph.pll_low : c->u.periph.pll_high;
+ source_rate = clk_get_rate(new_parent);
+
+ divider = clk_div71_get_divider(source_rate, rate, c->flags,
+ up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
+
+ if (divider < 0)
+ return c->min_rate;
+
+ round_rate = source_rate * 2 / (divider + 2);
+
+ if (round_rate > c->max_rate) {
+ divider += c->flags & DIV_U71_INT ? 2 : 1;
+#if !DIVIDER_1_5_ALLOWED
+ divider = max(2, divider);
+#endif
+ round_rate = source_rate * 2 / (divider + 2);
+ }
+
+ if (new_parent == c->u.periph.pll_high) {
+ /* Prevent oscillation across threshold */
+ if (round_rate <= c->u.periph.threshold)
+ round_rate = c->u.periph.threshold;
+ }
+ return round_rate;
+}
+
+static long tegra11_1xbus_round_rate(struct clk *c, unsigned long rate)
+{
+ return tegra11_1xbus_round_updown(c, rate, true);
+}
+
+static int tegra11_1xbus_set_rate(struct clk *c, unsigned long rate)
+{
+ /* Compensate rate truncating during rounding */
+ return tegra11_periph_clk_set_rate(c, rate + 1);
+}
+
+static int tegra11_clk_1xbus_update(struct clk *c)
+{
+ int ret;
+ struct clk *new_parent;
+ unsigned long rate, old_rate;
+
+ if (detach_shared_bus)
+ return 0;
+
+ rate = tegra11_clk_shared_bus_update(c, NULL, NULL, NULL);
+
+ old_rate = clk_get_rate_locked(c);
+ pr_debug("\n1xbus %s: rate %lu on parent %s: new request %lu\n",
+ c->name, old_rate, c->parent->name, rate);
+ if (rate == old_rate)
+ return 0;
+
+ if (!c->u.periph.min_div_low || !c->u.periph.min_div_high) {
+ unsigned long r, m = c->max_rate;
+ r = clk_get_rate(c->u.periph.pll_low);
+ c->u.periph.min_div_low = DIV_ROUND_UP(r, m) * c->mul;
+ r = clk_get_rate(c->u.periph.pll_high);
+ c->u.periph.min_div_high = DIV_ROUND_UP(r, m) * c->mul;
+ }
+
+ new_parent = (rate <= c->u.periph.threshold) ?
+ c->u.periph.pll_low : c->u.periph.pll_high;
+
+ /*
+ * The transition procedure below is guaranteed to switch to the target
+ * parent/rate without violation of max clock limits. It would attempt
+ * to switch without dip in bus rate if it is possible, but this cannot
+ * be guaranteed (example: switch from 408 MHz : 1 to 624 MHz : 2 with
+ * maximum bus limit 408 MHz will be executed as 408 => 204 => 312 MHz,
+ * and there is no way to avoid rate dip in this case).
+ */
+ if (new_parent != c->parent) {
+ int interim_div = 0;
+ /* Switching to pll_high may over-clock bus if current divider
+ is too small - increase divider to safe value */
+ if ((new_parent == c->u.periph.pll_high) &&
+ (c->div < c->u.periph.min_div_high))
+ interim_div = c->u.periph.min_div_high;
+
+ /* Switching to pll_low may dip down rate if current divider
+ is too big - decrease divider as much as we can */
+ if ((new_parent == c->u.periph.pll_low) &&
+ (c->div > c->u.periph.min_div_low))
+ interim_div = c->u.periph.min_div_low;
+
+ if (interim_div) {
+ u64 interim_rate = old_rate * c->div;
+ do_div(interim_rate, interim_div);
+ ret = clk_set_rate_locked(c, interim_rate);
+ if (ret) {
+ pr_err("Failed to set %s rate to %lu\n",
+ c->name, (unsigned long)interim_rate);
+ return ret;
+ }
+ pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
+ clk_get_rate_locked(c), c->parent->name);
+ }
+
+ ret = clk_set_parent_locked(c, new_parent);
+ if (ret) {
+ pr_err("Failed to set %s parent %s\n",
+ c->name, new_parent->name);
+ return ret;
+ }
+
+ old_rate = clk_get_rate_locked(c);
+ pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
+ old_rate, c->parent->name);
+ if (rate == old_rate)
+ return 0;
+ }
+
+ ret = clk_set_rate_locked(c, rate);
+ if (ret) {
+ pr_err("Failed to set %s rate to %lu\n", c->name, rate);
+ return ret;
+ }
+ pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
+ clk_get_rate_locked(c), c->parent->name);
+ return 0;
+
+}
+
+static struct clk_ops tegra_1xbus_clk_ops = {
+ .init = &tegra11_periph_clk_init,
+ .enable = &tegra11_periph_clk_enable,
+ .disable = &tegra11_periph_clk_disable,
+ .set_parent = &tegra11_periph_clk_set_parent,
+ .set_rate = &tegra11_1xbus_set_rate,
+ .round_rate = &tegra11_1xbus_round_rate,
+ .reset = &tegra11_periph_clk_reset,
+ .shared_bus_update = &tegra11_clk_1xbus_update,
+};
#if !defined(CONFIG_TEGRA_SIMULATION_PLATFORM)
/* msenc clock propagation WAR for bug 1005168 */
.reset = &tegra11_periph_clk_reset,
};
+/* xusb common clock gate - enabled on init and never disabled */
+static void tegra11_xusb_gate_clk_init(struct clk *c)
+{
+ tegra11_periph_clk_enable(c);
+}
+
+static struct clk_ops tegra_xusb_gate_clk_ops = {
+ .init = tegra11_xusb_gate_clk_init,
+};
+
/* pciex clock support only reset function */
static struct clk_ops tegra_pciex_clk_ops = {
.reset = tegra11_periph_clk_reset,
static long tegra11_emc_clk_round_updown(struct clk *c, unsigned long rate,
bool up)
{
- long new_rate = max(rate, c->min_rate);
+ unsigned long new_rate = max(rate, c->min_rate);
new_rate = tegra_emc_round_rate_updown(new_rate, up);
- if (new_rate < 0)
+ if (IS_ERR_VALUE(new_rate))
new_rate = c->max_rate;
return new_rate;
return -EINVAL;
}
- if (backup_rate < old_rate) /* skip lowering voltage */
- bus->auto_dvfs = false;
- ret = clk_set_rate_locked(bus, backup_rate);
- bus->auto_dvfs = true;
+ /* set volatge for backup rate if going up */
+ if (backup_rate > old_rate) {
+ ret = tegra_dvfs_set_rate(bus, backup_rate);
+ if (ret) {
+ pr_err("%s: dvfs failed on %s rate %lu\n",
+ __func__, bus->name, backup_rate);
+ return -EINVAL;
+ }
+ }
+
+ trace_clock_set_rate(bus->name, backup_rate, 0);
+ ret = bus->ops->set_rate(bus, backup_rate);
if (ret) {
pr_err("%s: Failed to backup %s for rate %lu\n",
__func__, bus->name, rate);
return -EINVAL;
}
+ clk_rate_change_notify(bus, backup_rate);
}
if (p->refcnt) {
pr_err("%s: %s has other than emc child\n",
unsigned long top_rate = 0;
unsigned long rate = bus->min_rate;
unsigned long bw = 0;
+ unsigned long iso_bw = 0;
unsigned long ceiling = bus->max_rate;
- u8 emc_bw_efficiency = tegra_emc_bw_efficiency;
+ unsigned long ceiling_but_iso = bus->max_rate;
+ u32 usage_flags = 0;
list_for_each_entry(c, &bus->shared_bus_list,
u.shared_bus_user.node) {
* bus just because ceiling is set.
*/
if (c->u.shared_bus_user.enabled ||
- (c->u.shared_bus_user.mode == SHARED_CEILING)) {
+ (c->u.shared_bus_user.mode == SHARED_CEILING) ||
+ (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) {
unsigned long request_rate = c->u.shared_bus_user.rate *
(c->div ? : 1);
+ usage_flags |= c->u.shared_bus_user.usage_flag;
switch (c->u.shared_bus_user.mode) {
+ case SHARED_ISO_BW:
+ iso_bw += request_rate;
+ if (iso_bw > bus->max_rate)
+ iso_bw = bus->max_rate;
+ /* fall thru */
case SHARED_BW:
bw += request_rate;
if (bw > bus->max_rate)
bw = bus->max_rate;
break;
+ case SHARED_CEILING_BUT_ISO:
+ ceiling_but_iso =
+ min(request_rate, ceiling_but_iso);
+ break;
case SHARED_CEILING:
ceiling = min(request_rate, ceiling);
break;
}
}
- if ((bus->flags & PERIPH_EMC_ENB) && bw && (emc_bw_efficiency < 100)) {
- bw = emc_bw_efficiency ?
- (bw / emc_bw_efficiency) : bus->max_rate;
- bw = (bw < bus->max_rate / 100) ? (bw * 100) : bus->max_rate;
- }
+ if (bus->flags & PERIPH_EMC_ENB)
+ bw = tegra_emc_apply_efficiency(
+ bw, iso_bw, bus->max_rate, usage_flags, NULL);
rate = override_rate ? : max(rate, bw);
+ ceiling = min(ceiling, ceiling_but_iso);
ceiling = override_rate ? bus->max_rate : ceiling;
if (bus_top && bus_slow && rate_cap) {
c->state = OFF;
c->set = true;
- if (c->u.shared_bus_user.mode == SHARED_CEILING) {
+ if ((c->u.shared_bus_user.mode == SHARED_CEILING) ||
+ (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) {
c->state = ON;
c->refcnt++;
}
/* Defer rounding requests until aggregated. BW users must not be
rounded at all, others just clipped to bus range (some clients
may use round api to find limits) */
- if (c->u.shared_bus_user.mode != SHARED_BW) {
+ if ((c->u.shared_bus_user.mode != SHARED_BW) &&
+ (c->u.shared_bus_user.mode != SHARED_ISO_BW)) {
if (c->div > 1)
rate *= c->div;
.parent = &tegra_pll_m,
.reg = 0x94,
.reg_shift = 0,
- .max_rate = 600000000,
+ .max_rate = 1066000000,
};
static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
{ 19200000, 216000000, 720, 16, 4, 12},
{ 26000000, 216000000, 864, 26, 4, 12},
- { 12000000, 594000000, 99, 2, 1, 8},
+ { 12000000, 594000000, 99, 1, 2, 15},
{ 13000000, 594000000, 594, 13, 1, 12},
{ 16800000, 594000000, 495, 14, 1, 12},
{ 19200000, 594000000, 495, 16, 1, 12},
.max_rate = 700000000,
};
-/* FIXME: remove; for now, should be always checked-in as "0" */
-#define USE_LP_CPU_TO_TEST_DFLL 0
-
static struct clk tegra_dfll_cpu = {
.name = "dfll_cpu",
.flags = DFLL,
/* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra11x */
/* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra11x */
{ .input = &tegra_pll_x_out0, .value = 8},
-#if USE_LP_CPU_TO_TEST_DFLL
- { .input = &tegra_dfll_cpu, .value = 15},
-#endif
{ .input = &tegra_pll_x, .value = 8 | SUPER_LP_DIV2_BYPASS},
{ 0, 0},
};
.u.cpu = {
.main = &tegra_pll_x,
.backup = &tegra_pll_p_out4,
-#if USE_LP_CPU_TO_TEST_DFLL
- .dynamic = &tegra_dfll_cpu,
-#endif
.mode = MODE_LP,
},
};
{ 0, 0},
};
-/* xusb_hs has an alternative source, that is not used - therefore, xusb_hs
- is modeled as a single source mux */
-static struct clk_mux_sel mux_pllu_60M[] = {
- { .input = &tegra_pll_u_60M, .value = 1},
- { 0, 0},
-};
-
static struct raw_notifier_head emc_rate_change_nh;
static struct clk tegra_clk_emc = {
.rate_change_nh = &emc_rate_change_nh,
};
+static struct raw_notifier_head host1x_rate_change_nh;
+
+static struct clk tegra_clk_host1x = {
+ .name = "host1x",
+ .ops = &tegra_1xbus_clk_ops,
+ .reg = 0x180,
+ .inputs = mux_pllm_pllc_pllp_plla,
+ .flags = MUX | DIV_U71 | DIV_U71_INT,
+ .max_rate = 384000000,
+ .min_rate = 12000000,
+ .u.periph = {
+ .clk_num = 28,
+ .pll_low = &tegra_pll_p,
+#ifdef CONFIG_TEGRA_PLLM_SCALED
+ .pll_high = &tegra_pll_c,
+#else
+ .pll_high = &tegra_pll_m,
+#endif
+ },
+ .rate_change_nh = &host1x_rate_change_nh,
+};
+
#ifdef CONFIG_TEGRA_DUAL_CBUS
static struct raw_notifier_head c2bus_rate_change_nh;
.mode = _mode, \
}, \
}
+#define SHARED_EMC_CLK(_name, _dev, _con, _parent, _id, _div, _mode, _flag)\
+ { \
+ .name = _name, \
+ .lookup = { \
+ .dev_id = _dev, \
+ .con_id = _con, \
+ }, \
+ .ops = &tegra_clk_shared_bus_user_ops, \
+ .parent = _parent, \
+ .u.shared_bus_user = { \
+ .client_id = _id, \
+ .client_div = _div, \
+ .mode = _mode, \
+ .usage_flag = _flag, \
+ }, \
+ }
+
struct clk tegra_list_clks[] = {
PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
PERIPH_CLK("sbc4", "spi-tegra114.3", NULL, 68, 0x1b4, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("sbc5", "spi-tegra114.4", NULL, 104, 0x3c8, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("sbc6", "spi-tegra114.5", NULL, 105, 0x3cc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB, &tegra_nand_clk_ops),
PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
+ PERIPH_CLK("cec", "tegra_cec", NULL, 136, 0, 250000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("i2c2", "tegra11-i2c.1", "div-clk", 54, 0x198, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
PERIPH_CLK("i2c3", "tegra11-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
PERIPH_CLK("i2c4", "tegra11-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c5", "tegra11-i2c.4", "div-clk", 47, 0x128, 58300000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
+ PERIPH_CLK("i2c5", "tegra11-i2c.4", "div-clk", 47, 0x128, 64000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, 0),
+ PERIPH_CLK("mipi-cal-fixed", "mipi-cal-fixed", NULL, 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
- PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
- PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
+ PERIPH_CLK_EX("vi", "vi", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
+ PERIPH_CLK("vi_sensor", "vi", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
PERIPH_CLK("msenc", "msenc", NULL, 60, 0x170, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
PERIPH_CLK_EX("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops),
#endif
PERIPH_CLK("tsec", "tsec", NULL, 83, 0x1f4, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
- PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 384000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops),
PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 297000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0x4b8, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops),
PERIPH_CLK("dsi1-fixed", "tegradc.0", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
PERIPH_CLK("dsi2-fixed", "tegradc.1", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
- PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
- PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
- PERIPH_CLK("cilab", "tegra_camera", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
- PERIPH_CLK("cilcd", "tegra_camera", "cilcd", 145, 0x618, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
- PERIPH_CLK("cile", "tegra_camera", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+ PERIPH_CLK("csi", "vi", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
+ PERIPH_CLK("isp", "vi", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
+ PERIPH_CLK("csus", "vi", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
+ PERIPH_CLK("cilab", "vi", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+ PERIPH_CLK("cilcd", "vi", "cilcd", 145, 0x618, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+ PERIPH_CLK("cile", "vi", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
PERIPH_CLK("dsiblp", "tegradc.1", "dsiblp", 148, 0x624, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_CLK("sdmmc4.sclk", "sdhci-tegra.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_CLK("camera.sclk", "vi", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
SHARED_CLK("cap.throttle.sclk", "cap_throttle", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
SHARED_CLK("sbc5.sclk", "tegra11-spi.4", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("sbc6.sclk", "tegra11-spi.5", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
- SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
- SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
- SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("usbd.emc", "tegra-udc.0", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
- SHARED_CLK("cap.throttle.emc", "cap_throttle", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
- SHARED_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
- SHARED_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("sdmmc4.emc", "sdhci-tegra.3", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("camera.emc", "tegra_camera", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
- SHARED_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
- SHARED_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE),
- SHARED_CLK("edp.emc", "edp.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
- SHARED_CLK("battery.emc", "battery_edp", "emc", &tegra_clk_emc, NULL, 0, SHARED_CEILING),
+ SHARED_EMC_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC)),
+ SHARED_EMC_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC)),
+ SHARED_EMC_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("usbd.emc", "tegra-udc.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
+ SHARED_EMC_CLK("cap.throttle.emc", "cap_throttle", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
+ SHARED_EMC_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_3D)),
+ SHARED_EMC_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_2D)),
+ SHARED_EMC_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, BIT(EMC_USER_MSENC)),
+ SHARED_EMC_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("sdmmc4.emc", "sdhci-tegra.3", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("camera.emc", "vi", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI)),
+ SHARED_EMC_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0, 0),
+ SHARED_EMC_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE, 0),
+ SHARED_EMC_CLK("edp.emc", "edp.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
+ SHARED_EMC_CLK("battery.emc", "battery_edp", "emc", &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
#ifdef CONFIG_TEGRA_DUAL_CBUS
DUAL_CBUS_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_c2bus, "3d", 0, 0),
SHARED_CLK("override.c2bus", "override.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_OVERRIDE),
SHARED_CLK("edp.c2bus", "edp.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
SHARED_CLK("battery.c2bus", "battery_edp", "gpu", &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("cap.profile.c2bus", "profile.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
DUAL_CBUS_CLK("msenc.cbus", "tegra_msenc", "msenc", &tegra_clk_c3bus, "msenc", 0, 0),
DUAL_CBUS_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_c3bus, "tsec", 0, 0),
SHARED_CLK("override.cbus", "override.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_OVERRIDE),
SHARED_CLK("edp.cbus", "edp.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
SHARED_CLK("battery.cbus", "battery_edp", "gpu", &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
+ SHARED_CLK("cap.profile.cbus", "profile.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
#endif
+ SHARED_CLK("nv_host1x", "tegra_host1x", "host1x", &tegra_clk_host1x, 0, 0, 0),
+ SHARED_CLK("vi_host1x", "tegra_vi", "host1x", &tegra_clk_host1x, 0, 0, 0),
};
/* XUSB clocks */
#define XUSB_ID "tegra-xhci"
+static struct clk tegra_clk_xusb_gate = {
+ .name = "xusb_gate",
+ .flags = ENABLE_ON_INIT | PERIPH_NO_RESET,
+ .ops = &tegra_xusb_gate_clk_ops,
+ .rate = 12000000,
+ .max_rate = 48000000,
+ .u.periph = {
+ .clk_num = 143,
+ },
+};
+
static struct clk tegra_xusb_source_clks[] = {
PERIPH_CLK("xusb_host_src", XUSB_ID, "host_src", 143, 0x600, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
PERIPH_CLK("xusb_falcon_src", XUSB_ID, "falcon_src", 143, 0x604, 350000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
PERIPH_CLK("xusb_fs_src", XUSB_ID, "fs_src", 143, 0x608, 48000000, mux_clkm_48M_pllp_480M, MUX | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
- PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 120000000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
+ PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 122400000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
PERIPH_CLK("xusb_dev_src", XUSB_ID, "dev_src", 95, 0x60c, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
- {
- .name = "xusb_hs_src",
- .lookup = {
- .dev_id = XUSB_ID,
- .con_id = "hs_src",
- },
- .ops = &tegra_periph_clk_ops,
- .reg = 0x610,
- .inputs = mux_pllu_60M,
- .flags = PLLU | PERIPH_NO_ENB,
- .max_rate = 60000000,
- .u.periph = {
- .src_mask = 0x1 << 25,
- .src_shift = 25,
- },
+ SHARED_EMC_CLK("xusb.emc", XUSB_ID, "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, 0),
+};
+
+static struct clk tegra_xusb_ss_div2 = {
+ .name = "xusb_ss_div2",
+ .ops = &tegra_clk_m_div_ops,
+ .parent = &tegra_xusb_source_clks[3],
+ .mul = 1,
+ .div = 2,
+ .state = OFF,
+ .max_rate = 61200000,
+};
+
+static struct clk_mux_sel mux_ss_div2_pllu_60M[] = {
+ { .input = &tegra_xusb_ss_div2, .value = 0},
+ { .input = &tegra_pll_u_60M, .value = 1},
+ { 0, 0},
+};
+
+static struct clk tegra_xusb_hs_src = {
+ .name = "xusb_hs_src",
+ .lookup = {
+ .dev_id = XUSB_ID,
+ .con_id = "hs_src",
+ },
+ .ops = &tegra_periph_clk_ops,
+ .reg = 0x610,
+ .inputs = mux_ss_div2_pllu_60M,
+ .flags = PLLU | PERIPH_NO_ENB,
+ .max_rate = 61200000,
+ .u.periph = {
+ .src_mask = 0x1 << 25,
+ .src_shift = 25,
},
- SHARED_CLK("xusb.emc", "XUSB_ID", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
};
static struct clk_mux_sel mux_xusb_host[] = {
{ .input = &tegra_xusb_source_clks[0], .value = 0},
{ .input = &tegra_xusb_source_clks[1], .value = 1},
{ .input = &tegra_xusb_source_clks[2], .value = 2},
- { .input = &tegra_xusb_source_clks[5], .value = 5},
+ { .input = &tegra_xusb_hs_src, .value = 5},
{ 0, 0},
};
PERIPH_CLK_EX("xusb_dev", XUSB_ID, "dev", 95, 0, 120000000, mux_xusb_dev, 0, &tegra_clk_coupled_gate_ops),
};
-
#define CLK_DUPLICATE(_name, _dev, _con) \
{ \
.name = _name, \
CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
+ CLK_DUPLICATE("cl_dvfs_soc", "tegra11-i2c.4", NULL),
+ CLK_DUPLICATE("cl_dvfs_ref", "tegra11-i2c.4", NULL),
CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL),
CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL),
CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL),
CLK_DUPLICATE("vde.cbus", "nvavp", "vde"),
CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
- CLK_DUPLICATE("host1x", "tegra_host1x", "host1x"),
CLK_DUPLICATE("epp.cbus", "tegra_isp", "epp"),
};
&tegra_pll_d_out0,
&tegra_pll_d2,
&tegra_pll_d2_out0,
+ &tegra_clk_xusb_gate,
&tegra_pll_u,
&tegra_pll_u_480M,
&tegra_pll_u_60M,
&tegra_clk_cop,
&tegra_clk_sbus_cmplx,
&tegra_clk_emc,
+ &tegra_clk_host1x,
#ifdef CONFIG_TEGRA_DUAL_CBUS
&tegra_clk_c2bus,
&tegra_clk_c3bus,
tegra_pll_p_out1.u.pll_div.default_rate = 28800000;
tegra_pll_p_out3.u.pll_div.default_rate = 72000000;
tegra_clk_sbus_cmplx.u.system.threshold = 108000000;
+ tegra_clk_host1x.u.periph.threshold = 108000000;
break;
case 408000000:
tegra_pll_p_out1.u.pll_div.default_rate = 9600000;
tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
+ tegra_clk_host1x.u.periph.threshold = 204000000;
break;
case 204000000:
tegra_pll_p_out1.u.pll_div.default_rate = 4800000;
tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
+ tegra_clk_host1x.u.periph.threshold = 204000000;
break;
default:
pr_err("tegra: PLLP rate: %lu is not supported\n", pllp_rate);
}
/* Direct access to CPU clock sources fot CPU idle driver */
-int tegra11_cpu_dfll_rate_exchange(unsigned long *rate)
+int tegra11_cpu_g_idle_rate_exchange(unsigned long *rate)
{
int ret = 0;
struct clk *dfll = tegra_clk_cpu_cmplx.parent->u.cpu.dynamic;
return ret;
}
-int tegra11_cpu_backup_rate_exchange(unsigned long *rate)
+int tegra11_cpu_lp_idle_rate_exchange(unsigned long *rate)
{
int ret = 0;
struct clk *backup = tegra_clk_cpu_cmplx.parent->u.cpu.backup;
* source for EMC only when pll_m is fixed, or as a general fixed rate
* clock source for EMC and other peripherals if pll_m is scaled. In
* configuration with single cbus pll_c can be used as a scaled cbus
- * clock source only.
+ * clock source only. No direct use for pll_c by super clocks.
*/
if ((p == &tegra_pll_c) && (c != &tegra_pll_c_out1)) {
+ if (c->ops == &tegra_super_ops)
+ return false;
#ifdef CONFIG_TEGRA_DUAL_CBUS
#ifndef CONFIG_TEGRA_PLLM_SCALED
return c->flags & PERIPH_EMC_ENB;
* In any configuration pll_m must not be used as a clock source for
* cbus modules. If pll_m is scaled it can be used as EMC source only.
* Otherwise fixed rate pll_m can be used as clock source for EMC and
- * other peripherals.
+ * other peripherals. No direct use for pll_m by super clocks.
*/
if ((p == &tegra_pll_m) && (c != &tegra_pll_m_out1)) {
+ if (c->ops == &tegra_super_ops)
+ return false;
+
if (c->flags & PERIPH_ON_CBUS)
return false;
#ifdef CONFIG_TEGRA_PLLM_SCALED
/* Vote on memory bus frequency based on cpu frequency;
cpu rate is in kHz, emc rate is in Hz */
- if (cpu_rate >= 1300000)
- return emc_max_rate; /* cpu >= 1.3GHz, emc max */
+ if (cpu_rate >= 1500000)
+ return emc_max_rate; /* cpu >= 1.5GHz, emc max */
else if (cpu_rate >= 975000)
return 400000000; /* cpu >= 975 MHz, emc 400 MHz */
else if (cpu_rate >= 725000)
clk_writel(*ctx++, CPU_SOFTRST_CTRL1);
clk_writel(*ctx++, CPU_SOFTRST_CTRL2);
- /* FIXME: DFLL? */
/* Since we are going to reset devices and switch clock sources in this
* function, plls and secondary dividers is required to be enabled. The
* actual value will be restored back later. Note that boot plls: pllm,
off <= PERIPH_CLK_SOURCE_SOC_THERM; off += 4)
clk_writel(*ctx++, off);
+ udelay(RESET_PROPAGATION_DELAY);
+
clk_writel(*ctx++, RST_DEVICES_L);
clk_writel(*ctx++, RST_DEVICES_H);
clk_writel(*ctx++, RST_DEVICES_U);
clk_writel(*ctx++, CLK_OUT_ENB_U);
/* For LP0 resume, clk to lpcpu is required to be on */
- /* FIXME: should be saved as on? */
val = *ctx++;
val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN;
clk_writel(val, CLK_OUT_ENB_V);
tegra_cpu_car_ops = &tegra11_cpu_car_ops;
}
+static void tegra11_init_xusb_clocks(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
+ tegra11_init_one_clock(&tegra_xusb_source_clks[i]);
+
+ tegra11_init_one_clock(&tegra_xusb_ss_div2);
+ tegra11_init_one_clock(&tegra_xusb_hs_src);
+
+ for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
+ tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]);
+}
+
void __init tegra11x_init_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
tegra11_init_one_clock(&tegra_list_clks[i]);
- for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
- c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
- if (!c) {
- pr_err("%s: Unknown duplicate clock %s\n", __func__,
- tegra_clk_duplicates[i].name);
- continue;
- }
-
- tegra_clk_duplicates[i].lookup.clk = c;
- clkdev_add(&tegra_clk_duplicates[i].lookup);
- }
-
for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
tegra11_init_one_clock(&tegra_sync_source_list[i]);
for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
tegra11_init_one_clock(&tegra_clk_out_list[i]);
- for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
- tegra11_init_one_clock(&tegra_xusb_source_clks[i]);
+ tegra11_init_xusb_clocks();
- for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
- tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]);
+ for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+ c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+ if (!c) {
+ pr_err("%s: Unknown duplicate clock %s\n", __func__,
+ tegra_clk_duplicates[i].name);
+ continue;
+ }
+
+ tegra_clk_duplicates[i].lookup.clk = c;
+ clkdev_add(&tegra_clk_duplicates[i].lookup);
+ }
/* Initialize to default */
tegra_init_cpu_edp_limits(0);
-#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
- /* To be ready for DFLL late init */
- tegra_dfll_cpu.ops->init = tegra11_dfll_cpu_late_init;
-#endif
-
tegra11_cpu_car_ops_init();
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&tegra_clk_syscore_ops);
#endif
+
+}
+
+static int __init tegra11x_clk_late_init(void)
+{
+ clk_disable(&tegra_pll_re_vco);
+ return 0;
}
+late_initcall(tegra11x_clk_late_init);
Code Review / linux-3.10.git / blobdiff