ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / tegra11_clocks.c
index 74a864a..01746af 100644 (file)
@@ -39,7 +39,6 @@
 #include <mach/mc.h>
 
 #include "clock.h"
-#include "fuse.h"
 #include "iomap.h"
 #include "dvfs.h"
 #include "pm.h"
@@ -4898,7 +4897,10 @@ static long tegra11_clk_cbus_round_updown(struct clk *c, unsigned long rate,
                        c->dvfs->freqs[n-2] + CBUS_FINE_GRANULARITY_RANGE);
                threshold -= CBUS_FINE_GRANULARITY_RANGE;
 
-               if (rate <= threshold)
+               if (rate == threshold)
+                       return threshold;
+
+               if (rate < threshold)
                        return up ? threshold : c->dvfs->freqs[n-2];
 
                rate = (up ? DIV_ROUND_UP(rate, CBUS_FINE_GRANULARITY) :
@@ -7061,6 +7063,13 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("floor.host1x", "floor.host1x",      NULL,     &tegra_clk_host1x, NULL,  0, 0),
        SHARED_CLK("override.host1x", "override.host1x", NULL,    &tegra_clk_host1x, NULL,  0, SHARED_OVERRIDE),
        SHARED_CLK("floor.profile.host1x", "profile.host1x", NULL, &tegra_clk_host1x, NULL,  0, 0),
+
+       SHARED_CLK("sbc1.sclk", "spi_tegra.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc2.sclk", "spi_tegra.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc3.sclk", "spi_tegra.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc4.sclk", "spi_tegra.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc5.sclk", "spi_tegra.4", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc6.sclk", "spi_tegra.5", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
 };