ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / tegra11_clocks.c
index 1a85b98..01746af 100644 (file)
@@ -39,7 +39,6 @@
 #include <mach/mc.h>
 
 #include "clock.h"
-#include "fuse.h"
 #include "iomap.h"
 #include "dvfs.h"
 #include "pm.h"
@@ -1488,16 +1487,6 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                goto abort;
        }
 
-       /* Disabling old parent scales old mode voltage rail */
-       if (c->refcnt)
-               clk_disable(c->parent);
-       if (p_source_old) {
-               clk_disable(p->parent);
-               clk_disable(p_source_old);
-       }
-
-       clk_reparent(c, p);
-
        /*
         * Lock DFLL now (resume closed loop VDD_CPU control).
         * G CPU operations are resumed on DFLL if it was the last G CPU
@@ -1514,6 +1503,16 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                }
        }
 
+       /* Disabling old parent scales old mode voltage rail */
+       if (c->refcnt)
+               clk_disable(c->parent);
+       if (p_source_old) {
+               clk_disable(p->parent);
+               clk_disable(p_source_old);
+       }
+
+       clk_reparent(c, p);
+
        tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return 0;
 
@@ -3668,11 +3667,17 @@ static int tegra11_use_dfll_cb(const char *arg, const struct kernel_param *kp)
        unsigned long c_flags, p_flags;
        unsigned int old_use_dfll;
        struct clk *c = tegra_get_clock_by_name("cpu");
+       struct clk *dfll = tegra_get_clock_by_name("dfll_cpu");
 
-       if (!c->parent || !c->parent->dvfs)
+       if (!c->parent || !c->parent->dvfs || !dfll)
                return -ENOSYS;
 
        clk_lock_save(c, &c_flags);
+       if (dfll->state == UNINITIALIZED) {
+               pr_err("%s: DFLL is not initialized\n", __func__);
+               clk_unlock_restore(c, &c_flags);
+               return -ENOSYS;
+       }
        if (c->parent->u.cpu.mode == MODE_LP) {
                pr_err("%s: DFLL is not used on LP CPU\n", __func__);
                clk_unlock_restore(c, &c_flags);
@@ -4892,7 +4897,10 @@ static long tegra11_clk_cbus_round_updown(struct clk *c, unsigned long rate,
                        c->dvfs->freqs[n-2] + CBUS_FINE_GRANULARITY_RANGE);
                threshold -= CBUS_FINE_GRANULARITY_RANGE;
 
-               if (rate <= threshold)
+               if (rate == threshold)
+                       return threshold;
+
+               if (rate < threshold)
                        return up ? threshold : c->dvfs->freqs[n-2];
 
                rate = (up ? DIV_ROUND_UP(rate, CBUS_FINE_GRANULARITY) :
@@ -7055,6 +7063,13 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("floor.host1x", "floor.host1x",      NULL,     &tegra_clk_host1x, NULL,  0, 0),
        SHARED_CLK("override.host1x", "override.host1x", NULL,    &tegra_clk_host1x, NULL,  0, SHARED_OVERRIDE),
        SHARED_CLK("floor.profile.host1x", "profile.host1x", NULL, &tegra_clk_host1x, NULL,  0, 0),
+
+       SHARED_CLK("sbc1.sclk", "spi_tegra.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc2.sclk", "spi_tegra.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc3.sclk", "spi_tegra.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc4.sclk", "spi_tegra.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc5.sclk", "spi_tegra.4", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc6.sclk", "spi_tegra.5", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
 };