ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / tegra11_clocks.c
index 06a48f2..01746af 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/tegra11_clocks.c
  *
- * Copyright (C) 2011-2012 NVIDIA Corporation
+ * Copyright (c) 2011-2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
 #include <linux/cpufreq.h>
 #include <linux/syscore_ops.h>
 #include <linux/platform_device.h>
+#include <linux/clk/tegra.h>
+#include <linux/tegra-soc.h>
+#include <linux/tegra-powergate.h>
 
 #include <asm/clkdev.h>
 
-#include <mach/iomap.h>
 #include <mach/edp.h>
-#include <mach/hardware.h>
 #include <mach/mc.h>
 
 #include "clock.h"
-#include "fuse.h"
+#include "iomap.h"
 #include "dvfs.h"
 #include "pm.h"
 #include "sleep.h"
 #define PLLE_MISC_VREG_CTRL_MASK       (0x3<<PLLE_MISC_VREG_CTRL_SHIFT)
 
 #define PLLE_SS_CTRL                   0x68
+#define        PLLE_SS_INCINTRV_SHIFT          24
+#define        PLLE_SS_INCINTRV_MASK           (0x3f<<PLLE_SS_INCINTRV_SHIFT)
+#define        PLLE_SS_INC_SHIFT               16
+#define        PLLE_SS_INC_MASK                (0xff<<PLLE_SS_INC_SHIFT)
+#define        PLLE_SS_CNTL_INVERT             (0x1 << 15)
+#define        PLLE_SS_CNTL_CENTER             (0x1 << 14)
 #define        PLLE_SS_CNTL_SSC_BYP            (0x1 << 12)
 #define        PLLE_SS_CNTL_INTERP_RESET       (0x1 << 11)
 #define        PLLE_SS_CNTL_BYPASS_SS          (0x1 << 10)
+#define        PLLE_SS_MAX_SHIFT               0
+#define        PLLE_SS_MAX_MASK                (0x1ff<<PLLE_SS_MAX_SHIFT)
+#define PLLE_SS_COEFFICIENTS_MASK      \
+       (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
+#define PLLE_SS_COEFFICIENTS_VAL       \
+       ((0x20<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
+        (0x25<<PLLE_SS_MAX_SHIFT))
 #define PLLE_SS_DISABLE                        (PLLE_SS_CNTL_SSC_BYP |\
        PLLE_SS_CNTL_INTERP_RESET | PLLE_SS_CNTL_BYPASS_SS)
-#define PLLE_SS_COEFFICIENTS_MASK       (~PLLE_SS_DISABLE)
 
 #define PLLE_AUX                       0x48c
 #define PLLE_AUX_PLLRE_SEL             (1<<28)
 #define USB_PLLS_USE_LOCKDET                   (1<<6)
 #define USB_PLLS_ENABLE_SWCTL                  ((1<<2) | (1<<0))
 
+/* CPU clock trimmers */
+#define CPU_FINETRIM_BYP                       0x4d0
+#define CPU_FINETRIM_SELECT                    0x4d4
+#define CPU_FINETRIM_DR                                0x4d8
+#define CPU_FINETRIM_DF                                0x4dc
+#define CPU_FINETRIM_F                         0x4e0
+#define CPU_FINETRIM_R                         0x4e4
+
 /* DFLL */
 #define DFLL_BASE                              0x2f4
 #define DFLL_BASE_RESET                                (1<<0)
 #define ROUND_DIVIDER_DOWN     1
 #define DIVIDER_1_5_ALLOWED    0
 
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX         0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET     0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR     0x344
+#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR   0x34c
+#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS    0x470
+
 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
 #define CPU_RESET(cpu) (0x111001ul << (cpu))
 
 /* PLLP default fixed rate in h/w controlled mode */
 #define PLLP_DEFAULT_FIXED_RATE                216000000
 
+/* Use PLL_RE as PLLE input (default - OSC via pll reference divider) */
+#define USE_PLLE_INPUT_PLLRE   0
+
 static bool tegra11_is_dyn_ramp(struct clk *c,
                                unsigned long rate, bool from_vco_min);
 static void tegra11_pllp_init_dependencies(unsigned long pllp_rate);
-static unsigned long tegra11_clk_shared_bus_update(
-       struct clk *bus, struct clk **bus_top, struct clk **bus_slow);
+static unsigned long tegra11_clk_shared_bus_update(struct clk *bus,
+       struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap);
+static unsigned long tegra11_clk_cap_shared_bus(struct clk *bus,
+       unsigned long rate, unsigned long ceiling);
 
 static bool detach_shared_bus;
 module_param(detach_shared_bus, bool, 0644);
@@ -534,7 +567,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
 static void __iomem *reg_xusb_padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
 
-#define MISC_GP_HIDREV                         0x804
 #define MISC_GP_TRANSACTOR_SCRATCH_0           0x864
 #define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE   (0x1 << 1)
 #define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE  (0x1 << 2)
@@ -549,15 +581,13 @@ static DEFINE_SPINLOCK(periph_refcount_lock);
 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
 
 #define clk_writel(value, reg) \
-       __raw_writel(value, (u32)reg_clk_base + (reg))
+       __raw_writel(value, reg_clk_base + (reg))
 #define clk_readl(reg) \
-       __raw_readl((u32)reg_clk_base + (reg))
+       __raw_readl(reg_clk_base + (reg))
 #define pmc_writel(value, reg) \
-       __raw_writel(value, (u32)reg_pmc_base + (reg))
+       __raw_writel(value, reg_pmc_base + (reg))
 #define pmc_readl(reg) \
-       __raw_readl((u32)reg_pmc_base + (reg))
-#define chipid_readl() \
-       __raw_readl((u32)misc_gp_base + MISC_GP_HIDREV)
+       __raw_readl(reg_pmc_base + (reg))
 #define xusb_padctl_writel(value, reg) \
        __raw_writel(value, reg_xusb_padctl_base + (reg))
 #define xusb_padctl_readl(reg) \
@@ -565,13 +595,15 @@ static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
 
 #define clk_writel_delay(value, reg)                                   \
        do {                                                            \
-               __raw_writel((value), (u32)reg_clk_base + (reg));       \
+               __raw_writel((value), reg_clk_base + (reg));            \
+               __raw_readl(reg_clk_base + (reg));                      \
                udelay(2);                                              \
        } while (0)
 
 #define pll_writel_delay(value, reg)                                   \
        do {                                                            \
-               __raw_writel((value), reg_clk_base + (reg));    \
+               __raw_writel((value), reg_clk_base + (reg));            \
+               __raw_readl(reg_clk_base + (reg));                      \
                udelay(1);                                              \
        } while (0)
 
@@ -830,8 +862,10 @@ static void tegra11_super_clk_init(struct clk *c)
                c->mul = 2;
                c->div = 2;
 
-               /* Make sure 7.1 divider is 1:1, clear s/w skipper control */
-               /* FIXME: set? preserve? thermal h/w skipper control */
+               /*
+                * Make sure 7.1 divider is 1:1; clear h/w skipper control -
+                * it will be enabled by soctherm later
+                */
                val = clk_readl(c->reg + SUPER_CLK_DIVIDER);
                BUG_ON(val & SUPER_CLOCK_DIV_U71_MASK);
                val = 0;
@@ -1126,8 +1160,10 @@ static int tegra11_cpu_clk_dfll_on(struct clk *c, unsigned long rate,
                        }
                }
 
+               tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
                ret = clk_set_parent(c->parent, dfll);
                if (ret) {
+                       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
                        pr_err("Failed to switch cpu to %s\n", dfll->name);
                        return ret;
                }
@@ -1136,6 +1172,7 @@ static int tegra11_cpu_clk_dfll_on(struct clk *c, unsigned long rate,
 
                /* prevent legacy dvfs voltage scaling */
                tegra_dvfs_dfll_mode_set(c->dvfs, rate);
+               tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        }
        return 0;
 }
@@ -1150,7 +1187,23 @@ static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
 
        rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost);
        pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main;
+       dfll_rate_min = max(rate, dfll_rate_min);
+
+       /* set target rate last time in dfll mode */
+       if (old_rate != dfll_rate_min) {
+               ret = tegra_dvfs_set_rate(c, dfll_rate_min);
+               if (!ret)
+                       ret = clk_set_rate(dfll, dfll_rate_min);
+
+               if (ret) {
+                       pr_err("Failed to set cpu rate %lu on source %s\n",
+                              dfll_rate_min, dfll->name);
+                       return ret;
+               }
+       }
 
+       /* unlock dfll - release volatge rail control */
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
        ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
        if (ret) {
                pr_err("Failed to unlock %s\n", dfll->name);
@@ -1158,7 +1211,7 @@ static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
        }
 
        /* restore legacy dvfs operations and set appropriate voltage */
-       ret = tegra_dvfs_dfll_mode_clear(c->dvfs, max(rate, dfll_rate_min));
+       ret = tegra_dvfs_dfll_mode_clear(c->dvfs, dfll_rate_min);
        if (ret) {
                pr_err("Failed to set cpu rail for rate %lu\n", rate);
                goto back_to_dfll;
@@ -1182,11 +1235,13 @@ static int tegra11_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
        if (old_rate <= rate)
                tegra_dvfs_set_rate(c, rate);
 
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return 0;
 
 back_to_dfll:
        tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
        tegra_dvfs_dfll_mode_set(c->dvfs, old_rate);
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return ret;
 }
 
@@ -1198,12 +1253,13 @@ static int tegra11_cpu_clk_set_rate(struct clk *c, unsigned long rate)
        bool is_dfll = c->parent->parent == c->u.cpu.dynamic;
 
        /* On SILICON allow CPU rate change only if cpu regulator is connected.
-          Ignore regulator connection on FPGA and SIMULATION platforms. */
+          Ignore regulator connection on FPGA platforms. */
 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
        if (c->dvfs) {
                if (!c->dvfs->dvfs_rail)
                        return -ENOSYS;
-               else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate)) {
+               else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate) &&
+                        (c->boot_rate < rate)) {
                        WARN(1, "Increasing CPU rate while regulator is not"
                                " ready is not allowed\n");
                        return -ENOSYS;
@@ -1307,6 +1363,7 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
        const struct clk_mux_sel *sel;
        unsigned long rate = clk_get_rate(c->parent);
        struct clk *dfll = c->parent->u.cpu.dynamic ? : p->u.cpu.dynamic;
+       struct clk *p_source_old = NULL;
        struct clk *p_source;
 
        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
@@ -1364,6 +1421,7 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                return 0;       /* already switched - exit */
        }
 
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
        if (c->parent->parent->parent == dfll) {
                /* G (DFLL selected as clock source) => LP switch:
                 * turn DFLL into open loop mode ("release" VDD_CPU rail)
@@ -1378,23 +1436,34 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                ret = clk_set_rate(p_source, rate);
                if (ret)
                        goto abort;
-       } else if (p->parent->parent == dfll) {
+       } else if ((p->parent->parent == dfll) ||
+                  (p->dvfs && tegra_dvfs_is_dfll_range(p->dvfs, rate))) {
                /* LP => G (DFLL selected as clock source) switch:
                 * set DFLL rate ready (DFLL is still disabled)
                 * (set target p_source as dfll, G source is already selected)
                 */
                p_source = dfll;
-               ret = clk_set_rate(p_source, rate);
+               ret = clk_set_rate(dfll,
+                       tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail) ? rate :
+                       max(rate, p->dvfs->dfll_data.use_dfll_rate_min));
                if (ret)
                        goto abort;
+
+               ret = tegra_dvfs_rail_dfll_mode_set_cold(tegra_cpu_rail);
+               if (ret)
+                       goto abort;
+
        } else
-               /* DFLL is not selcted on either side of the switch:
+               /* DFLL is not selected on either side of the switch:
                 * set target p_source equal to current clock source
                 */
                p_source = c->parent->parent->parent;
 
        /* Switch new parent to target clock source if necessary */
        if (p->parent->parent != p_source) {
+               clk_enable(p->parent->parent);
+               clk_enable(p->parent);
+               p_source_old = p->parent->parent;
                ret = clk_set_parent(p->parent, p_source);
                if (ret) {
                        pr_err("%s: Failed to set parent %s for %s\n",
@@ -1418,22 +1487,49 @@ static int tegra11_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
                goto abort;
        }
 
+       /*
+        * Lock DFLL now (resume closed loop VDD_CPU control).
+        * G CPU operations are resumed on DFLL if it was the last G CPU
+        * clock source, or if resume rate is in DFLL usage range in case
+        * when auto-switch between PLL and DFLL is enabled.
+        */
+       if (p_source == dfll) {
+               if (tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail)) {
+                       tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+               } else {
+                       clk_set_rate(dfll, rate);
+                       tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+                       tegra_dvfs_dfll_mode_set(p->dvfs, rate);
+               }
+       }
+
        /* Disabling old parent scales old mode voltage rail */
        if (c->refcnt)
                clk_disable(c->parent);
+       if (p_source_old) {
+               clk_disable(p->parent);
+               clk_disable(p_source_old);
+       }
 
        clk_reparent(c, p);
 
-       /* Lock DFLL now (resume closed loop VDD_CPU control) */
-       if (p_source == dfll)
-               tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
-
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
        return 0;
 
 abort:
        /* Re-lock DFLL if necessary after aborted switch */
-       if (c->parent->parent->parent == dfll)
+       if (c->parent->parent->parent == dfll) {
+               clk_set_rate(dfll, rate);
                tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+       }
+       if (p_source_old) {
+               clk_disable(p->parent);
+               clk_disable(p_source_old);
+       }
+       tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
+
+       pr_err("%s: aborted switch from %s to %s\n",
+              __func__, c->parent->name, p->name);
        return ret;
 }
 
@@ -1549,7 +1645,8 @@ static void tegra11_sbus_cmplx_init(struct clk *c)
  * recursive calls. Lost 1Hz is added in tegra11_sbus_cmplx_set_rate before
  * actually setting divider rate.
  */
-static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
+static long tegra11_sbus_cmplx_round_updown(struct clk *c, unsigned long rate,
+                                           bool up)
 {
        int divider;
        unsigned long source_rate, round_rate;
@@ -1562,9 +1659,9 @@ static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
        source_rate = clk_get_rate(new_parent->parent);
 
        divider = clk_div71_get_divider(source_rate, rate,
-               new_parent->flags, ROUND_DIVIDER_DOWN);
+               new_parent->flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
        if (divider < 0)
-               return divider;
+               return c->min_rate;
 
        if (divider == 1)
                divider = 0;
@@ -1586,6 +1683,11 @@ static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
        return round_rate;
 }
 
+static long tegra11_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
+{
+       return tegra11_sbus_cmplx_round_updown(c, rate, true);
+}
+
 static int tegra11_sbus_cmplx_set_rate(struct clk *c, unsigned long rate)
 {
        int ret;
@@ -1641,8 +1743,7 @@ static int tegra11_clk_sbus_update(struct clk *bus)
        if (detach_shared_bus)
                return 0;
 
-       rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
-       rate = clk_round_rate_locked(bus, rate);
+       rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL);
 
        old_rate = clk_get_rate_locked(bus);
        if (rate == old_rate)
@@ -1655,6 +1756,7 @@ static struct clk_ops tegra_sbus_cmplx_ops = {
        .init = tegra11_sbus_cmplx_init,
        .set_rate = tegra11_sbus_cmplx_set_rate,
        .round_rate = tegra11_sbus_cmplx_round_rate,
+       .round_rate_updown = tegra11_sbus_cmplx_round_updown,
        .shared_bus_update = tegra11_clk_sbus_update,
 };
 
@@ -1744,21 +1846,35 @@ static struct clk_ops tegra_blink_clk_ops = {
 static int tegra11_pll_clk_wait_for_lock(
        struct clk *c, u32 lock_reg, u32 lock_bits)
 {
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
 #if USE_PLL_LOCK_BITS
        int i;
+       u32 val = 0;
+
        for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) {
                udelay(PLL_PRE_LOCK_DELAY);
-               if ((clk_readl(lock_reg) & lock_bits) == lock_bits) {
+               val = clk_readl(lock_reg);
+               if ((val & lock_bits) == lock_bits) {
                        udelay(PLL_POST_LOCK_DELAY);
                        return 0;
                }
        }
-       pr_err("Timed out waiting for lock bit on pll %s\n", c->name);
-       return -1;
+
+       /* PLLCX lock bits may fluctuate after the lock - don't report timeout
+          in this case (phase lock bit happens to uniquely identify PLLCX) */
+       if (lock_bits & PLLCX_BASE_PHASE_LOCK) {
+               pr_debug("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+                        c->name, lock_reg, val);
+               return 0;
+       } else if ((c->flags & PLLD) &&
+                       tegra_powergate_check_clamping(TEGRA_POWERGATE_DISA)) {
+               pr_debug("Waiting for %s lock.\n", c->name);
+       } else {
+               pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
+                      c->name, lock_reg, val);
+               return -ETIMEDOUT;
+       }
 #endif
        udelay(c->u.pll.lock_delay);
-#endif
        return 0;
 }
 
@@ -1853,7 +1969,7 @@ static void tegra11_utmi_param_configure(struct clk *c)
           ports are assigned to USB2 */
        reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
        reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
-       reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
+       reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
        clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
 
        udelay(1);
@@ -1972,6 +2088,59 @@ static u8 get_pll_cpcon(struct clk *c, u16 n)
        return c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
 }
 
+/* Special comparison frequency selection for PLLD at 12MHz refrence rate */
+unsigned long get_pll_cfreq_special(struct clk *c, unsigned long input_rate,
+                                  unsigned long rate, unsigned long *vco)
+{
+       if (!(c->flags & PLLD) || (input_rate != 12000000))
+               return 0;
+
+       *vco = c->u.pll.vco_min;
+
+       if (rate <= 250000000)
+               return 4000000;
+       else if (rate <= 500000000)
+               return 2000000;
+       else
+               return 1000000;
+}
+
+/* Common comparison frequency selection */
+unsigned long get_pll_cfreq_common(struct clk *c, unsigned long input_rate,
+                                  unsigned long rate, unsigned long *vco)
+{
+       unsigned long cfreq = 0;
+
+       switch (input_rate) {
+       case 12000000:
+       case 26000000:
+               cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
+               break;
+       case 13000000:
+               cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
+               break;
+       case 16800000:
+       case 19200000:
+               cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
+               break;
+       default:
+               if (c->parent->flags & DIV_U71_FIXED) {
+                       /* PLLP_OUT1 rate is not in PLLA table */
+                       pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
+                               __func__, c->name, input_rate, rate);
+                       cfreq = input_rate/(input_rate/1000000);
+                       break;
+               }
+               pr_err("%s: Unexpected reference rate %lu\n",
+                      __func__, input_rate);
+               BUG();
+       }
+
+       /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */
+       *vco = max(200 * cfreq, c->u.pll.vco_min);
+       return cfreq;
+}
+
 static int tegra11_pll_clk_set_rate(struct clk *c, unsigned long rate)
 {
        u32 val, p_div, old_base;
@@ -2016,33 +2185,12 @@ static int tegra11_pll_clk_set_rate(struct clk *c, unsigned long rate)
                BUG_ON(c->flags & PLLU);
                sel = &cfg;
 
-               switch (input_rate) {
-               case 12000000:
-               case 26000000:
-                       cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
-                       break;
-               case 13000000:
-                       cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
-                       break;
-               case 16800000:
-               case 19200000:
-                       cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
-                       break;
-               default:
-                       if (c->parent->flags & DIV_U71_FIXED) {
-                               /* PLLP_OUT1 rate is not in PLLA table */
-                               pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
-                                       __func__, c->name, input_rate, rate);
-                               cfreq = input_rate/(input_rate/1000000);
-                               break;
-                       }
-                       pr_err("%s: Unexpected reference rate %lu\n",
-                              __func__, input_rate);
-                       BUG();
-               }
+               /* If available, use pll specific algorithm to select comparison
+                  frequency, and vco target */
+               cfreq = get_pll_cfreq_special(c, input_rate, rate, &vco);
+               if (!cfreq)
+                       cfreq = get_pll_cfreq_common(c, input_rate, rate, &vco);
 
-               /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */
-               vco = max(200 * cfreq, c->u.pll.vco_min);
                for (cfg.output_rate = rate; cfg.output_rate < vco; p_div++)
                        cfg.output_rate <<= 1;
 
@@ -2352,9 +2500,7 @@ static void tegra11_pllcx_clk_init(struct clk *c)
         * and no enabled module clocks should use it as a source during clock
         * init.
         */
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
        BUG_ON(c->state == ON);
-#endif
        /*
         * Most of PLLCX register fields are shadowed, and can not be read
         * directly from PLL h/w. Hence, actual PLLCX boot state is unknown.
@@ -2571,9 +2717,7 @@ static void pllx_set_defaults(struct clk *c, unsigned long input_rate)
 
        /* Only s/w dyn ramp control is supported */
        val = clk_readl(PLLX_HW_CTRL_CFG);
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
        BUG_ON(!(val & PLLX_HW_CTRL_CFG_SWCTRL));
-#endif
 
        pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b);
        val = step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
@@ -2591,11 +2735,9 @@ static void pllx_set_defaults(struct clk *c, unsigned long input_rate)
 
        /* Check/set IDDQ */
        val = clk_readl(c->reg + PLL_MISCN(c, 3));
-       if (c->state == ON) {
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
+       if (c->state == ON)
                BUG_ON(val & PLLX_MISC3_IDDQ);
-#endif
-       } else {
+       else {
                val |= PLLX_MISC3_IDDQ;
                clk_writel(val, c->reg + PLL_MISCN(c, 3));
        }
@@ -2626,9 +2768,7 @@ static void pllc_set_defaults(struct clk *c, unsigned long input_rate)
        clk_writel(val, c->reg + PLL_MISC(c));
 
        if (c->state == ON) {
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
                BUG_ON(val & PLLC_MISC_IDDQ);
-#endif
        } else {
                val |= PLLC_MISC_IDDQ;
                clk_writel(val, c->reg + PLL_MISC(c));
@@ -2842,10 +2982,8 @@ static void pllm_set_defaults(struct clk *c, unsigned long input_rate)
 
        if (c->state != ON)
                val |= PLLM_MISC_IDDQ;
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
        else
                BUG_ON(val & PLLM_MISC_IDDQ);
-#endif
 
        clk_writel(val, c->reg + PLL_MISC(c));
 }
@@ -3009,10 +3147,8 @@ static void pllre_set_defaults(struct clk *c, unsigned long input_rate)
 
        if (c->state != ON)
                val |= PLLRE_MISC_IDDQ;
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
        else
                BUG_ON(val & PLLRE_MISC_IDDQ);
-#endif
 
        clk_writel(val, c->reg + PLL_MISC(c));
 }
@@ -3224,10 +3360,28 @@ static u8 plle_p[PLLE_CMLDIV_MAX + 1] = {
 /* CMLDIV: 0, 1, 2, 3, 4, 5, 6,  7,  8,  9, 10, 11, 12, 13, 14 */
 /* p: */   1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
 
+static inline void select_pll_e_input(u32 aux_reg)
+{
+#if USE_PLLE_INPUT_PLLRE
+       aux_reg |= PLLE_AUX_PLLRE_SEL;
+#else
+       aux_reg &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
+#endif
+       clk_writel(aux_reg, PLLE_AUX);
+}
+
 static void tegra11_plle_clk_init(struct clk *c)
 {
        u32 val, p;
-       struct clk *ref = tegra_get_clock_by_name("pll_re_vco");
+       struct clk *pll_ref = tegra_get_clock_by_name("pll_ref");
+       struct clk *re_vco = tegra_get_clock_by_name("pll_re_vco");
+       struct clk *pllp = tegra_get_clock_by_name("pllp");
+#if USE_PLLE_INPUT_PLLRE
+       struct clk *ref = re_vco;
+#else
+       struct clk *ref = pll_ref;
+#endif
+
 
        val = clk_readl(c->reg + PLL_BASE);
        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
@@ -3237,18 +3391,15 @@ static void tegra11_plle_clk_init(struct clk *c)
        c->div *= plle_p[p];
 
        val = clk_readl(PLLE_AUX);
-       c->parent = (val & PLLE_AUX_PLLRE_SEL) ? ref :
-                       (val & PLLE_AUX_PLLP_SEL) ?
-                               tegra_get_clock_by_name("pll_p") :
-                               tegra_get_clock_by_name("pll_ref");
+       c->parent = (val & PLLE_AUX_PLLRE_SEL) ? re_vco :
+               (val & PLLE_AUX_PLLP_SEL) ? pllp : pll_ref;
        if (c->parent != ref) {
                if (c->state == ON) {
                        WARN(1, "%s: pll_e is left enabled with %s input\n",
                             __func__, c->parent->name);
                } else {
                        c->parent = ref;
-                       val |= PLLE_AUX_PLLRE_SEL;
-                       clk_writel(val, PLLE_AUX);
+                       select_pll_e_input(val);
                }
        }
 }
@@ -3328,7 +3479,15 @@ static int tegra11_plle_clk_enable(struct clk *c)
        tegra11_pll_clk_wait_for_lock(
                c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
 #if USE_PLLE_SS
-       /* FIXME: enable SS if necessary */
+       val = clk_readl(PLLE_SS_CTRL);
+       val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
+       val &= ~PLLE_SS_COEFFICIENTS_MASK;
+       val |= PLLE_SS_COEFFICIENTS_VAL;
+       clk_writel(val, PLLE_SS_CTRL);
+       val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
+       pll_writel_delay(val, PLLE_SS_CTRL);
+       val &= ~PLLE_SS_CNTL_INTERP_RESET;
+       pll_writel_delay(val, PLLE_SS_CTRL);
 #endif
 #if !USE_PLLE_SWCTL
        /* switch pll under h/w control */
@@ -3362,10 +3521,9 @@ static void tegra11_plle_clk_resume(struct clk *c)
        if (val & PLL_BASE_ENABLE)
                return;         /* already resumed */
 
-       /* Restore pll_re_vco as parent */
+       /* Restore parent */
        val = clk_readl(PLLE_AUX);
-       val |= PLLE_AUX_PLLRE_SEL;
-       clk_writel(val, PLLE_AUX);
+       select_pll_e_input(val);
 }
 #endif
 
@@ -3384,13 +3542,36 @@ static struct clk_ops tegra_plle_ops = {
  * basically cl-dvfs wrappers.
  */
 
-#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
 /* DFLL operations */
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+static void tune_cpu_trimmers(bool trim_high)
+{
+       if (trim_high) {
+               clk_writel(0, CPU_FINETRIM_SELECT);
+               clk_writel(0, CPU_FINETRIM_DR);
+               clk_writel(0, CPU_FINETRIM_R);
+       } else {
+               clk_writel(0x3F, CPU_FINETRIM_SELECT);
+               clk_writel(0x3F, CPU_FINETRIM_DR);
+               clk_writel(0xFFF, CPU_FINETRIM_R);
+       }
+       wmb();
+       clk_readl(CPU_FINETRIM_R);
+}
+#endif
+
 static void __init tegra11_dfll_cpu_late_init(struct clk *c)
 {
 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
        int ret;
-       struct clk *cpu = tegra_get_clock_by_name("cpu");
+       struct clk *cpu = tegra_get_clock_by_name("cpu_g");
+
+       if (!cpu || !cpu->dvfs) {
+               pr_err("%s: CPU dvfs is not present\n", __func__);
+               return;
+       }
+       if (cpu->dvfs->speedo_id > 0)   /* A01P and above parts */
+               tegra_dvfs_set_dfll_tune_trimmers(cpu->dvfs, tune_cpu_trimmers);
 
 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
        u32 netlist, patchid;
@@ -3410,12 +3591,17 @@ static void __init tegra11_dfll_cpu_late_init(struct clk *c)
                c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device);
 
                use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
-               tegra_dvfs_set_dfll_range(cpu->parent->dvfs, use_dfll);
+               tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll);
+               tegra_cl_dvfs_debug_init(c);
                pr_info("Tegra CPU DFLL is initialized\n");
        }
 #endif
 }
-#endif
+
+static void tegra11_dfll_clk_init(struct clk *c)
+{
+       c->ops->init = tegra11_dfll_cpu_late_init;
+}
 
 static int tegra11_dfll_clk_enable(struct clk *c)
 {
@@ -3466,6 +3652,7 @@ static void tegra11_dfll_clk_resume(struct clk *c)
 #endif
 
 static struct clk_ops tegra_dfll_ops = {
+       .init                   = tegra11_dfll_clk_init,
        .enable                 = tegra11_dfll_clk_enable,
        .disable                = tegra11_dfll_clk_disable,
        .set_rate               = tegra11_dfll_clk_set_rate,
@@ -3480,11 +3667,17 @@ static int tegra11_use_dfll_cb(const char *arg, const struct kernel_param *kp)
        unsigned long c_flags, p_flags;
        unsigned int old_use_dfll;
        struct clk *c = tegra_get_clock_by_name("cpu");
+       struct clk *dfll = tegra_get_clock_by_name("dfll_cpu");
 
-       if (!c->parent || !c->parent->dvfs)
+       if (!c->parent || !c->parent->dvfs || !dfll)
                return -ENOSYS;
 
        clk_lock_save(c, &c_flags);
+       if (dfll->state == UNINITIALIZED) {
+               pr_err("%s: DFLL is not initialized\n", __func__);
+               clk_unlock_restore(c, &c_flags);
+               return -ENOSYS;
+       }
        if (c->parent->u.cpu.mode == MODE_LP) {
                pr_err("%s: DFLL is not used on LP CPU\n", __func__);
                clk_unlock_restore(c, &c_flags);
@@ -3529,8 +3722,11 @@ static int tegra11_pll_div_clk_set_rate(struct clk *c, unsigned long rate);
 static void tegra11_pll_div_clk_init(struct clk *c)
 {
        if (c->flags & DIV_U71) {
-               u32 divu71;
-               u32 val = clk_readl(c->reg);
+               u32 val, divu71;
+               if (c->parent->state == OFF)
+                       c->ops->disable(c);
+
+               val = clk_readl(c->reg);
                val >>= c->reg_shift;
                c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
                if (!(val & PLL_OUT_RESET_DISABLE))
@@ -3734,14 +3930,20 @@ static void tegra11_periph_clk_init(struct clk *c)
                c->parent = mux->input;
        } else {
                if (c->flags & PLLU) {
-                       /* for xusb_hs clock enforce PLLU source during init */
+                       /* for xusb_hs clock enforce SS div2 source */
                        val &= ~periph_clk_source_mask(c);
-                       val |= c->inputs[0].value << periph_clk_source_shift(c);
                        clk_writel_delay(val, c->reg);
                }
                c->parent = c->inputs[0].input;
        }
 
+       /* if peripheral is left under reset - enforce safe rate */
+       if (!(c->flags & PERIPH_NO_RESET) &&
+           (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))) {
+               tegra_periph_clk_safe_rate_init(c);
+                val = clk_readl(c->reg);
+       }
+
        if (c->flags & DIV_U71) {
                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
                if (c->flags & DIV_U71_IDLE) {
@@ -3803,7 +4005,7 @@ static int tegra11_periph_clk_enable(struct clk *c)
        clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
        if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) {
                if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) {
-                       udelay(5);      /* reset propagation delay */
+                       udelay(RESET_PROPAGATION_DELAY);
                        clk_writel(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_RST_CLR_REG(c));
                }
        }
@@ -3829,7 +4031,7 @@ static void tegra11_periph_clk_disable(struct clk *c)
                 * flush the write operation in apb bus. This will avoid the
                 * peripheral access after disabling clock*/
                if (c->flags & PERIPH_ON_APB)
-                       val = chipid_readl();
+                       val = tegra_read_chipid();
 
                clk_writel_delay(
                        PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
@@ -3853,7 +4055,7 @@ static void tegra11_periph_clk_reset(struct clk *c, bool assert)
                         * will avoid the peripheral access after disabling
                         * clock */
                        if (c->flags & PERIPH_ON_APB)
-                               val = chipid_readl();
+                               val = tegra_read_chipid();
 
                        clk_writel(PERIPH_CLK_TO_BIT(c),
                                   PERIPH_CLK_TO_RST_SET_REG(c));
@@ -3989,8 +4191,154 @@ static struct clk_ops tegra_periph_clk_ops = {
        .reset                  = &tegra11_periph_clk_reset,
 };
 
+/* 1x shared bus ops */
+static long tegra11_1xbus_round_updown(struct clk *c, unsigned long rate,
+                                           bool up)
+{
+       int divider;
+       unsigned long source_rate, round_rate;
+       struct clk *new_parent;
+
+       rate = max(rate, c->min_rate);
+
+       new_parent = (rate <= c->u.periph.threshold) ?
+               c->u.periph.pll_low : c->u.periph.pll_high;
+       source_rate = clk_get_rate(new_parent);
+
+       divider = clk_div71_get_divider(source_rate, rate, c->flags,
+               up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
+
+       if (divider < 0)
+               return c->min_rate;
+
+       round_rate = source_rate * 2 / (divider + 2);
+
+       if (round_rate > c->max_rate) {
+               divider += c->flags & DIV_U71_INT ? 2 : 1;
+#if !DIVIDER_1_5_ALLOWED
+               divider = max(2, divider);
+#endif
+               round_rate = source_rate * 2 / (divider + 2);
+       }
+
+       if (new_parent == c->u.periph.pll_high) {
+               /* Prevent oscillation across threshold */
+               if (round_rate <= c->u.periph.threshold)
+                       round_rate = c->u.periph.threshold;
+       }
+       return round_rate;
+}
+
+static long tegra11_1xbus_round_rate(struct clk *c, unsigned long rate)
+{
+       return tegra11_1xbus_round_updown(c, rate, true);
+}
+
+static int tegra11_1xbus_set_rate(struct clk *c, unsigned long rate)
+{
+       /* Compensate rate truncating during rounding */
+       return tegra11_periph_clk_set_rate(c, rate + 1);
+}
+
+static int tegra11_clk_1xbus_update(struct clk *c)
+{
+       int ret;
+       struct clk *new_parent;
+       unsigned long rate, old_rate;
+
+       if (detach_shared_bus)
+               return 0;
+
+       rate = tegra11_clk_shared_bus_update(c, NULL, NULL, NULL);
+
+       old_rate = clk_get_rate_locked(c);
+       pr_debug("\n1xbus %s: rate %lu on parent %s: new request %lu\n",
+                c->name, old_rate, c->parent->name, rate);
+       if (rate == old_rate)
+               return 0;
+
+       if (!c->u.periph.min_div_low || !c->u.periph.min_div_high) {
+               unsigned long r, m = c->max_rate;
+               r = clk_get_rate(c->u.periph.pll_low);
+               c->u.periph.min_div_low = DIV_ROUND_UP(r, m) * c->mul;
+               r = clk_get_rate(c->u.periph.pll_high);
+               c->u.periph.min_div_high = DIV_ROUND_UP(r, m) * c->mul;
+       }
+
+       new_parent = (rate <= c->u.periph.threshold) ?
+               c->u.periph.pll_low : c->u.periph.pll_high;
+
+       /*
+        * The transition procedure below is guaranteed to switch to the target
+        * parent/rate without violation of max clock limits. It would attempt
+        * to switch without dip in bus rate if it is possible, but this cannot
+        * be guaranteed (example: switch from 408 MHz : 1 to 624 MHz : 2 with
+        * maximum bus limit 408 MHz will be executed as 408 => 204 => 312 MHz,
+        * and there is no way to avoid rate dip in this case).
+        */
+       if (new_parent != c->parent) {
+               int interim_div = 0;
+               /* Switching to pll_high may over-clock bus if current divider
+                  is too small - increase divider to safe value */
+               if ((new_parent == c->u.periph.pll_high) &&
+                   (c->div < c->u.periph.min_div_high))
+                       interim_div = c->u.periph.min_div_high;
+
+               /* Switching to pll_low may dip down rate if current divider
+                  is too big - decrease divider as much as we can */
+               if ((new_parent == c->u.periph.pll_low) &&
+                   (c->div > c->u.periph.min_div_low))
+                       interim_div = c->u.periph.min_div_low;
+
+               if (interim_div) {
+                       u64 interim_rate = old_rate * c->div;
+                       do_div(interim_rate, interim_div);
+                       ret = clk_set_rate_locked(c, interim_rate);
+                       if (ret) {
+                               pr_err("Failed to set %s rate to %lu\n",
+                                      c->name, (unsigned long)interim_rate);
+                               return ret;
+                       }
+                       pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
+                                clk_get_rate_locked(c), c->parent->name);
+               }
+
+               ret = clk_set_parent_locked(c, new_parent);
+               if (ret) {
+                       pr_err("Failed to set %s parent %s\n",
+                              c->name, new_parent->name);
+                       return ret;
+               }
+
+               old_rate = clk_get_rate_locked(c);
+               pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
+                        old_rate, c->parent->name);
+               if (rate == old_rate)
+                       return 0;
+       }
+
+       ret = clk_set_rate_locked(c, rate);
+       if (ret) {
+               pr_err("Failed to set %s rate to %lu\n", c->name, rate);
+               return ret;
+       }
+       pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
+                clk_get_rate_locked(c), c->parent->name);
+       return 0;
+
+}
+
+static struct clk_ops tegra_1xbus_clk_ops = {
+       .init                   = &tegra11_periph_clk_init,
+       .enable                 = &tegra11_periph_clk_enable,
+       .disable                = &tegra11_periph_clk_disable,
+       .set_parent             = &tegra11_periph_clk_set_parent,
+       .set_rate               = &tegra11_1xbus_set_rate,
+       .round_rate             = &tegra11_1xbus_round_rate,
+       .reset                  = &tegra11_periph_clk_reset,
+       .shared_bus_update      = &tegra11_clk_1xbus_update,
+};
 
-#if !defined(CONFIG_TEGRA_SIMULATION_PLATFORM)
 /* msenc clock propagation WAR for bug 1005168 */
 static int tegra11_msenc_clk_enable(struct clk *c)
 {
@@ -4014,7 +4362,6 @@ static struct clk_ops tegra_msenc_clk_ops = {
        .round_rate             = &tegra11_periph_clk_round_rate,
        .reset                  = &tegra11_periph_clk_reset,
 };
-#endif
 /* Periph extended clock configuration ops */
 static int
 tegra11_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
@@ -4135,6 +4482,16 @@ static struct clk_ops tegra_dsi_clk_ops = {
        .reset                  = &tegra11_periph_clk_reset,
 };
 
+/* xusb common clock gate - enabled on init and never disabled */
+static void tegra11_xusb_gate_clk_init(struct clk *c)
+{
+       tegra11_periph_clk_enable(c);
+}
+
+static struct clk_ops tegra_xusb_gate_clk_ops = {
+       .init    = tegra11_xusb_gate_clk_init,
+};
+
 /* pciex clock support only reset function */
 static struct clk_ops tegra_pciex_clk_ops = {
        .reset    = tegra11_periph_clk_reset,
@@ -4238,17 +4595,23 @@ static void tegra11_emc_clk_init(struct clk *c)
        tegra_emc_dram_type_init(c);
 }
 
-static long tegra11_emc_clk_round_rate(struct clk *c, unsigned long rate)
+static long tegra11_emc_clk_round_updown(struct clk *c, unsigned long rate,
+                                        bool up)
 {
-       long new_rate = max(rate, c->min_rate);
+       unsigned long new_rate = max(rate, c->min_rate);
 
-       new_rate = tegra_emc_round_rate(new_rate);
-       if (new_rate < 0)
+       new_rate = tegra_emc_round_rate_updown(new_rate, up);
+       if (IS_ERR_VALUE(new_rate))
                new_rate = c->max_rate;
 
        return new_rate;
 }
 
+static long tegra11_emc_clk_round_rate(struct clk *c, unsigned long rate)
+{
+       return tegra11_emc_clk_round_updown(c, rate, true);
+}
+
 static int tegra11_emc_clk_set_rate(struct clk *c, unsigned long rate)
 {
        int ret;
@@ -4297,8 +4660,7 @@ static int tegra11_clk_emc_bus_update(struct clk *bus)
        if (detach_shared_bus)
                return 0;
 
-       rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
-       rate = clk_round_rate_locked(bus, rate);
+       rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL);
 
        old_rate = clk_get_rate_locked(bus);
        if (rate == old_rate)
@@ -4314,15 +4676,24 @@ static int tegra11_clk_emc_bus_update(struct clk *bus)
                                return -EINVAL;
                        }
 
-                       if (backup_rate < old_rate) /* skip lowering voltage */
-                               bus->auto_dvfs = false;
-                       ret = clk_set_rate_locked(bus, backup_rate);
-                       bus->auto_dvfs = true;
+                       /* set volatge for backup rate if going up */
+                       if (backup_rate > old_rate) {
+                               ret = tegra_dvfs_set_rate(bus, backup_rate);
+                               if (ret) {
+                                       pr_err("%s: dvfs failed on %s rate %lu\n",
+                                             __func__, bus->name, backup_rate);
+                                       return -EINVAL;
+                               }
+                       }
+
+                       trace_clock_set_rate(bus->name, backup_rate, 0);
+                       ret = bus->ops->set_rate(bus, backup_rate);
                        if (ret) {
                                pr_err("%s: Failed to backup %s for rate %lu\n",
                                       __func__, bus->name, rate);
                                return -EINVAL;
                        }
+                       clk_rate_change_notify(bus, backup_rate);
                }
                if (p->refcnt) {
                        pr_err("%s: %s has other than emc child\n",
@@ -4346,6 +4717,7 @@ static struct clk_ops tegra_emc_clk_ops = {
        .disable                = &tegra11_periph_clk_disable,
        .set_rate               = &tegra11_emc_clk_set_rate,
        .round_rate             = &tegra11_emc_clk_round_rate,
+       .round_rate_updown      = &tegra11_emc_clk_round_updown,
        .reset                  = &tegra11_periph_clk_reset,
        .shared_bus_update      = &tegra11_clk_emc_bus_update,
 };
@@ -4488,9 +4860,14 @@ static int tegra11_clk_cbus_enable(struct clk *c)
        return 0;
 }
 
-static long tegra11_clk_cbus_round_rate(struct clk *c, unsigned long rate)
+/* select 5 steps below top rate as fine granularity region */
+#define CBUS_FINE_GRANULARITY          12000000        /* 12 MHz */
+#define CBUS_FINE_GRANULARITY_RANGE    (5 * CBUS_FINE_GRANULARITY)
+
+static long tegra11_clk_cbus_round_updown(struct clk *c, unsigned long rate,
+                                         bool up)
 {
-       int i;
+       int i, n;
 
        if (!c->dvfs) {
                if (!c->min_rate)
@@ -4512,15 +4889,45 @@ static long tegra11_clk_cbus_round_rate(struct clk *c, unsigned long rate)
        }
        rate = max(rate, c->min_rate);
 
-       for (i = 0; i < (c->dvfs->num_freqs - 1); i++) {
+       /* for top rates in fine granularity region don't clip to dvfs table */
+       n = c->dvfs->num_freqs;
+       if ((n >= 2) && (c->dvfs->millivolts[n-1] <= c->dvfs->max_millivolts) &&
+           (rate > c->dvfs->freqs[n-2])) {
+               unsigned long threshold = max(c->dvfs->freqs[n-1],
+                       c->dvfs->freqs[n-2] + CBUS_FINE_GRANULARITY_RANGE);
+               threshold -= CBUS_FINE_GRANULARITY_RANGE;
+
+               if (rate == threshold)
+                       return threshold;
+
+               if (rate < threshold)
+                       return up ? threshold : c->dvfs->freqs[n-2];
+
+               rate = (up ? DIV_ROUND_UP(rate, CBUS_FINE_GRANULARITY) :
+                       rate / CBUS_FINE_GRANULARITY) * CBUS_FINE_GRANULARITY;
+               rate = clamp(rate, threshold, c->dvfs->freqs[n-1]);
+               return rate;
+       }
+
+       /* clip rate to dvfs table steps */
+       for (i = 0; ; i++) {
                unsigned long f = c->dvfs->freqs[i];
                int mv = c->dvfs->millivolts[i];
-               if ((f >= rate) || (mv >= c->dvfs->max_millivolts))
+               if ((f >= rate) || (mv >= c->dvfs->max_millivolts) ||
+                   ((i + 1) >=  c->dvfs->num_freqs)) {
+                       if (!up && i && (f > rate))
+                               i--;
                        break;
+               }
        }
        return c->dvfs->freqs[i];
 }
 
+static long tegra11_clk_cbus_round_rate(struct clk *c, unsigned long rate)
+{
+       return tegra11_clk_cbus_round_updown(c, rate, true);
+}
+
 static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort)
 {
        int ret = 0;
@@ -4681,11 +5088,12 @@ static int tegra11_clk_cbus_update(struct clk *bus)
        struct clk *top = NULL;
        unsigned long rate;
        unsigned long old_rate;
+       unsigned long ceiling;
 
        if (detach_shared_bus)
                return 0;
 
-       rate = tegra11_clk_shared_bus_update(bus, &top, &slow);
+       rate = tegra11_clk_shared_bus_update(bus, &top, &slow, &ceiling);
 
        /* use dvfs table of the slowest enabled client as cbus dvfs table */
        if (bus->dvfs && slow && (slow != bus->u.cbus.slow_user)) {
@@ -4704,7 +5112,7 @@ static int tegra11_clk_cbus_update(struct clk *bus)
        bus->u.cbus.slow_user = slow;
        bus->u.cbus.top_user = top;
 
-       rate = bus->ops->round_rate(bus, rate);
+       rate = tegra11_clk_cap_shared_bus(bus, rate, ceiling);
        mv = tegra_dvfs_predict_millivolts(bus, rate);
        if (IS_ERR_VALUE(mv))
                return -EINVAL;
@@ -4719,7 +5127,7 @@ static int tegra11_clk_cbus_update(struct clk *bus)
        }
 
        old_rate = clk_get_rate_locked(bus);
-       if (old_rate != rate) {
+       if (IS_ENABLED(CONFIG_TEGRA_MIGRATE_CBUS_USERS) || (old_rate != rate)) {
                ret = bus->ops->set_rate(bus, rate);
                if (ret)
                        return ret;
@@ -4744,8 +5152,7 @@ static int tegra11_clk_cbus_update(struct clk *bus)
        if (detach_shared_bus)
                return 0;
 
-       rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
-       rate = clk_round_rate_locked(bus, rate);
+       rate = tegra11_clk_shared_bus_update(bus, NULL, NULL, NULL);
 
        old_rate = clk_get_rate_locked(bus);
        if (rate == old_rate)
@@ -4810,6 +5217,7 @@ static struct clk_ops tegra_clk_cbus_ops = {
        .enable = tegra11_clk_cbus_enable,
        .set_rate = tegra11_clk_cbus_set_rate,
        .round_rate = tegra11_clk_cbus_round_rate,
+       .round_rate_updown = tegra11_clk_cbus_round_updown,
        .shared_bus_update = tegra11_clk_cbus_update,
 };
 
@@ -4820,10 +5228,17 @@ static struct clk_ops tegra_clk_cbus_ops = {
  * clock to each user.  The frequency of the bus is set to the highest
  * enabled shared_bus_user clock, with a minimum value set by the
  * shared bus.
+ *
+ * Optionally shared bus may support users migration. Since shared bus and
+ * its * children (users) have reversed rate relations: user rates determine
+ * bus rate, * switching user from one parent/bus to another may change rates
+ * of both parents. Therefore we need a cross-bus lock on top of individual
+ * user and bus locks. For now, limit bus switch support to cbus only if
+ * CONFIG_TEGRA_MIGRATE_CBUS_USERS is set.
  */
 
-static unsigned long tegra11_clk_shared_bus_update(
-       struct clk *bus, struct clk **bus_top, struct clk **bus_slow)
+static unsigned long tegra11_clk_shared_bus_update(struct clk *bus,
+       struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap)
 {
        struct clk *c;
        struct clk *slow = NULL;
@@ -4833,8 +5248,10 @@ static unsigned long tegra11_clk_shared_bus_update(
        unsigned long top_rate = 0;
        unsigned long rate = bus->min_rate;
        unsigned long bw = 0;
+       unsigned long iso_bw = 0;
        unsigned long ceiling = bus->max_rate;
-       u8 emc_bw_efficiency = tegra_emc_bw_efficiency;
+       unsigned long ceiling_but_iso = bus->max_rate;
+       u32 usage_flags = 0;
 
        list_for_each_entry(c, &bus->shared_bus_list,
                        u.shared_bus_user.node) {
@@ -4845,16 +5262,27 @@ static unsigned long tegra11_clk_shared_bus_update(
                 * bus just because ceiling is set.
                 */
                if (c->u.shared_bus_user.enabled ||
-                   (c->u.shared_bus_user.mode == SHARED_CEILING)) {
+                   (c->u.shared_bus_user.mode == SHARED_CEILING) ||
+                   (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) {
                        unsigned long request_rate = c->u.shared_bus_user.rate *
                                (c->div ? : 1);
+                       usage_flags |= c->u.shared_bus_user.usage_flag;
 
                        switch (c->u.shared_bus_user.mode) {
+                       case SHARED_ISO_BW:
+                               iso_bw += request_rate;
+                               if (iso_bw > bus->max_rate)
+                                       iso_bw = bus->max_rate;
+                               /* fall thru */
                        case SHARED_BW:
                                bw += request_rate;
                                if (bw > bus->max_rate)
                                        bw = bus->max_rate;
                                break;
+                       case SHARED_CEILING_BUT_ISO:
+                               ceiling_but_iso =
+                                       min(request_rate, ceiling_but_iso);
+                               break;
                        case SHARED_CEILING:
                                ceiling = min(request_rate, ceiling);
                                break;
@@ -4884,21 +5312,42 @@ static unsigned long tegra11_clk_shared_bus_update(
                }
        }
 
-       if ((bus->flags & PERIPH_EMC_ENB) && bw && (emc_bw_efficiency < 100)) {
-               bw = emc_bw_efficiency ?
-                       (bw / emc_bw_efficiency) : bus->max_rate;
-               bw = (bw < bus->max_rate / 100) ? (bw * 100) : bus->max_rate;
-       }
+       if (bus->flags & PERIPH_EMC_ENB)
+               bw = tegra_emc_apply_efficiency(
+                       bw, iso_bw, bus->max_rate, usage_flags, NULL);
 
-       rate = override_rate ? : min(max(rate, bw), ceiling);
+       rate = override_rate ? : max(rate, bw);
+       ceiling = min(ceiling, ceiling_but_iso);
+       ceiling = override_rate ? bus->max_rate : ceiling;
 
-       if (bus_top)
+       if (bus_top && bus_slow && rate_cap) {
+               /* If dynamic bus dvfs table, let the caller to complete
+                  rounding and aggregation */
                *bus_top = top;
-       if (bus_slow)
                *bus_slow = slow;
+               *rate_cap = ceiling;
+       } else {
+               /* If satic bus dvfs table, complete rounding and aggregation */
+               rate = tegra11_clk_cap_shared_bus(bus, rate, ceiling);
+       }
+
        return rate;
 };
 
+static unsigned long tegra11_clk_cap_shared_bus(struct clk *bus,
+       unsigned long rate, unsigned long ceiling)
+{
+       if (bus->ops && bus->ops->round_rate_updown)
+               ceiling = bus->ops->round_rate_updown(bus, ceiling, false);
+
+       rate = min(rate, ceiling);
+
+       if (bus->ops && bus->ops->round_rate)
+               rate = bus->ops->round_rate(bus, rate);
+
+       return rate;
+}
+
 static int tegra_clk_shared_bus_migrate_users(struct clk *user)
 {
        if (detach_shared_bus)
@@ -4917,6 +5366,12 @@ static void tegra_clk_shared_bus_user_init(struct clk *c)
        c->state = OFF;
        c->set = true;
 
+       if ((c->u.shared_bus_user.mode == SHARED_CEILING) ||
+           (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) {
+               c->state = ON;
+               c->refcnt++;
+       }
+
        if (c->u.shared_bus_user.client_id) {
                c->u.shared_bus_user.client =
                        tegra_get_clock_by_name(c->u.shared_bus_user.client_id);
@@ -4936,15 +5391,9 @@ static void tegra_clk_shared_bus_user_init(struct clk *c)
                &c->parent->shared_bus_list);
 }
 
-/*
- * Shared bus and its children/users have reversed rate relations - user rates
- * determine bus rate. Hence switching user from one parent/bus to another may
- * change rates of both parents. Therefore we need a cross-bus lock on top of
- * individual user and bus locks. For now limit bus switch support to cansleep
- * users with cross-clock mutex only.
- */
 static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
 {
+       int ret;
        const struct clk_mux_sel *sel;
 
        if (detach_shared_bus)
@@ -4967,7 +5416,15 @@ static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
                clk_enable(p);
 
        list_move_tail(&c->u.shared_bus_user.node, &p->shared_bus_list);
-       tegra_clk_shared_bus_update(p);
+       ret = tegra_clk_shared_bus_update(p);
+       if (ret) {
+               list_move_tail(&c->u.shared_bus_user.node,
+                              &c->parent->shared_bus_list);
+               tegra_clk_shared_bus_update(c->parent);
+               clk_disable(p);
+               return ret;
+       }
+
        tegra_clk_shared_bus_update(c->parent);
 
        if (c->refcnt)
@@ -4980,13 +5437,15 @@ static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
 
 static int tegra_clk_shared_bus_user_set_rate(struct clk *c, unsigned long rate)
 {
+       int ret;
+
        c->u.shared_bus_user.rate = rate;
-       tegra_clk_shared_bus_update(c->parent);
+       ret = tegra_clk_shared_bus_update(c->parent);
 
-       if (c->cross_clk_mutex && clk_cansleep(c))
+       if (!ret && c->cross_clk_mutex && clk_cansleep(c))
                tegra_clk_shared_bus_migrate_users(c);
 
-       return 0;
+       return ret;
 }
 
 static long tegra_clk_shared_bus_user_round_rate(
@@ -4995,7 +5454,8 @@ static long tegra_clk_shared_bus_user_round_rate(
        /* Defer rounding requests until aggregated. BW users must not be
           rounded at all, others just clipped to bus range (some clients
           may use round api to find limits) */
-       if (c->u.shared_bus_user.mode != SHARED_BW) {
+       if ((c->u.shared_bus_user.mode != SHARED_BW) &&
+           (c->u.shared_bus_user.mode != SHARED_ISO_BW)) {
                if (c->div > 1)
                        rate *= c->div;
 
@@ -5012,14 +5472,14 @@ static long tegra_clk_shared_bus_user_round_rate(
 
 static int tegra_clk_shared_bus_user_enable(struct clk *c)
 {
-       int ret = 0;
+       int ret;
 
        c->u.shared_bus_user.enabled = true;
-       tegra_clk_shared_bus_update(c->parent);
-       if (c->u.shared_bus_user.client)
+       ret = tegra_clk_shared_bus_update(c->parent);
+       if (!ret && c->u.shared_bus_user.client)
                ret = clk_enable(c->u.shared_bus_user.client);
 
-       if (c->cross_clk_mutex && clk_cansleep(c))
+       if (!ret && c->cross_clk_mutex && clk_cansleep(c))
                tegra_clk_shared_bus_migrate_users(c);
 
        return ret;
@@ -5099,6 +5559,9 @@ static void tegra11_clk_coupled_gate_disable(struct clk *c)
 
        tegra11_periph_clk_disable(c);
 
+       if (!c->refcnt) /* happens only on boot clean-up: don't propagate */
+               return;
+
        for (sel = c->inputs; sel->input != NULL; sel++) {
                if (sel->input == c->parent)
                        continue;
@@ -5293,7 +5756,7 @@ static struct clk tegra_pll_m_out1 = {
        .parent    = &tegra_pll_m,
        .reg       = 0x94,
        .reg_shift = 0,
-       .max_rate  = 600000000,
+       .max_rate  = 1066000000,
 };
 
 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
@@ -5411,7 +5874,7 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
        { 19200000, 216000000, 720, 16, 4, 12},
        { 26000000, 216000000, 864, 26, 4, 12},
 
-       { 12000000, 594000000,  99,  2, 1,  8},
+       { 12000000, 594000000,  99,  1, 2, 15},
        { 13000000, 594000000, 594, 13, 1, 12},
        { 16800000, 594000000, 495, 14, 1, 12},
        { 19200000, 594000000, 495, 16, 1, 12},
@@ -5596,9 +6059,6 @@ static struct clk tegra_pll_x_out0 = {
        .max_rate  = 700000000,
 };
 
-/* FIXME: remove; for now, should be always checked-in as "0" */
-#define USE_LP_CPU_TO_TEST_DFLL                0
-
 static struct clk tegra_dfll_cpu = {
        .name      = "dfll_cpu",
        .flags     = DFLL,
@@ -5613,14 +6073,14 @@ static struct clk tegra_pll_re_vco = {
        .ops       = &tegra_pllre_ops,
        .reg       = 0x4c4,
        .parent    = &tegra_pll_ref,
-       .max_rate  = 600000000,
+       .max_rate  = 672000000,
        .u.pll = {
                .input_min = 12000000,
                .input_max = 1000000000,
                .cf_min    = 12000000,
                .cf_max    = 19200000,  /* s/w policy, h/w capability 38 MHz */
                .vco_min   = 300000000,
-               .vco_max   = 600000000,
+               .vco_max   = 672000000,
                .lock_delay = 300,
                .round_p_to_pdiv = pllre_round_p_to_pdiv,
        },
@@ -5631,13 +6091,14 @@ static struct clk tegra_pll_re_out = {
        .ops       = &tegra_pllre_out_ops,
        .parent    = &tegra_pll_re_vco,
        .reg       = 0x4c4,
-       .max_rate  = 600000000,
+       .max_rate  = 672000000,
 };
 
 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
        /* PLLE special case: use cpcon field to store cml divider value */
        { 336000000, 100000000, 100, 21,  16, 11},
        { 312000000, 100000000, 200, 26,  24, 13},
+       {  12000000, 100000000, 200,  1,  24, 13},
        { 0, 0, 0, 0, 0, 0 },
 };
 
@@ -5866,9 +6327,6 @@ static struct clk_mux_sel mux_cclk_lp[] = {
        /* { .input = &tegra_pll_c2,    .value = 6}, - no use on tegra11x */
        /* { .input = &tegra_clk_c3,    .value = 7}, - no use on tegra11x */
        { .input = &tegra_pll_x_out0,   .value = 8},
-#if USE_LP_CPU_TO_TEST_DFLL
-       { .input = &tegra_dfll_cpu,     .value = 15},
-#endif
        { .input = &tegra_pll_x,        .value = 8 | SUPER_LP_DIV2_BYPASS},
        { 0, 0},
 };
@@ -5933,9 +6391,6 @@ static struct clk tegra_clk_virtual_cpu_lp = {
        .u.cpu = {
                .main      = &tegra_pll_x,
                .backup    = &tegra_pll_p_out4,
-#if USE_LP_CPU_TO_TEST_DFLL
-               .dynamic   = &tegra_dfll_cpu,
-#endif
                .mode      = MODE_LP,
        },
 };
@@ -6173,13 +6628,6 @@ static struct clk_mux_sel mux_clk_32k[] = {
        { 0, 0},
 };
 
-/* xusb_hs has an alternative source, that is not used - therefore, xusb_hs
-   is modeled as a single source mux */
-static struct clk_mux_sel mux_pllu_60M[] = {
-       { .input = &tegra_pll_u_60M, .value = 1},
-       { 0, 0},
-};
-
 static struct raw_notifier_head emc_rate_change_nh;
 
 static struct clk tegra_clk_emc = {
@@ -6196,6 +6644,31 @@ static struct clk tegra_clk_emc = {
        .rate_change_nh = &emc_rate_change_nh,
 };
 
+static struct raw_notifier_head host1x_rate_change_nh;
+
+static struct clk tegra_clk_host1x = {
+       .name      = "host1x",
+       .lookup    = {
+               .dev_id = "host1x",
+       },
+       .ops       = &tegra_1xbus_clk_ops,
+       .reg       = 0x180,
+       .inputs    = mux_pllm_pllc_pllp_plla,
+       .flags     = MUX | DIV_U71 | DIV_U71_INT,
+       .max_rate  = 384000000,
+       .min_rate  = 12000000,
+       .u.periph = {
+               .clk_num   = 28,
+               .pll_low = &tegra_pll_p,
+#ifdef CONFIG_TEGRA_PLLM_SCALED
+               .pll_high = &tegra_pll_c,
+#else
+               .pll_high = &tegra_pll_m,
+#endif
+       },
+       .rate_change_nh = &host1x_rate_change_nh,
+};
+
 #ifdef CONFIG_TEGRA_DUAL_CBUS
 
 static struct raw_notifier_head c2bus_rate_change_nh;
@@ -6205,7 +6678,7 @@ static struct clk tegra_clk_c2bus = {
        .name      = "c2bus",
        .parent    = &tegra_pll_c2,
        .ops       = &tegra_clk_cbus_ops,
-       .max_rate  = 700000000,
+       .max_rate  = 864000000,
        .mul       = 1,
        .div       = 1,
        .flags     = PERIPH_ON_CBUS,
@@ -6228,7 +6701,13 @@ static struct clk tegra_clk_c3bus = {
        .rate_change_nh = &c3bus_rate_change_nh,
 };
 
+#ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
 static DEFINE_MUTEX(cbus_mutex);
+#define CROSS_CBUS_MUTEX (&cbus_mutex)
+#else
+#define CROSS_CBUS_MUTEX NULL
+#endif
+
 
 static struct clk_mux_sel mux_clk_cbus[] = {
        { .input = &tegra_clk_c2bus, .value = 0},
@@ -6252,7 +6731,7 @@ static struct clk_mux_sel mux_clk_cbus[] = {
                        .client_div = _div,             \
                        .mode = _mode,                  \
                },                                      \
-               .cross_clk_mutex = &cbus_mutex,         \
+               .cross_clk_mutex = CROSS_CBUS_MUTEX,    \
        }
 
 #else
@@ -6274,6 +6753,35 @@ static struct clk tegra_clk_cbus = {
 };
 #endif
 
+static void tegra11_camera_mclk_init(struct clk *c)
+{
+       c->state = OFF;
+       c->set = true;
+       c->parent = tegra_get_clock_by_name("vi_sensor");
+       c->max_rate = c->parent->max_rate;
+}
+
+static int tegra11_camera_mclk_set_rate(struct clk *c, unsigned long rate)
+{
+       return clk_set_rate(c->parent, rate);
+}
+
+static struct clk_ops tegra_camera_mclk_ops = {
+       .init     = tegra11_camera_mclk_init,
+       .enable   = tegra11_periph_clk_enable,
+       .disable  = tegra11_periph_clk_disable,
+       .set_rate = tegra11_camera_mclk_set_rate,
+};
+
+static struct clk tegra_camera_mclk = {
+       .name = "mclk",
+       .ops = &tegra_camera_mclk_ops,
+       .u.periph = {
+               .clk_num = 92, /* csus */
+       },
+       .flags = PERIPH_NO_RESET,
+};
+
 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
        {                                               \
                .name      = _name,                     \
@@ -6343,6 +6851,23 @@ static struct clk tegra_clk_cbus = {
                        .mode = _mode,                  \
                },                                      \
        }
+#define SHARED_EMC_CLK(_name, _dev, _con, _parent, _id, _div, _mode, _flag)\
+       {                                               \
+               .name      = _name,                     \
+               .lookup    = {                          \
+                       .dev_id    = _dev,              \
+                       .con_id    = _con,              \
+               },                                      \
+               .ops = &tegra_clk_shared_bus_user_ops,  \
+               .parent = _parent,                      \
+               .u.shared_bus_user = {                  \
+                       .client_id = _id,               \
+                       .client_div = _div,             \
+                       .mode = _mode,                  \
+                       .usage_flag = _flag,            \
+               },                                      \
+       }
+
 struct clk tegra_list_clks[] = {
        PERIPH_CLK("apbdma",    "tegra-apbdma",         NULL,   34,     0,      26000000,  mux_clk_m,                   0),
        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
@@ -6364,20 +6889,17 @@ struct clk tegra_list_clks[] = {
        D_AUDIO_CLK("dam0",     "tegra30-dam.0",        NULL,   108,    0x3d8,  19910000,  mux_d_audio_clk,     MUX | DIV_U71 | PERIPH_ON_APB),
        D_AUDIO_CLK("dam1",     "tegra30-dam.1",        NULL,   109,    0x3dc,  19910000,  mux_d_audio_clk,     MUX | DIV_U71 | PERIPH_ON_APB),
        D_AUDIO_CLK("dam2",     "tegra30-dam.2",        NULL,   110,    0x3e0,  19910000,  mux_d_audio_clk,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("adx",       "adx",                  NULL,   154,    0x638,  19910000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("amx",       "amx",                  NULL,   153,    0x63c,  19910000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("adx",       "adx",                  NULL,   154,    0x638,  24730000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("amx",       "amx",                  NULL,   153,    0x63c,  24730000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("hda",       "tegra30-hda",          "hda",          125,    0x428,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("hda2codec_2x",      "tegra30-hda",  "hda2codec",    111,    0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("hda2hdmi",  "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   PERIPH_ON_APB),
-       PERIPH_CLK("sbc1",      "tegra11-spi.0",        NULL,   41,     0x134,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc2",      "tegra11-spi.1",        NULL,   44,     0x118,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc3",      "tegra11-spi.2",        NULL,   46,     0x11c,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc4",      "tegra11-spi.3",        NULL,   68,     0x1b4,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc5",      "tegra11-spi.4",        NULL,   104,    0x3c8,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sbc6",      "tegra11-spi.5",        NULL,   105,    0x3cc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata_oob",  "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata",      "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata_cold", "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   PERIPH_ON_APB),
+       PERIPH_CLK("sbc1",      "spi-tegra114.0",       NULL,   41,     0x134,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc2",      "spi-tegra114.1",       NULL,   44,     0x118,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc3",      "spi-tegra114.2",       NULL,   46,     0x11c,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc4",      "spi-tegra114.3",       NULL,   68,     0x1b4,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc5",      "spi-tegra114.4",       NULL,   104,    0x3c8,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+       PERIPH_CLK("sbc6",      "spi-tegra114.5",       NULL,   105,    0x3cc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK_EX("ndflash", "tegra_nand",          NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB,  &tegra_nand_clk_ops),
        PERIPH_CLK("ndspeed",   "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
@@ -6388,6 +6910,7 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("vcp",       "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0),
        PERIPH_CLK("bsea",      "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0),
        PERIPH_CLK("bsev",      "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0),
+       PERIPH_CLK("cec",       "tegra_cec",            NULL,   136,    0,      250000000, mux_clk_m,                   PERIPH_ON_APB),
        PERIPH_CLK("vde",       "vde",                  NULL,   61,     0x1c8,  600000000, mux_pllp_pllc2_c_c3_pllm_clkm,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
        PERIPH_CLK("csite",     "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("la",        "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
@@ -6395,32 +6918,25 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("owr",       "tegra_w1",             NULL,   71,     0x1cc,  12000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("nor",       "tegra-nor",            NULL,   42,     0x1d0,  127000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
        PERIPH_CLK("mipi",      "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-#ifdef CONFIG_ARCH_TEGRA_14x_SOC
-       PERIPH_CLK("mipibif",   "tegra-mipi-bif",       NULL,   173,    0x660,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-#endif
        PERIPH_CLK("i2c1",      "tegra11-i2c.0",        "div-clk",      12,     0x124,  136000000, mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
        PERIPH_CLK("i2c2",      "tegra11-i2c.1",        "div-clk",      54,     0x198,  136000000, mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
        PERIPH_CLK("i2c3",      "tegra11-i2c.2",        "div-clk",      67,     0x1b8,  136000000, mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
        PERIPH_CLK("i2c4",      "tegra11-i2c.3",        "div-clk",      103,    0x3c4,  136000000, mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
-       PERIPH_CLK("i2c5",      "tegra11-i2c.4",        "div-clk",      47,     0x128,  58300000,  mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
-       PERIPH_CLK("mipi-cal",  "mipi-cal",             NULL,   56,     0,      60000000,  mux_clk_m,   0),
-       PERIPH_CLK("uarta",     "tegra_uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
-       PERIPH_CLK("uartb",     "tegra_uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
-       PERIPH_CLK("uartc",     "tegra_uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
-       PERIPH_CLK("uartd",     "tegra_uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
+       PERIPH_CLK("i2c5",      "tegra11-i2c.4",        "div-clk",      47,     0x128,  64000000,  mux_pllp_clkm,       MUX | DIV_U16 | PERIPH_ON_APB),
+       PERIPH_CLK("mipi-cal",  "mipi-cal",             NULL,   56,     0,      60000000,  mux_clk_m,                   PERIPH_ON_APB),
+       PERIPH_CLK("mipi-cal-fixed", "mipi-cal-fixed",  NULL,   0,      0,      108000000, mux_pllp_out3,       PERIPH_NO_ENB),
+       PERIPH_CLK("uarta",     "serial-tegra.0",       NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
+       PERIPH_CLK("uartb",     "serial-tegra.1",       NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
+       PERIPH_CLK("uartc",     "serial-tegra.2",       NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
+       PERIPH_CLK("uartd",     "serial-tegra.3",       NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
        PERIPH_CLK("uarte",     "tegra_uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
-       PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
-       PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
-       PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
-       PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
-       PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
-#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
-       PERIPH_CLK("msenc",     "msenc",                NULL,   60,     0x170,  600000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
-#else
+       PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  864000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
+       PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  864000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
+       PERIPH_CLK_EX("vi",     "vi",                   "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
+       PERIPH_CLK("vi_sensor", NULL,                   "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
+       PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  864000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
        PERIPH_CLK_EX("msenc",  "msenc",                NULL,   91,     0x1f0,  600000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops),
-#endif
        PERIPH_CLK("tsec",      "tsec",                 NULL,   83,     0x1f4,  600000000, mux_pllp_pllc2_c_c3_pllm_clkm,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
-       PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  384000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
        PERIPH_CLK_EX("dtv",    "dtv",                  NULL,   79,     0x1dc,  250000000, mux_clk_m,                   PERIPH_ON_APB,  &tegra_dtv_clk_ops),
        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  297000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8 | DIV_U71),
        PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8),
@@ -6432,12 +6948,12 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK_EX("dsib",   "tegradc.1",            "dsib", 82,     0x4b8,  500000000, mux_plld_out0_plld2_out0,    MUX | PLLD,     &tegra_dsi_clk_ops),
        PERIPH_CLK("dsi1-fixed", "tegradc.0",           "dsi-fixed",    0,      0,      108000000, mux_pllp_out3,       PERIPH_NO_ENB),
        PERIPH_CLK("dsi2-fixed", "tegradc.1",           "dsi-fixed",    0,      0,      108000000, mux_pllp_out3,       PERIPH_NO_ENB),
-       PERIPH_CLK("csi",       "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0),
-       PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
-       PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
-       PERIPH_CLK("cilab",     "tegra_camera",         "cilab", 144,   0x614,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
-       PERIPH_CLK("cilcd",     "tegra_camera",         "cilcd", 145,   0x618,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
-       PERIPH_CLK("cile",      "tegra_camera",         "cile",  146,   0x61c,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
+       PERIPH_CLK("csi",       "vi",                   "csi",  52,     0,      102000000, mux_pllp_out3,               0),
+       PERIPH_CLK("isp",       "vi",                   "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
+       PERIPH_CLK("csus",      "vi",                   "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
+       PERIPH_CLK("cilab",     "vi",                   "cilab", 144,   0x614,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
+       PERIPH_CLK("cilcd",     "vi",                   "cilcd", 145,   0x618,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
+       PERIPH_CLK("cile",      "vi",                   "cile",  146,   0x61c,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
        PERIPH_CLK("dsialp",    "tegradc.0",            "dsialp", 147,  0x620,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
        PERIPH_CLK("dsiblp",    "tegradc.1",            "dsiblp", 148,  0x624,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
 
@@ -6464,54 +6980,64 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("usb1.sclk", "tegra-ehci.0",         "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("usb2.sclk", "tegra-ehci.1",         "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("usb3.sclk", "tegra-ehci.2",         "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sdmmc3.sclk",       "sdhci-tegra.2",        "sclk", &tegra_clk_sbus_cmplx,  NULL,   0,      0),
+       SHARED_CLK("sdmmc4.sclk", "sdhci-tegra.3",      "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("wake.sclk", "wake_sclk",            "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("camera.sclk",       "vi",           "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("mon.avp",   "tegra_actmon",         "avp",  &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("cap.sclk",  "cap_sclk",             NULL,   &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
+       SHARED_CLK("cap.throttle.sclk", "cap_throttle", NULL,   &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
        SHARED_CLK("floor.sclk", "floor_sclk",          NULL,   &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("override.sclk", "override_sclk",    NULL,   &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
-       SHARED_CLK("sbc1.sclk", "tegra11-spi.0",        "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
-       SHARED_CLK("sbc2.sclk", "tegra11-spi.1",        "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
-       SHARED_CLK("sbc3.sclk", "tegra11-spi.2",        "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
-       SHARED_CLK("sbc4.sclk", "tegra11-spi.3",        "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
-       SHARED_CLK("sbc5.sclk", "tegra11-spi.4",        "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
-       SHARED_CLK("sbc6.sclk", "tegra11-spi.5",        "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
-
-       SHARED_CLK("avp.emc",   "tegra-avp",            "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("cpu.emc",   "cpu",                  "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("disp1.emc", "tegradc.0",            "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
-       SHARED_CLK("disp2.emc", "tegradc.1",            "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
-       SHARED_CLK("hdmi.emc",  "hdmi",                 "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("usbd.emc",  "tegra-udc.0",          "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("usb1.emc",  "tegra-ehci.0",         "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("usb2.emc",  "tegra-ehci.1",         "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("usb3.emc",  "tegra-ehci.2",         "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("mon.emc",   "tegra_actmon",         "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("cap.emc",   "cap.emc",              NULL,   &tegra_clk_emc, NULL, 0, SHARED_CEILING),
-       SHARED_CLK("3d.emc",    "tegra_gr3d",           "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("2d.emc",    "tegra_gr2d",           "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("msenc.emc", "tegra_msenc",          "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
-       SHARED_CLK("tsec.emc",  "tegra_tsec",           "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("sdmmc4.emc", "sdhci-tegra.3",       "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("camera.emc", "tegra_camera",        "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
-       SHARED_CLK("iso.emc",   "iso",                  "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
-       SHARED_CLK("floor.emc", "floor.emc",            NULL,   &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("override.emc", "override.emc",      NULL,   &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE),
-       SHARED_CLK("edp.emc",   "edp.emc",              NULL,   &tegra_clk_emc, NULL, 0, SHARED_CEILING),
+
+       SHARED_EMC_CLK("avp.emc",       "tegra-avp",    "emc",  &tegra_clk_emc, NULL, 0, 0, 0),
+       SHARED_EMC_CLK("disp1.emc", "tegradc.0",        "emc",  &tegra_clk_emc,
+                               NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC1)),
+       SHARED_EMC_CLK("disp2.emc", "tegradc.1",        "emc",  &tegra_clk_emc,
+                               NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC2)),
+       SHARED_EMC_CLK("mon_cpu.emc",   "tegra_mon",            "cpu_emc",
+                                               &tegra_clk_emc, NULL, 0, 0, 0),
+       SHARED_EMC_CLK("hdmi.emc",      "hdmi",         "emc",  &tegra_clk_emc, NULL, 0, 0, 0),
+       SHARED_EMC_CLK("usbd.emc",      "tegra-udc.0",  "emc",  &tegra_clk_emc, NULL, 0, 0, 0),
+       SHARED_EMC_CLK("usb1.emc",      "tegra-ehci.0", "emc",  &tegra_clk_emc, NULL, 0, 0, 0),
+       SHARED_EMC_CLK("usb2.emc",      "tegra-ehci.1", "emc",  &tegra_clk_emc, NULL, 0, 0, 0),
+       SHARED_EMC_CLK("usb3.emc",      "tegra-ehci.2", "emc",  &tegra_clk_emc, NULL, 0, 0, 0),
+       SHARED_EMC_CLK("mon.emc",       "tegra_actmon", "emc",  &tegra_clk_emc, NULL, 0, 0, 0),
+       SHARED_EMC_CLK("cap.emc",       "cap.emc",      NULL,   &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
+       SHARED_EMC_CLK("cap.throttle.emc", "cap_throttle", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
+       SHARED_EMC_CLK("3d.emc",        "tegra_gr3d",   "emc",  &tegra_clk_emc, NULL, 0, 0,             BIT(EMC_USER_3D)),
+       SHARED_EMC_CLK("2d.emc",        "tegra_gr2d",   "emc",  &tegra_clk_emc, NULL, 0, 0,             BIT(EMC_USER_2D)),
+       SHARED_EMC_CLK("msenc.emc",     "tegra_msenc",  "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW,     BIT(EMC_USER_MSENC)),
+       SHARED_EMC_CLK("tsec.emc",      "tegra_tsec",   "emc",  &tegra_clk_emc, NULL, 0, 0, 0),
+       SHARED_EMC_CLK("sdmmc3.emc",    "sdhci-tegra.2",        "emc",  &tegra_clk_emc, NULL,   0,      0,      0),
+       SHARED_EMC_CLK("sdmmc4.emc", "sdhci-tegra.3",   "emc",  &tegra_clk_emc, NULL, 0, 0, 0),
+       SHARED_EMC_CLK("camera.emc", "vi",              "emc",  &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI)),
+       SHARED_EMC_CLK("iso.emc",       "iso",          "emc",  &tegra_clk_emc, NULL, 0, 0, 0),
+       SHARED_EMC_CLK("floor.emc",     "floor.emc",    NULL,   &tegra_clk_emc, NULL, 0, 0, 0),
+       SHARED_EMC_CLK("override.emc", "override.emc",  NULL,   &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE, 0),
+       SHARED_EMC_CLK("edp.emc",       "edp.emc",      NULL,   &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
+       SHARED_EMC_CLK("battery.emc", "battery_edp",    "emc",  &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
+       SHARED_EMC_CLK("floor.profile.emc", "profile.emc", NULL, &tegra_clk_emc, NULL,  0, 0, 0),
 
 #ifdef CONFIG_TEGRA_DUAL_CBUS
        DUAL_CBUS_CLK("3d.cbus",        "tegra_gr3d",           "gr3d", &tegra_clk_c2bus, "3d",  0, 0),
        DUAL_CBUS_CLK("2d.cbus",        "tegra_gr2d",           "gr2d", &tegra_clk_c2bus, "2d",  0, 0),
        DUAL_CBUS_CLK("epp.cbus",       "tegra_gr2d",           "epp",  &tegra_clk_c2bus, "epp", 0, 0),
        SHARED_CLK("cap.c2bus",         "cap.c2bus",            NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.throttle.c2bus", "cap_throttle",        NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
        SHARED_CLK("floor.c2bus",       "floor.c2bus",          NULL,   &tegra_clk_c2bus, NULL,  0, 0),
        SHARED_CLK("override.c2bus",    "override.c2bus",       NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_OVERRIDE),
        SHARED_CLK("edp.c2bus",         "edp.c2bus",            NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("battery.c2bus",     "battery_edp",          "gpu",  &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.profile.c2bus", "profile.c2bus",        NULL,   &tegra_clk_c2bus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("floor.profile.c2bus", "profile.c2bus",      NULL,   &tegra_clk_c2bus, NULL,  0, 0),
 
        DUAL_CBUS_CLK("msenc.cbus",     "tegra_msenc",          "msenc",  &tegra_clk_c3bus, "msenc", 0, 0),
        DUAL_CBUS_CLK("tsec.cbus",      "tegra_tsec",           "tsec",   &tegra_clk_c3bus, "tsec", 0, 0),
        DUAL_CBUS_CLK("vde.cbus",       "tegra-avp",            "vde",    &tegra_clk_c3bus, "vde", 0, 0),
        DUAL_CBUS_CLK("se.cbus",        "tegra11-se",           NULL,     &tegra_clk_c3bus, "se",  0, 0),
        SHARED_CLK("cap.c3bus",         "cap.c3bus",            NULL,   &tegra_clk_c3bus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.throttle.c3bus", "cap_throttle",        NULL,   &tegra_clk_c3bus, NULL,  0, SHARED_CEILING),
        SHARED_CLK("floor.c3bus",       "floor.c3bus",          NULL,   &tegra_clk_c3bus, NULL,  0, 0),
        SHARED_CLK("override.c3bus",    "override.c3bus",       NULL,   &tegra_clk_c3bus, NULL,  0, SHARED_OVERRIDE),
 #else
@@ -6523,46 +7049,91 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("vde.cbus",  "tegra-avp",            "vde",  &tegra_clk_cbus, "vde", 0, 0),
        SHARED_CLK("se.cbus",   "tegra11-se",           NULL,   &tegra_clk_cbus, "se",  0, 0),
        SHARED_CLK("cap.cbus",  "cap.cbus",             NULL,   &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.throttle.cbus", "cap_throttle", NULL,   &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
        SHARED_CLK("floor.cbus", "floor.cbus",          NULL,   &tegra_clk_cbus, NULL,  0, 0),
        SHARED_CLK("override.cbus", "override.cbus",    NULL,   &tegra_clk_cbus, NULL,  0, SHARED_OVERRIDE),
        SHARED_CLK("edp.cbus",  "edp.cbus",             NULL,   &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("battery.cbus", "battery_edp",       "gpu",  &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("cap.profile.cbus", "profile.cbus",  NULL,   &tegra_clk_cbus, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("floor.profile.cbus", "profile.cbus", NULL,  &tegra_clk_cbus, NULL,  0, 0),
 #endif
+       SHARED_CLK("nv.host1x", "tegra_host1x",         "host1x", &tegra_clk_host1x, NULL,  0, 0),
+       SHARED_CLK("vi.host1x", "tegra_vi",             "host1x", &tegra_clk_host1x, NULL,  0, 0),
+       SHARED_CLK("cap.host1x", "cap.host1x",          NULL,     &tegra_clk_host1x, NULL,  0, SHARED_CEILING),
+       SHARED_CLK("floor.host1x", "floor.host1x",      NULL,     &tegra_clk_host1x, NULL,  0, 0),
+       SHARED_CLK("override.host1x", "override.host1x", NULL,    &tegra_clk_host1x, NULL,  0, SHARED_OVERRIDE),
+       SHARED_CLK("floor.profile.host1x", "profile.host1x", NULL, &tegra_clk_host1x, NULL,  0, 0),
+
+       SHARED_CLK("sbc1.sclk", "spi_tegra.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc2.sclk", "spi_tegra.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc3.sclk", "spi_tegra.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc4.sclk", "spi_tegra.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc5.sclk", "spi_tegra.4", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("sbc6.sclk", "spi_tegra.5", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
 };
 
 
 /* XUSB clocks */
 #define XUSB_ID "tegra-xhci"
 
+static struct clk tegra_clk_xusb_gate = {
+       .name      = "xusb_gate",
+       .flags     = ENABLE_ON_INIT | PERIPH_NO_RESET,
+       .ops       = &tegra_xusb_gate_clk_ops,
+       .rate      = 12000000,
+       .max_rate  = 48000000,
+       .u.periph = {
+               .clk_num   = 143,
+       },
+};
+
 static struct clk tegra_xusb_source_clks[] = {
        PERIPH_CLK("xusb_host_src",     XUSB_ID, "host_src",    143,    0x600,  120000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
        PERIPH_CLK("xusb_falcon_src",   XUSB_ID, "falcon_src",  143,    0x604,  350000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
        PERIPH_CLK("xusb_fs_src",       XUSB_ID, "fs_src",      143,    0x608,   48000000, mux_clkm_48M_pllp_480M,      MUX | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
-       PERIPH_CLK("xusb_ss_src",       XUSB_ID, "ss_src",      143,    0x610,  120000000, mux_clkm_pllre_clk32_480M_pllc_ref,  MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
+       PERIPH_CLK("xusb_ss_src",       XUSB_ID, "ss_src",      143,    0x610,  122400000, mux_clkm_pllre_clk32_480M_pllc_ref,  MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
        PERIPH_CLK("xusb_dev_src",      XUSB_ID, "dev_src",     95,     0x60c,  120000000, mux_clkm_pllp_pllc_pllre,    MUX | MUX8 | DIV_U71 |  DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
-       {
-               .name      = "xusb_hs_src",
-               .lookup    = {
-                       .dev_id    = XUSB_ID,
-                       .con_id    = "hs_src",
-               },
-               .ops       = &tegra_periph_clk_ops,
-               .reg       = 0x610,
-               .inputs    = mux_pllu_60M,
-               .flags     = PLLU | PERIPH_NO_ENB,
-               .max_rate  = 60000000,
-               .u.periph = {
-                       .src_mask  = 0x1 << 25,
-                       .src_shift = 25,
-               },
+       SHARED_EMC_CLK("xusb.emc",      XUSB_ID, "emc", &tegra_clk_emc, NULL,   0,      SHARED_BW, 0),
+};
+
+static struct clk tegra_xusb_ss_div2 = {
+       .name      = "xusb_ss_div2",
+       .ops       = &tegra_clk_m_div_ops,
+       .parent    = &tegra_xusb_source_clks[3],
+       .mul       = 1,
+       .div       = 2,
+       .state     = OFF,
+       .max_rate  = 61200000,
+};
+
+static struct clk_mux_sel mux_ss_div2_pllu_60M[] = {
+       { .input = &tegra_xusb_ss_div2, .value = 0},
+       { .input = &tegra_pll_u_60M,    .value = 1},
+       { 0, 0},
+};
+
+static struct clk tegra_xusb_hs_src = {
+       .name      = "xusb_hs_src",
+       .lookup    = {
+               .dev_id    = XUSB_ID,
+               .con_id    = "hs_src",
+       },
+       .ops       = &tegra_periph_clk_ops,
+       .reg       = 0x610,
+       .inputs    = mux_ss_div2_pllu_60M,
+       .flags     = PLLU | PERIPH_NO_ENB,
+       .max_rate  = 61200000,
+       .u.periph = {
+               .src_mask  = 0x1 << 25,
+               .src_shift = 25,
        },
-       SHARED_CLK("xusb.emc",  "XUSB_ID",              "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
 };
 
 static struct clk_mux_sel mux_xusb_host[] = {
        { .input = &tegra_xusb_source_clks[0], .value = 0},
        { .input = &tegra_xusb_source_clks[1], .value = 1},
        { .input = &tegra_xusb_source_clks[2], .value = 2},
-       { .input = &tegra_xusb_source_clks[5], .value = 5},
+       { .input = &tegra_xusb_hs_src,         .value = 5},
        { 0, 0},
 };
 
@@ -6586,7 +7157,6 @@ static struct clk tegra_xusb_coupled_clks[] = {
        PERIPH_CLK_EX("xusb_dev",  XUSB_ID, "dev",  95, 0, 120000000, mux_xusb_dev,  0, &tegra_clk_coupled_gate_ops),
 };
 
-
 #define CLK_DUPLICATE(_name, _dev, _con)               \
        {                                               \
                .name   = _name,                        \
@@ -6640,6 +7210,8 @@ struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
        CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
        CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
+       CLK_DUPLICATE("cl_dvfs_soc", "tegra11-i2c.4", NULL),
+       CLK_DUPLICATE("cl_dvfs_ref", "tegra11-i2c.4", NULL),
        CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL),
        CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL),
        CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL),
@@ -6652,8 +7224,17 @@ struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("vde.cbus", "nvavp", "vde"),
        CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
        CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
-       CLK_DUPLICATE("host1x", "tegra_host1x", "host1x"),
        CLK_DUPLICATE("epp.cbus", "tegra_isp", "epp"),
+       CLK_DUPLICATE("i2s0", NULL, "i2s0"),
+       CLK_DUPLICATE("i2s1", NULL, "i2s1"),
+       CLK_DUPLICATE("i2s2", NULL, "i2s2"),
+       CLK_DUPLICATE("i2s3", NULL, "i2s3"),
+       CLK_DUPLICATE("i2s4", NULL, "i2s4"),
+       CLK_DUPLICATE("dam0", NULL, "dam0"),
+       CLK_DUPLICATE("dam1", NULL, "dam1"),
+       CLK_DUPLICATE("dam2", NULL, "dam2"),
+       CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
+       CLK_DUPLICATE("mclk", NULL, "default_mclk"),
 };
 
 struct clk *tegra_ptr_clks[] = {
@@ -6679,6 +7260,7 @@ struct clk *tegra_ptr_clks[] = {
        &tegra_pll_d_out0,
        &tegra_pll_d2,
        &tegra_pll_d2_out0,
+       &tegra_clk_xusb_gate,
        &tegra_pll_u,
        &tegra_pll_u_480M,
        &tegra_pll_u_60M,
@@ -6703,6 +7285,7 @@ struct clk *tegra_ptr_clks[] = {
        &tegra_clk_cop,
        &tegra_clk_sbus_cmplx,
        &tegra_clk_emc,
+       &tegra_clk_host1x,
 #ifdef CONFIG_TEGRA_DUAL_CBUS
        &tegra_clk_c2bus,
        &tegra_clk_c3bus,
@@ -6783,16 +7366,19 @@ static void tegra11_pllp_init_dependencies(unsigned long pllp_rate)
                tegra_pll_p_out1.u.pll_div.default_rate = 28800000;
                tegra_pll_p_out3.u.pll_div.default_rate = 72000000;
                tegra_clk_sbus_cmplx.u.system.threshold = 108000000;
+               tegra_clk_host1x.u.periph.threshold = 108000000;
                break;
        case 408000000:
                tegra_pll_p_out1.u.pll_div.default_rate = 9600000;
                tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
                tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
+               tegra_clk_host1x.u.periph.threshold = 204000000;
                break;
        case 204000000:
                tegra_pll_p_out1.u.pll_div.default_rate = 4800000;
                tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
                tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
+               tegra_clk_host1x.u.periph.threshold = 204000000;
                break;
        default:
                pr_err("tegra: PLLP rate: %lu is not supported\n", pllp_rate);
@@ -6819,6 +7405,49 @@ static void tegra11_init_one_clock(struct clk *c)
        clkdev_add(&c->lookup);
 }
 
+/* Direct access to CPU clock sources fot CPU idle driver */
+int tegra11_cpu_g_idle_rate_exchange(unsigned long *rate)
+{
+       int ret = 0;
+       struct clk *dfll = tegra_clk_cpu_cmplx.parent->u.cpu.dynamic;
+       unsigned long old_rate, new_rate, flags;
+
+       if (!dfll || !tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail))
+               return -EPERM;
+
+       /* Clipping min to oscillator rate is pretty much arbitrary */
+       new_rate = max(*rate, tegra_clk_m.rate);
+
+       clk_lock_save(dfll, &flags);
+
+       old_rate = clk_get_rate_locked(dfll);
+       *rate = old_rate;
+       if (new_rate != old_rate)
+               ret = clk_set_rate_locked(dfll, new_rate);
+
+       clk_unlock_restore(dfll, &flags);
+       return ret;
+}
+
+int tegra11_cpu_lp_idle_rate_exchange(unsigned long *rate)
+{
+       int ret = 0;
+       struct clk *backup = tegra_clk_cpu_cmplx.parent->u.cpu.backup;
+       unsigned long old_rate, flags;
+       unsigned long new_rate = min(
+               *rate, tegra_clk_cpu_cmplx.parent->u.cpu.backup_rate);
+
+       clk_lock_save(backup, &flags);
+
+       old_rate = clk_get_rate_locked(backup);
+       *rate = old_rate;
+       if (new_rate != old_rate)
+               ret = clk_set_rate_locked(backup, new_rate);
+
+       clk_unlock_restore(backup, &flags);
+       return ret;
+}
+
 void tegra_edp_throttle_cpu_now(u8 factor)
 {
        /* empty definition for tegra11 */
@@ -6841,9 +7470,11 @@ bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
         * source for EMC only when pll_m is fixed, or as a general fixed rate
         * clock source for EMC and other peripherals if pll_m is scaled. In
         * configuration with single cbus pll_c can be used as a scaled cbus
-        * clock source only.
+        * clock source only. No direct use for pll_c by super clocks.
         */
        if ((p == &tegra_pll_c) && (c != &tegra_pll_c_out1)) {
+               if (c->ops == &tegra_super_ops)
+                       return false;
 #ifdef CONFIG_TEGRA_DUAL_CBUS
 #ifndef CONFIG_TEGRA_PLLM_SCALED
                return c->flags & PERIPH_EMC_ENB;
@@ -6857,9 +7488,12 @@ bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
         * In any configuration pll_m must not be used as a clock source for
         * cbus modules. If pll_m is scaled it can be used as EMC source only.
         * Otherwise fixed rate pll_m can be used as clock source for EMC and
-        * other peripherals.
+        * other peripherals. No direct use for pll_m by super clocks.
         */
        if ((p == &tegra_pll_m) && (c != &tegra_pll_m_out1)) {
+               if (c->ops == &tegra_super_ops)
+                       return false;
+
                if (c->flags & PERIPH_ON_CBUS)
                        return false;
 #ifdef CONFIG_TEGRA_PLLM_SCALED
@@ -7032,8 +7666,8 @@ unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate)
 
        /* Vote on memory bus frequency based on cpu frequency;
           cpu rate is in kHz, emc rate is in Hz */
-       if (cpu_rate >= 1300000)
-               return emc_max_rate;    /* cpu >= 1.3GHz, emc max */
+       if (cpu_rate >= 1500000)
+               return emc_max_rate;    /* cpu >= 1.5GHz, emc max */
        else if (cpu_rate >= 975000)
                return 400000000;       /* cpu >= 975 MHz, emc 400 MHz */
        else if (cpu_rate >= 725000)
@@ -7167,7 +7801,6 @@ static void tegra11_clk_resume(void)
        clk_writel(*ctx++, CPU_SOFTRST_CTRL1);
        clk_writel(*ctx++, CPU_SOFTRST_CTRL2);
 
-       /* FIXME: DFLL? */
        /* Since we are going to reset devices and switch clock sources in this
         * function, plls and secondary dividers is required to be enabled. The
         * actual value will be restored back later. Note that boot plls: pllm,
@@ -7242,6 +7875,8 @@ static void tegra11_clk_resume(void)
                off <= PERIPH_CLK_SOURCE_SOC_THERM; off += 4)
                clk_writel(*ctx++, off);
 
+       udelay(RESET_PROPAGATION_DELAY);
+
        clk_writel(*ctx++, RST_DEVICES_L);
        clk_writel(*ctx++, RST_DEVICES_H);
        clk_writel(*ctx++, RST_DEVICES_U);
@@ -7255,7 +7890,6 @@ static void tegra11_clk_resume(void)
        clk_writel(*ctx++, CLK_OUT_ENB_U);
 
        /* For LP0 resume, clk to lpcpu is required to be on */
-       /* FIXME: should be saved as on? */
        val = *ctx++;
        val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN;
        clk_writel(val, CLK_OUT_ENB_V);
@@ -7308,21 +7942,24 @@ static void tegra11_clk_resume(void)
        p = tegra_clk_emc.parent;
        tegra11_periph_clk_init(&tegra_clk_emc);
 
+       /* Turn Off pll_m if it was OFF before suspend, and emc was not switched
+          to pll_m across suspend; re-init pll_m to sync s/w and h/w states */
+       if ((tegra_pll_m.state == OFF) &&
+           (&tegra_pll_m != tegra_clk_emc.parent))
+               tegra11_pllm_clk_disable(&tegra_pll_m);
+       tegra11_pllm_clk_init(&tegra_pll_m);
+
        if (p != tegra_clk_emc.parent) {
-               /* FIXME: old parent is left enabled here even if EMC was its
-                  only child before suspend (may happen on Tegra11 !!) */
                pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)",
                        p->name, p->refcnt, tegra_clk_emc.parent->name,
                        tegra_clk_emc.parent->refcnt);
 
-               BUG_ON(!p->refcnt);
-               p->refcnt--;
-
-               /* the new parent is enabled by low level code, but ref count
-                  need to be updated up to the root */
-               p = tegra_clk_emc.parent;
-               while (p && ((p->refcnt++) == 0))
-                       p = p->parent;
+               /* emc switched to the new parent by low level code, but ref
+                  count and s/w state need to be updated */
+               clk_disable(p);
+               clk_enable(tegra_clk_emc.parent);
+               tegra_dvfs_set_rate(&tegra_clk_emc,
+                                   clk_get_rate_all_locked(&tegra_clk_emc));
        }
        tegra_emc_timing_invalidate();
 
@@ -7334,13 +7971,79 @@ static void tegra11_clk_resume(void)
 static struct syscore_ops tegra_clk_syscore_ops = {
        .suspend = tegra11_clk_suspend,
        .resume = tegra11_clk_resume,
+       .save = tegra11_clk_suspend,
+       .restore = tegra11_clk_resume,
 };
 #endif
 
+/* Tegra11 CPU clock and reset control functions */
+static void tegra11_wait_cpu_in_reset(u32 cpu)
+{
+       unsigned int reg;
+
+       do {
+               reg = readl(reg_clk_base +
+                           TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+               cpu_relax();
+       } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
+
+       return;
+}
+
+static void tegra11_put_cpu_in_reset(u32 cpu)
+{
+       writel(CPU_RESET(cpu),
+              reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+       dmb();
+}
+
+static void tegra11_cpu_out_of_reset(u32 cpu)
+{
+       writel(CPU_RESET(cpu),
+              reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+       wmb();
+}
+
+static void tegra11_enable_cpu_clock(u32 cpu)
+{
+       unsigned int reg;
+
+       writel(CPU_CLOCK(cpu),
+              reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+       reg = readl(reg_clk_base +
+                   TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+}
 static void tegra11_disable_cpu_clock(u32 cpu)
 {
 }
 
+static struct tegra_cpu_car_ops tegra11_cpu_car_ops = {
+       .wait_for_reset = tegra11_wait_cpu_in_reset,
+       .put_in_reset   = tegra11_put_cpu_in_reset,
+       .out_of_reset   = tegra11_cpu_out_of_reset,
+       .enable_clock   = tegra11_enable_cpu_clock,
+       .disable_clock  = tegra11_disable_cpu_clock,
+};
+
+static void __init tegra11_cpu_car_ops_init(void)
+{
+       tegra_cpu_car_ops = &tegra11_cpu_car_ops;
+}
+
+static void tegra11_init_xusb_clocks(void)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
+               tegra11_init_one_clock(&tegra_xusb_source_clks[i]);
+
+       tegra11_init_one_clock(&tegra_xusb_ss_div2);
+       tegra11_init_one_clock(&tegra_xusb_hs_src);
+
+       for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
+               tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]);
+}
+
 void __init tegra11x_init_clocks(void)
 {
        int i;
@@ -7352,17 +8055,7 @@ void __init tegra11x_init_clocks(void)
        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
                tegra11_init_one_clock(&tegra_list_clks[i]);
 
-       for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
-               c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
-               if (!c) {
-                       pr_err("%s: Unknown duplicate clock %s\n", __func__,
-                               tegra_clk_duplicates[i].name);
-                       continue;
-               }
-
-               tegra_clk_duplicates[i].lookup.clk = c;
-               clkdev_add(&tegra_clk_duplicates[i].lookup);
-       }
+       tegra11_init_one_clock(&tegra_camera_mclk);
 
        for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
                tegra11_init_one_clock(&tegra_sync_source_list[i]);
@@ -7375,21 +8068,34 @@ void __init tegra11x_init_clocks(void)
        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
                tegra11_init_one_clock(&tegra_clk_out_list[i]);
 
-       for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
-               tegra11_init_one_clock(&tegra_xusb_source_clks[i]);
+       tegra11_init_xusb_clocks();
 
-       for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
-               tegra11_init_one_clock(&tegra_xusb_coupled_clks[i]);
+       for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+               c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+               if (!c) {
+                       pr_err("%s: Unknown duplicate clock %s\n", __func__,
+                               tegra_clk_duplicates[i].name);
+                       continue;
+               }
+
+               tegra_clk_duplicates[i].lookup.clk = c;
+               clkdev_add(&tegra_clk_duplicates[i].lookup);
+       }
 
        /* Initialize to default */
        tegra_init_cpu_edp_limits(0);
 
-#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
-       /* To be ready for DFLL late init */
-       tegra_dfll_cpu.ops->init = tegra11_dfll_cpu_late_init;
-#endif
+       tegra11_cpu_car_ops_init();
 
 #ifdef CONFIG_PM_SLEEP
        register_syscore_ops(&tegra_clk_syscore_ops);
 #endif
+
+}
+
+static int __init tegra11x_clk_late_init(void)
+{
+       clk_disable(&tegra_pll_re_vco);
+       return 0;
 }
+late_initcall(tegra11x_clk_late_init);