ARM: tegra11: Update cache flush/invalidate for power gating
[linux-3.10.git] / arch / arm / mach-tegra / sleep-t20.S
index 23474e2..556df6e 100644 (file)
@@ -187,10 +187,25 @@ ENTRY(tegra2_finish_sleep_cpu_secondary)
 
        dsb
 #ifdef MULTI_CACHE
+#ifdef CONFIG_HAVE_ARM_SCU
        mov32   r10, cpu_cache
        mov     lr, pc
        ldr     pc, [r10, #CACHE_FLUSH_KERN_ALL]
 #else
+       cpu_id  r2
+       cpu_to_csr_reg  r1,     r2
+       mov32   r10, TEGRA_FLOW_CTRL_VIRT
+       ldr     r10, [r10, r1]
+       tst     r10, #FLOW_CTRL_CSR_ENABLE_EXT_MASK
+       beq     flush_l1
+       mov32   r10, cpu_cache
+       mov     lr, pc
+       ldr     pc, [r10, #CACHE_FLUSH_KERN_ALL]
+       b       no_l2_sync
+flush_l1:
+       bl      tegra_flush_l1_cache
+#endif
+#else
        bl      __cpuc_flush_kern_all
 #endif
 
@@ -231,10 +246,25 @@ ENTRY(tegra2_finish_sleep_cpu_secondary)
 
        @ the cpu was running with coherency disabled, caches may be out of date
 #ifdef MULTI_CACHE
+#ifdef CONFIG_HAVE_ARM_SCU
        mov32   r10, cpu_cache
        mov     lr, pc
        ldr     pc, [r10, #CACHE_FLUSH_KERN_ALL]
 #else
+       cpu_id  r2
+       cpu_to_csr_reg  r1,     r2
+       mov32   r10, TEGRA_FLOW_CTRL_VIRT
+       ldr     r10, [r10, r1]
+       tst     r10, #FLOW_CTRL_CSR_ENABLE_EXT_MASK
+       beq     flush_l1
+       mov32   r10, cpu_cache
+       mov     lr, pc
+       ldr     pc, [r10, #CACHE_FLUSH_KERN_ALL]
+       b       no_l2_sync
+flush_l1:
+       bl      tegra_flush_l1_cache
+#endif
+#else
        bl      __cpuc_flush_kern_all
 #endif