ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / pm.h
index 7f605f9..6b86d50 100644 (file)
 
 #include "iomap.h"
 
+#include "pmc.h"
+
 #define PMC_SCRATCH0           0x50
 #define PMC_SCRATCH1           0x54
 #define PMC_SCRATCH4           0x60
 
-enum tegra_suspend_mode {
-       TEGRA_SUSPEND_NONE = 0,
-       TEGRA_SUSPEND_LP2,      /* CPU voltage off */
-       TEGRA_SUSPEND_LP1,      /* CPU voltage off, DRAM self-refresh */
-       TEGRA_SUSPEND_LP0,      /* CPU + core voltage off, DRAM self-refresh */
-       TEGRA_MAX_SUSPEND_MODE,
-};
-
 enum suspend_stage {
        TEGRA_SUSPEND_BEFORE_PERIPHERAL,
        TEGRA_SUSPEND_BEFORE_CPU,
@@ -86,10 +80,14 @@ struct tegra_suspend_platform_data {
        unsigned long min_residency_ncpu_slow;
        unsigned long min_residency_ncpu_fast;
        unsigned long min_residency_crail;
+       bool crail_up_early;
 #endif
-       unsigned long min_residency_mc_clk;
+       unsigned long min_residency_mclk_stop;
        bool usb_vbus_internal_wake; /* support for internal vbus wake */
        bool usb_id_internal_wake; /* support for internal id wake */
+
+       void (*suspend_dfll_bypass)(void);
+       void (*resume_dfll_bypass)(void);
 };
 
 /* clears io dpd settings before kernel code */
@@ -103,17 +101,30 @@ unsigned long tegra_mc_clk_stop_min_residency(void);
 unsigned long tegra_min_residency_vmin_fmin(void);
 unsigned long tegra_min_residency_ncpu(void);
 unsigned long tegra_min_residency_crail(void);
+bool tegra_crail_can_start_early(void);
+#else
+static inline bool tegra_crail_can_start_early(void)
+{ return false; }
 #endif
+void tegra_limit_cpu_power_timers(unsigned long us_on, unsigned long us_off);
 void tegra_clear_cpu_in_pd(int cpu);
 bool tegra_set_cpu_in_pd(int cpu);
 
 void tegra_mc_clk_prepare(void);
 void tegra_mc_clk_finish(void);
 int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags);
+#ifdef CONFIG_TEGRA_LP0_IN_IDLE
+int tegra_enter_lp0(unsigned long sleep_time);
+#else
+static inline int tegra_enter_lp0(unsigned long sleep_time)
+{ return 0; }
+#endif
 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
 int tegra_is_lp1_suspend_mode(void);
 #endif
 void tegra_lp1bb_suspend_emc_rate(unsigned long emc_min, unsigned long emc_max);
+void tegra_lp1bb_suspend_mv_set(int mv);
+unsigned long tegra_lp1bb_emc_min_rate_get(void);
 
 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
 #define FLOW_CTRL_CLUSTER_CONTROL \
@@ -130,6 +141,8 @@ void tegra_lp1bb_suspend_emc_rate(unsigned long emc_min, unsigned long emc_max);
 #define FLOW_CTRL_RAM_REPAIR \
        (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x40)
 #define FLOW_CTRL_RAM_REPAIR_BYPASS_EN (1<<2)
+#define FLOW_CTRL_RAM_REPAIR_STS       (1<<1)
+#define FLOW_CTRL_RAM_REPAIR_REQ       (1<<0)
 
 #define FUSE_SKU_DIRECT_CONFIG \
        (IO_ADDRESS(TEGRA_FUSE_BASE) + 0x1F4)
@@ -158,10 +171,22 @@ static inline void tegra_lp0_cpu_mode(bool enter) {}
 #endif
 
 #ifdef CONFIG_TEGRA_CLUSTER_CONTROL
-#define INSTRUMENT_CLUSTER_SWITCH 0    /* Should be zero for shipping code */
+#define INSTRUMENT_CLUSTER_SWITCH 1    /* Should be zero for shipping code */
 #define DEBUG_CLUSTER_SWITCH 0         /* Should be zero for shipping code */
 #define PARAMETERIZE_CLUSTER_SWITCH 1  /* Should be zero for shipping code */
 
+#define CLUSTER_SWITCH_TIME_AVG_SHIFT  4
+#define CLUSTER_SWITCH_AVG_SAMPLES     (0x1U << CLUSTER_SWITCH_TIME_AVG_SHIFT)
+
+enum tegra_cluster_switch_time_id {
+       tegra_cluster_switch_time_id_start = 0,
+       tegra_cluster_switch_time_id_prolog,
+       tegra_cluster_switch_time_id_switch,
+       tegra_cluster_switch_time_id_epilog,
+       tegra_cluster_switch_time_id_end,
+       tegra_cluster_switch_time_id_max
+};
+
 static inline bool is_g_cluster_present(void)
 {
        u32 fuse_sku = readl(FUSE_SKU_DIRECT_CONFIG);
@@ -218,6 +243,12 @@ static inline int tegra_cluster_switch(struct clk *cpu_clk,
 }
 #endif
 
+#if INSTRUMENT_CLUSTER_SWITCH
+void tegra_cluster_switch_time(unsigned int flags, int id);
+#else
+static inline void tegra_cluster_switch_time(unsigned int flags, int id) { }
+#endif
+
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 void tegra2_lp0_suspend_init(void);
 void tegra2_lp2_set_trigger(unsigned long cycles);