arm: tegra: Set Core to 0.95V in LP1

[linux-3.10.git] / arch / arm / mach-tegra / pm.c

diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 9f82908f433b48deee58e25b390f0e860a955ada..78572d12a5c1ec1cb1ee720a8ee8f786cbdfb7a2 100644 (file)
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -3,7 +3,7 @@
  *
  * CPU complex suspend & resume functions for Tegra SoCs
  *
- * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2009-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -103,9 +103,6 @@ struct suspend_context {
 };
 
 #ifdef CONFIG_PM_SLEEP
-#ifdef CONFIG_TRUSTED_FOUNDATIONS
-void *tegra_cpu_context;       /* non-cacheable page for CPU context */
-#endif
 phys_addr_t tegra_pgd_phys;    /* pgd used by hotplug & LP2 bootup */
 static pgd_t *tegra_pgd;
 static DEFINE_SPINLOCK(tegra_lp2_lock);
@@ -510,27 +507,17 @@ bool tegra_set_cpu_in_lp2(int cpu)
        return last_cpu;
 }
 
-bool tegra_is_cpu_in_lp2(int cpu)
-{
-       bool in_lp2;
-
-       spin_lock(&tegra_lp2_lock);
-       in_lp2 = cpumask_test_cpu(cpu, &tegra_in_lp2);
-       spin_unlock(&tegra_lp2_lock);
-       return in_lp2;
-}
-
 static void tegra_sleep_core(enum tegra_suspend_mode mode,
                             unsigned long v2p)
 {
 #ifdef CONFIG_TRUSTED_FOUNDATIONS
        if (mode == TEGRA_SUSPEND_LP0) {
-               tegra_generic_smc_uncached(0xFFFFFFFC, 0xFFFFFFE3,
-                                          virt_to_phys(tegra_resume));
+               tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE3,
+                                 virt_to_phys(tegra_resume));
        } else {
-               tegra_generic_smc_uncached(0xFFFFFFFC, 0xFFFFFFE6,
-                                          (TEGRA_RESET_HANDLER_BASE +
-                                           tegra_cpu_reset_handler_offset));
+               tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE6,
+                                 (TEGRA_RESET_HANDLER_BASE +
+                                  tegra_cpu_reset_handler_offset));
        }
 #endif
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
@@ -543,9 +530,9 @@ static void tegra_sleep_core(enum tegra_suspend_mode mode,
 static inline void tegra_sleep_cpu(unsigned long v2p)
 {
 #ifdef CONFIG_TRUSTED_FOUNDATIONS
-       tegra_generic_smc_uncached(0xFFFFFFFC, 0xFFFFFFE4,
-                                  (TEGRA_RESET_HANDLER_BASE +
-                                   tegra_cpu_reset_handler_offset));
+       tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE4,
+                         (TEGRA_RESET_HANDLER_BASE +
+                          tegra_cpu_reset_handler_offset));
 #endif
        cpu_suspend(v2p, tegra_sleep_cpu_finish);
 }
@@ -663,41 +650,6 @@ unsigned int tegra_idle_lp2_last(unsigned int sleep_time, unsigned int flags)
        return remain;
 }
 
-/*
- * alloc_suspend_context
- *
- * Allocate a non-cacheable page to hold the CPU contexts.
- */
-static int alloc_suspend_context(void)
-{
-#if CONFIG_TRUSTED_FOUNDATIONS
-       pgprot_t prot = __pgprot_modify(pgprot_kernel, L_PTE_MT_MASK,
-               L_PTE_MT_BUFFERABLE | L_PTE_XN);
-       struct page *ctx_page;
-
-       ctx_page = alloc_pages(GFP_KERNEL, 0);
-       if (IS_ERR_OR_NULL(ctx_page))
-               goto fail;
-
-       tegra_cpu_context = vm_map_ram(&ctx_page, 1, -1, prot);
-       if (IS_ERR_OR_NULL(tegra_cpu_context))
-               goto fail;
-
-       return 0;
-
-fail:
-       if (ctx_page)
-               __free_page(ctx_page);
-       if (tegra_cpu_context)
-               vm_unmap_ram((void*)tegra_cpu_context, 1);
-       tegra_cpu_context = NULL;
-
-       return -ENOMEM;
-#else
-       return 0;
-#endif
-}
-
 static int tegra_common_suspend(void)
 {
        void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
@@ -1139,13 +1091,6 @@ void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat)
                goto fail;
        }
 
-       if (alloc_suspend_context() < 0) {
-               pr_err("%s: CPU context alloc failed -- LP0/LP1/LP2 unavailable\n",
-                       __func__);
-               plat->suspend_mode = TEGRA_SUSPEND_NONE;
-               goto fail;
-       }
-
        if ((tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) &&
            (tegra_revision == TEGRA_REVISION_A01) &&
            (plat->suspend_mode == TEGRA_SUSPEND_LP0)) {
@@ -1202,6 +1147,21 @@ out:
                plat->suspend_mode = TEGRA_SUSPEND_LP2;
        }
 
+#ifdef CONFIG_TEGRA_LP1_950
+       if (pdata->lp1_lowvolt_support) {
+               u32 lp1_core_lowvolt, lp1_core_highvolt;
+               memcpy(tegra_lp1_register_pmuslave_addr(), &pdata->pmuslave_addr, 4);
+               memcpy(tegra_lp1_register_i2c_base_addr(), &pdata->i2c_base_addr, 4);
+
+               lp1_core_lowvolt = 0;
+               lp1_core_lowvolt = (pdata->lp1_core_volt_low << 8) | pdata->core_reg_addr;
+               memcpy(tegra_lp1_register_core_lowvolt(), &lp1_core_lowvolt, 4);
+
+               lp1_core_highvolt = 0;
+               lp1_core_highvolt = (pdata->lp1_core_volt_high << 8) | pdata->core_reg_addr;
+               memcpy(tegra_lp1_register_core_highvolt(), &lp1_core_highvolt, 4);
+       }
+#endif
        /* !!!FIXME!!! THIS IS TEGRA2 ONLY */
        /* Initialize scratch registers used for CPU LP2 synchronization */
        writel(0, pmc + PMC_SCRATCH37);