#endif
}
+static inline u32 __mc_raw_readl(int mc_ind, u32 reg)
+{
+ if (!mc_ind)
+ return __raw_readl(mc + reg);
+#ifdef MC_DUAL_CHANNEL
+ else
+ return __raw_readl(mc1 + reg);
+#endif
+ return 0;
+}
+
+static inline void __mc_raw_writel(int mc_ind, u32 val, u32 reg)
+{
+ if (!mc_ind)
+ __raw_writel(val, mc + reg);
+#ifdef MC_DUAL_CHANNEL
+ else
+ __raw_writel(val, mc1 + reg);
+#endif
+}
+
#define mc_readl(reg) __mc_readl(0, reg)
#define mc_writel(val, reg) __mc_writel(0, val, reg)
int tegra_mc_get_tiled_memory_bandwidth_multiplier(void);
/*
- * On Tegra11 dual channel MC effectively operates as 64-bit bus
+ * Tegra11 has dual 32-bit memory channels, while
+ * Tegra12 has single 64-bit memory channel.
+ * MC effectively operates as 64-bit bus.
*/
static inline int tegra_mc_get_effective_bytes_width(void)
{
-#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_12x_SOC) || \
+ defined(CONFIG_ARCH_TEGRA_11x_SOC)
return 8;
#else
return 4;