#include <linux/clk/tegra.h>
#include <linux/highmem.h>
#include <linux/memblock.h>
+#include <linux/bitops.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/system_info.h>
#include "pmc.h"
#include "apbio.h"
#include "sleep.h"
+#include "reset.h"
#define MC_SECURITY_CFG2 0x7c
+#define AHB_ARBITRATION_PRIORITY_CTRL 0x4
+#define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29)
+#define PRIORITY_SELECT_USB BIT(6)
+#define PRIORITY_SELECT_USB2 BIT(18)
+#define PRIORITY_SELECT_USB3 BIT(17)
+
+#define AHB_GIZMO_AHB_MEM 0xc
+#define ENB_FAST_REARBITRATE BIT(2)
+#define DONT_SPLIT_AHB_WR BIT(7)
+
+#define AHB_GIZMO_USB 0x1c
+#define AHB_GIZMO_USB2 0x78
+#define AHB_GIZMO_USB3 0x7c
+#define IMMEDIATE BIT(18)
+
+#define AHB_MEM_PREFETCH_CFG3 0xe0
+#define AHB_MEM_PREFETCH_CFG4 0xe4
+#define AHB_MEM_PREFETCH_CFG1 0xec
+#define AHB_MEM_PREFETCH_CFG2 0xf0
+#define PREFETCH_ENB BIT(31)
+#define MST_ID(x) (((x) & 0x1f) << 26)
+#define AHBDMA_MST_ID MST_ID(5)
+#define USB_MST_ID MST_ID(6)
+#define USB2_MST_ID MST_ID(18)
+#define USB3_MST_ID MST_ID(17)
+#define ADDR_BNDRY(x) (((x) & 0xf) << 21)
+#define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
+
unsigned long tegra_bootloader_fb_start;
unsigned long tegra_bootloader_fb_size;
unsigned long tegra_fb_start;
unsigned long tegra_lp0_vec_size;
unsigned long tegra_grhost_aperture = ~0ul;
static bool is_tegra_debug_uart_hsport;
+static struct board_info pmu_board_info;
static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
static int board_panel_type;
tag_latency = 0x331;
data_latency = 0x441;
#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
- tag_latency = 0x770;
- data_latency = 0x770;
-#else
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
if (is_lp_cluster()) {
tag_latency = 0x221;
data_latency = 0x221;
tag_latency = 0x331;
data_latency = 0x441;
}
+#else
+ tag_latency = 0x770;
+ data_latency = 0x770;
#endif
#endif
writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
#endif
/* Enable PL310 double line fill feature. */
- writel(((1<<30) | 7), p + L2X0_PREFETCH_CTRL);
+ writel(((1<<30) | 0), p + L2X0_PREFETCH_CTRL);
#endif
cache_type = readl(p + L2X0_CACHE_TYPE);
static void __init tegra_init_power(void)
{
- tegra_powergate_power_off(TEGRA_POWERGATE_MPE);
- tegra_powergate_power_off(TEGRA_POWERGATE_3D);
+ tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_MPE);
+ tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_3D);
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+ tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_3D1);
+#endif
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
+ /* for TEGRA_3x_SOC it will be handled seperately */
+ tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
#endif
}
+static inline unsigned long gizmo_readl(unsigned long offset)
+{
+ return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
+}
+
+static inline void gizmo_writel(unsigned long value, unsigned long offset)
+{
+ writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
+}
+
+static void __init tegra_init_ahb_gizmo_settings(void)
+{
+ unsigned long val;
+
+ val = gizmo_readl(AHB_GIZMO_AHB_MEM);
+ val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
+ gizmo_writel(val, AHB_GIZMO_AHB_MEM);
+
+ val = gizmo_readl(AHB_GIZMO_USB);
+ val |= IMMEDIATE;
+ gizmo_writel(val, AHB_GIZMO_USB);
+
+ val = gizmo_readl(AHB_GIZMO_USB2);
+ val |= IMMEDIATE;
+ gizmo_writel(val, AHB_GIZMO_USB2);
+
+ val = gizmo_readl(AHB_GIZMO_USB3);
+ val |= IMMEDIATE;
+ gizmo_writel(val, AHB_GIZMO_USB3);
+
+ val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
+ val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
+ | AHB_PRIORITY_WEIGHT(7);
+ gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
+
+ val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
+ val &= ~MST_ID(~0);
+ val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
+ gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
+
+ val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
+ val &= ~MST_ID(~0);
+ val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
+ gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
+
+ val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
+ val &= ~MST_ID(~0);
+ val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
+ gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
+
+ val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
+ val &= ~MST_ID(~0);
+ val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
+ gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
+}
+
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
void __init tegra20_init_early(void)
{
+#ifndef CONFIG_SMP
+ /* For SMP system, initializing the reset handler here is too
+ late. For non-SMP systems, the function that calls the reset
+ handler initializer is not called, so do it here for non-SMP. */
+ tegra_cpu_reset_handler_init();
+#endif
tegra_apb_io_init();
tegra_init_fuse();
tegra_init_cache();
tegra_powergate_init();
tegra20_hotplug_init();
tegra_init_power();
- tegra20_mc_init(); /* !!!FIXME!!! Change Tegra3 behavior to match Tegra2 */
+ tegra_init_ahb_gizmo_settings();
}
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
void __init tegra30_init_early(void)
{
+#ifndef CONFIG_SMP
+ /* For SMP system, initializing the reset handler here is too
+ late. For non-SMP systems, the function that calls the reset
+ handler initializer is not called, so do it here for non-SMP. */
+ tegra_cpu_reset_handler_init();
+#endif
tegra_apb_io_init();
tegra_init_fuse();
tegra_init_cache();
tegra_powergate_init();
tegra30_hotplug_init();
tegra_init_power();
- tegra30_mc_init();
+ tegra_init_ahb_gizmo_settings();
}
#endif
bi->minor_revision = (system_serial_low >> 8) & 0xFF;
}
+static int __init tegra_pmu_board_info(char *info)
+{
+ char *p = info;
+ pmu_board_info.board_id = memparse(p, &p);
+ pmu_board_info.sku = memparse(p+1, &p);
+ pmu_board_info.fab = memparse(p+1, &p);
+ pmu_board_info.major_revision = memparse(p+1, &p);
+ pmu_board_info.minor_revision = memparse(p+1, &p);
+ return 1;
+}
+
+void tegra_get_pmu_board_info(struct board_info *bi)
+{
+ memcpy(bi, &pmu_board_info, sizeof(struct board_info));
+}
+
+__setup("pmuboard=", tegra_pmu_board_info);
+
+
/*
* Tegra has a protected aperture that prevents access by most non-CPU
* memory masters to addresses above the aperture value. Enabling it