ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-loki-memory.c
index e3ea529..1c20b03 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
 #include "tegra12_emc.h"
 #include "devices.h"
 
-static struct tegra12_emc_table loki_a02_emc_table[] = {
+static struct tegra12_emc_table loki_b00_sku0_emc_table[] = {
        {
-               0x15,       /* V5.0.2 */
-               "01_12750_V01_V5.0.2_V0.3", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_12750_01_V5.0.6_V0.8", /* DVFS table version */
                12750,      /* SDRAM frequency */
-               780,        /* min voltage */
+               800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x4000003e, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000000, /* EMC_RC */
@@ -57,7 +57,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000004, /* EMC_EINPUT */
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
-                       0x00000002, /* EMC_PUTERM_WIDTH */
+                       0x00000001, /* EMC_PUTERM_WIDTH */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -88,7 +88,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
-                       0x10674098, /* EMC_FBIO_CFG5 */
+                       0x10604098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x00064000, /* EMC_DLL_XFORM_DQS0 */
@@ -145,14 +145,14 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ0 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ4 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ5 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ6 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ7 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -174,13 +174,10 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00000000, /* EMC_ZCAL_INTERVAL */
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
-                       0x00000002, /* EMC_CTT_DURATION */
+                       0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
                        0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */
                        0x00000009, /* EMC_QPOP */
@@ -240,24 +237,27 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0x00000802, /* EMC_CTT_TERM_CTRL */
                0x73240000, /* EMC_CFG */
-               0x00000885, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
+               0x000008c5, /* EMC_CFG_2 */
+               0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               57820,      /* expected dvfs latency (ns) */
        },
        {
-               0x15,       /* V5.0.2 */
-               "01_20400_V01_V5.0.2_V0.3", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_20400_01_V5.0.6_V0.8", /* DVFS table version */
                20400,      /* SDRAM frequency */
-               780,        /* min voltage */
+               800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000026, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000000, /* EMC_RC */
@@ -282,7 +282,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000004, /* EMC_EINPUT */
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
-                       0x00000002, /* EMC_PUTERM_WIDTH */
+                       0x00000001, /* EMC_PUTERM_WIDTH */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -313,7 +313,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
-                       0x10674098, /* EMC_FBIO_CFG5 */
+                       0x10604098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x00064000, /* EMC_DLL_XFORM_DQS0 */
@@ -370,14 +370,14 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ0 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ4 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ5 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ6 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ7 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -399,13 +399,10 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00000000, /* EMC_ZCAL_INTERVAL */
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
-                       0x00000002, /* EMC_CTT_DURATION */
+                       0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
                        0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
                        0x00000009, /* EMC_QPOP */
@@ -465,24 +462,27 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0x00000802, /* EMC_CTT_TERM_CTRL */
                0x73240000, /* EMC_CFG */
-               0x00000885, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
+               0x000008c5, /* EMC_CFG_2 */
+               0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               35610,      /* expected dvfs latency (ns) */
        },
        {
-               0x15,       /* V5.0.2 */
-               "01_40800_V01_V5.0.2_V0.3", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_40800_01_V5.0.6_V0.8", /* DVFS table version */
                40800,      /* SDRAM frequency */
-               780,        /* min voltage */
+               800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000012, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000001, /* EMC_RC */
@@ -507,7 +507,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000004, /* EMC_EINPUT */
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
-                       0x00000002, /* EMC_PUTERM_WIDTH */
+                       0x00000001, /* EMC_PUTERM_WIDTH */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -538,7 +538,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
-                       0x10674098, /* EMC_FBIO_CFG5 */
+                       0x10604098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x00064000, /* EMC_DLL_XFORM_DQS0 */
@@ -595,14 +595,14 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ0 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ4 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ5 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ6 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ7 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -624,13 +624,10 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00000000, /* EMC_ZCAL_INTERVAL */
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
-                       0x00000002, /* EMC_CTT_DURATION */
+                       0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
                        0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
                        0x00000009, /* EMC_QPOP */
@@ -690,24 +687,27 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0x00000802, /* EMC_CTT_TERM_CTRL */
                0x73240000, /* EMC_CFG */
-               0x00000885, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
+               0x000008c5, /* EMC_CFG_2 */
+               0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               20850,      /* expected dvfs latency (ns) */
        },
        {
-               0x15,       /* V5.0.2 */
-               "01_68000_V01_V5.0.2_V0.3", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_68000_01_V5.0.6_V0.8", /* DVFS table version */
                68000,      /* SDRAM frequency */
-               780,        /* min voltage */
+               800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x4000000a, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000003, /* EMC_RC */
@@ -732,7 +732,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000004, /* EMC_EINPUT */
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
-                       0x00000002, /* EMC_PUTERM_WIDTH */
+                       0x00000001, /* EMC_PUTERM_WIDTH */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -755,7 +755,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000004, /* EMC_TCKE */
                        0x00000005, /* EMC_TCKESR */
                        0x00000004, /* EMC_TPD */
-                       0x00000001, /* EMC_TFAW */
+                       0x00000000, /* EMC_TFAW */
                        0x00000000, /* EMC_TRPAB */
                        0x00000005, /* EMC_TCLKSTABLE */
                        0x00000005, /* EMC_TCLKSTOP */
@@ -763,7 +763,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000002, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
-                       0x10674098, /* EMC_FBIO_CFG5 */
+                       0x10604098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x00064000, /* EMC_DLL_XFORM_DQS0 */
@@ -820,14 +820,14 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ0 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ4 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ5 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ6 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ7 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -849,13 +849,10 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00000000, /* EMC_ZCAL_INTERVAL */
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
-                       0x00000002, /* EMC_CTT_DURATION */
+                       0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
                        0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
                        0x00000009, /* EMC_QPOP */
@@ -915,24 +912,27 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0x00000802, /* EMC_CTT_TERM_CTRL */
                0x73240000, /* EMC_CFG */
-               0x00000885, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
+               0x000008c5, /* EMC_CFG_2 */
+               0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               10720,      /* expected dvfs latency (ns) */
        },
        {
-               0x15,       /* V5.0.2 */
-               "01_102000_V01_V5.0.2_V0.3", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_102000_01_V5.0.6_V0.8", /* DVFS table version */
                102000,     /* SDRAM frequency */
-               780,        /* min voltage */
+               800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000006, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000004, /* EMC_RC */
@@ -951,13 +951,13 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_WEXT */
                        0x00000005, /* EMC_WDV */
                        0x00000005, /* EMC_WDV_MASK */
-                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_QUSE */
                        0x00000000, /* EMC_QUSE_WIDTH */
                        0x00000000, /* EMC_IBDLY */
                        0x00000004, /* EMC_EINPUT */
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
-                       0x00000002, /* EMC_PUTERM_WIDTH */
+                       0x00000001, /* EMC_PUTERM_WIDTH */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -980,15 +980,15 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000004, /* EMC_TCKE */
                        0x00000005, /* EMC_TCKESR */
                        0x00000004, /* EMC_TPD */
-                       0x00000003, /* EMC_TFAW */
+                       0x00000001, /* EMC_TFAW */
                        0x00000000, /* EMC_TRPAB */
                        0x00000005, /* EMC_TCLKSTABLE */
                        0x00000005, /* EMC_TCLKSTOP */
                        0x0000031c, /* EMC_TREFBW */
-                       0x00000000, /* EMC_FBIO_CFG6 */
+                       0x00000002, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
-                       0x10674098, /* EMC_FBIO_CFG5 */
+                       0x10604098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x00064000, /* EMC_DLL_XFORM_DQS0 */
@@ -1045,14 +1045,14 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ0 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ4 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ5 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ6 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ7 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -1074,13 +1074,10 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00000000, /* EMC_ZCAL_INTERVAL */
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
-                       0x00000002, /* EMC_CTT_DURATION */
+                       0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
                        0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
                        0x00000009, /* EMC_QPOP */
@@ -1140,24 +1137,27 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0x00000802, /* EMC_CTT_TERM_CTRL */
                0x73240000, /* EMC_CFG */
-               0x00000885, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
+               0x000008c5, /* EMC_CFG_2 */
+               0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               6890,       /* expected dvfs latency (ns) */
        },
        {
-               0x15,       /* V5.0.2 */
-               "01_204000_V01_V5.0.2_V0.3", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_204000_01_V5.0.6_V0.8", /* DVFS table version */
                204000,     /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000002, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000009, /* EMC_RC */
@@ -1182,7 +1182,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000003, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
-                       0x00000002, /* EMC_PUTERM_WIDTH */
+                       0x00000001, /* EMC_PUTERM_WIDTH */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -1205,7 +1205,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000004, /* EMC_TCKE */
                        0x00000005, /* EMC_TCKESR */
                        0x00000004, /* EMC_TPD */
-                       0x00000007, /* EMC_TFAW */
+                       0x00000004, /* EMC_TFAW */
                        0x00000000, /* EMC_TRPAB */
                        0x00000005, /* EMC_TCLKSTABLE */
                        0x00000005, /* EMC_TCLKSTOP */
@@ -1213,7 +1213,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000002, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
-                       0x10674098, /* EMC_FBIO_CFG5 */
+                       0x10604098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x00064000, /* EMC_DLL_XFORM_DQS0 */
@@ -1242,10 +1242,10 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE7 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00004000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR3 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR4 */
-                       0x00004000, /* EMC_DLL_XFORM_ADDR5 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE8 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE9 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE10 */
@@ -1270,14 +1270,14 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ0 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0007c000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ4 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ5 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ6 */
-                       0x00007c00, /* EMC_DLL_XFORM_DQ7 */
+                       0x00090000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00090000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00090000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00090000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00009000, /* EMC_DLL_XFORM_DQ4 */
+                       0x00009000, /* EMC_DLL_XFORM_DQ5 */
+                       0x00009000, /* EMC_DLL_XFORM_DQ6 */
+                       0x00009000, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -1285,7 +1285,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_XM2DQPADCTRL2 */
                        0x00000000, /* EMC_XM2DQPADCTRL3 */
                        0x77ffc081, /* EMC_XM2CLKPADCTRL */
-                       0x00001212, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000606, /* EMC_XM2CLKPADCTRL2 */
                        0x81f1f108, /* EMC_XM2COMPPADCTRL */
                        0x07070004, /* EMC_XM2VTTGENPADCTRL */
                        0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
@@ -1299,13 +1299,10 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
-                       0x00000002, /* EMC_CTT_DURATION */
+                       0x00000001, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
                        0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
                        0x00000009, /* EMC_QPOP */
@@ -1315,7 +1312,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000001, /* MC_EMEM_ARB_TIMING_RP */
                        0x00000004, /* MC_EMEM_ARB_TIMING_RC */
                        0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
                        0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
                        0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
                        0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
@@ -1365,37 +1362,40 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0x00000802, /* EMC_CTT_TERM_CTRL */
                0x73240000, /* EMC_CFG */
-               0x0000088d, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
+               0x000008cd, /* EMC_CFG_2 */
+               0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               3420,       /* expected dvfs latency (ns) */
        },
        {
-               0x15,       /* V5.0.2 */
-               "01_312000_V01_V5.0.2_V0.3", /* DVFS table version */
-               312000,     /* SDRAM frequency */
-               820,        /* min voltage */
+               0x18,       /* V5.0.6 */
+               "06_300000_01_V5.0.6_V0.8", /* DVFS table version */
+               300000,     /* SDRAM frequency */
+               810,        /* min voltage */
                800,        /* gpu min voltage */
-               "pllm_out0", /* clock source id */
-               0x00000002, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
+               "pllc_out0", /* clock source id */
+               0x20000002, /* CLK_SOURCE_EMC */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
-                       0x0000000d, /* EMC_RC */
-                       0x00000050, /* EMC_RFC */
+                       0x0000000c, /* EMC_RC */
+                       0x0000004c, /* EMC_RFC */
                        0x00000000, /* EMC_RFC_SLR */
-                       0x00000009, /* EMC_RAS */
-                       0x00000003, /* EMC_RP */
+                       0x00000008, /* EMC_RAS */
+                       0x00000002, /* EMC_RP */
                        0x00000004, /* EMC_R2W */
                        0x00000008, /* EMC_W2R */
                        0x00000002, /* EMC_R2P */
                        0x00000009, /* EMC_W2P */
-                       0x00000003, /* EMC_RD_RCD */
-                       0x00000003, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RD_RCD */
+                       0x00000002, /* EMC_WR_RCD */
                        0x00000002, /* EMC_RRD */
                        0x00000002, /* EMC_REXT */
                        0x00000000, /* EMC_WEXT */
@@ -1404,41 +1404,41 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000005, /* EMC_QUSE */
                        0x00000002, /* EMC_QUSE_WIDTH */
                        0x00000000, /* EMC_IBDLY */
-                       0x00000002, /* EMC_EINPUT */
+                       0x00000003, /* EMC_EINPUT */
                        0x00000006, /* EMC_EINPUT_DURATION */
                        0x00030000, /* EMC_PUTERM_EXTRA */
-                       0x00000004, /* EMC_PUTERM_WIDTH */
+                       0x00000003, /* EMC_PUTERM_WIDTH */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
                        0x00000000, /* EMC_CDB_CNTL_3 */
                        0x00000002, /* EMC_QRST */
-                       0x0000000e, /* EMC_QSAFE */
+                       0x0000000d, /* EMC_QSAFE */
                        0x0000000e, /* EMC_RDV */
                        0x00000010, /* EMC_RDV_MASK */
-                       0x00000942, /* EMC_REFRESH */
+                       0x000008e4, /* EMC_REFRESH */
                        0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x00000250, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000239, /* EMC_PRE_REFRESH_REQ_CNT */
                        0x00000001, /* EMC_PDEX2WR */
                        0x00000008, /* EMC_PDEX2RD */
                        0x00000001, /* EMC_PCHG2PDEN */
                        0x00000000, /* EMC_ACT2PDEN */
-                       0x0000004d, /* EMC_AR2PDEN */
+                       0x0000004a, /* EMC_AR2PDEN */
                        0x0000000e, /* EMC_RW2PDEN */
-                       0x00000055, /* EMC_TXSR */
+                       0x00000051, /* EMC_TXSR */
                        0x00000200, /* EMC_TXSRDLL */
                        0x00000004, /* EMC_TCKE */
                        0x00000005, /* EMC_TCKESR */
                        0x00000004, /* EMC_TPD */
-                       0x0000000a, /* EMC_TFAW */
+                       0x00000005, /* EMC_TFAW */
                        0x00000000, /* EMC_TRPAB */
                        0x00000005, /* EMC_TCLKSTABLE */
                        0x00000005, /* EMC_TCLKSTOP */
-                       0x00000982, /* EMC_TREFBW */
+                       0x00000924, /* EMC_TREFBW */
                        0x00000000, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
-                       0x1047b898, /* EMC_FBIO_CFG5 */
+                       0x1040b098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x00030000, /* EMC_DLL_XFORM_DQS0 */
@@ -1465,11 +1465,11 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x0009c000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x0009c000, /* EMC_DLL_XFORM_ADDR1 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR4 */
+                       0x0009c000, /* EMC_DLL_XFORM_ADDR3 */
+                       0x0009c000, /* EMC_DLL_XFORM_ADDR4 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE8 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -1495,14 +1495,14 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x00050000, /* EMC_DLL_XFORM_DQ0 */
-                       0x00050000, /* EMC_DLL_XFORM_DQ1 */
-                       0x00050000, /* EMC_DLL_XFORM_DQ2 */
-                       0x00050000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00005000, /* EMC_DLL_XFORM_DQ4 */
-                       0x00005000, /* EMC_DLL_XFORM_DQ5 */
-                       0x00005000, /* EMC_DLL_XFORM_DQ6 */
-                       0x00005000, /* EMC_DLL_XFORM_DQ7 */
+                       0x00060000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00060000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00060000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00006000, /* EMC_DLL_XFORM_DQ4 */
+                       0x00006000, /* EMC_DLL_XFORM_DQ5 */
+                       0x00006000, /* EMC_DLL_XFORM_DQ6 */
+                       0x00006000, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -1520,27 +1520,24 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00514514, /* EMC_XM2DQSPADCTRL5 */
                        0x51451400, /* EMC_XM2DQSPADCTRL6 */
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-                       0x0000009c, /* EMC_TXDSRVTTGEN */
+                       0x00000096, /* EMC_TXDSRVTTGEN */
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x0171000e, /* EMC_MRS_WAIT_CNT */
-                       0x0171000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x01740010, /* EMC_MRS_WAIT_CNT */
+                       0x01740010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
-                       0x00000004, /* EMC_CTT_DURATION */
+                       0x00000003, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
-                       0x8000138d, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x800012d7, /* EMC_DYN_SELF_REF_CONTROL */
                        0x00000009, /* EMC_QPOP */
-                       0x0b000004, /* MC_EMEM_ARB_CFG */
+                       0x08000004, /* MC_EMEM_ARB_CFG */
                        0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
                        0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000007, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
                        0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
                        0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
                        0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
@@ -1549,65 +1546,68 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
                        0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
                        0x06040202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
-                       0x76e50f08, /* MC_EMEM_ARB_MISC0 */
+                       0x000a0506, /* MC_EMEM_ARB_DA_COVERS */
+                       0x77450e07, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
                },
                {
-                       0x00000005, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x00000096, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00ff0047, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00ff0047, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+                       0x00000004, /* MC_MLL_MPCORER_PTSA_RATE */
+                       0x00000090, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00ff004a, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+                       0x00ff004a, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
                        0x00ff003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
                        0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
                        0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
                        0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
                        0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-                       0x00330049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+                       0x00350049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
                        0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
                        0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
                        0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x00080039, /* MC_LATENCY_ALLOWANCE_HC_0 */
+                       0x0008003b, /* MC_LATENCY_ALLOWANCE_HC_0 */
                        0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
                        0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00ff0041, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00ff002c, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+                       0x00ff0043, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+                       0x00ff002d, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
                        0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x00ff0046, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+                       0x00ff0049, /* MC_LATENCY_ALLOWANCE_VIC_0 */
                        0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
                        0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
                        0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
                        0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-                       0x00510034, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+                       0x00510036, /* MC_LATENCY_ALLOWANCE_VDE_1 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00ff0082, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x00ff0047, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+                       0x00ff0087, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+                       0x00ff004a, /* MC_LATENCY_ALLOWANCE_AFI_0 */
                },
                0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0x00000802, /* EMC_CTT_TERM_CTRL */
                0x73340000, /* EMC_CFG */
-               0x0000088d, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
+               0x000008cd, /* EMC_CFG_2 */
+               0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000321, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200000, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               2180,       /* expected dvfs latency (ns) */
        },
        {
-               0x15,       /* V5.0.2 */
-               "01_396000_V01_V5.0.2_V0.3", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_396000_01_V5.0.6_V0.8", /* DVFS table version */
                396000,     /* SDRAM frequency */
-               870,        /* min voltage */
-               800,        /* gpu min voltage */
-               "pllc_out0", /* clock source id */
-               0x20000002, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
+               860,        /* min voltage */
+               900,        /* gpu min voltage */
+               "pllm_out0", /* clock source id */
+               0x00000002, /* CLK_SOURCE_EMC */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000011, /* EMC_RC */
@@ -1624,23 +1624,23 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000002, /* EMC_RRD */
                        0x00000002, /* EMC_REXT */
                        0x00000000, /* EMC_WEXT */
-                       0x00000004, /* EMC_WDV */
-                       0x00000004, /* EMC_WDV_MASK */
-                       0x00000007, /* EMC_QUSE */
+                       0x00000003, /* EMC_WDV */
+                       0x00000003, /* EMC_WDV_MASK */
+                       0x00000005, /* EMC_QUSE */
                        0x00000002, /* EMC_QUSE_WIDTH */
                        0x00000000, /* EMC_IBDLY */
                        0x00000003, /* EMC_EINPUT */
                        0x00000006, /* EMC_EINPUT_DURATION */
-                       0x00050000, /* EMC_PUTERM_EXTRA */
-                       0x00000004, /* EMC_PUTERM_WIDTH */
+                       0x00030000, /* EMC_PUTERM_EXTRA */
+                       0x00000003, /* EMC_PUTERM_WIDTH */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
                        0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000004, /* EMC_QRST */
-                       0x0000000f, /* EMC_QSAFE */
-                       0x00000010, /* EMC_RDV */
-                       0x00000012, /* EMC_RDV_MASK */
+                       0x00000002, /* EMC_QRST */
+                       0x0000000d, /* EMC_QSAFE */
+                       0x0000000e, /* EMC_RDV */
+                       0x00000010, /* EMC_RDV_MASK */
                        0x00000bd1, /* EMC_REFRESH */
                        0x00000000, /* EMC_BURST_REFRESH_NUM */
                        0x000002f4, /* EMC_PRE_REFRESH_REQ_CNT */
@@ -1655,7 +1655,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000004, /* EMC_TCKE */
                        0x00000005, /* EMC_TCKESR */
                        0x00000004, /* EMC_TPD */
-                       0x0000000d, /* EMC_TFAW */
+                       0x00000007, /* EMC_TFAW */
                        0x00000000, /* EMC_TRPAB */
                        0x00000005, /* EMC_TCLKSTABLE */
                        0x00000005, /* EMC_TCLKSTOP */
@@ -1663,7 +1663,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
-                       0x1047b898, /* EMC_FBIO_CFG5 */
+                       0x1040b098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x00030000, /* EMC_DLL_XFORM_DQS0 */
@@ -1690,11 +1690,11 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00074000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00074000, /* EMC_DLL_XFORM_ADDR1 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00068000, /* EMC_DLL_XFORM_ADDR4 */
+                       0x00074000, /* EMC_DLL_XFORM_ADDR3 */
+                       0x00074000, /* EMC_DLL_XFORM_ADDR4 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE8 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -1720,21 +1720,21 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x00038000, /* EMC_DLL_XFORM_DQ0 */
-                       0x00038000, /* EMC_DLL_XFORM_DQ1 */
-                       0x00038000, /* EMC_DLL_XFORM_DQ2 */
-                       0x00038000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00003800, /* EMC_DLL_XFORM_DQ4 */
-                       0x00003800, /* EMC_DLL_XFORM_DQ5 */
-                       0x00003800, /* EMC_DLL_XFORM_DQ6 */
-                       0x00003800, /* EMC_DLL_XFORM_DQ7 */
-                       0x100002a0, /* EMC_XM2CMDPADCTRL */
+                       0x00044000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00044000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00044000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00044000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00004400, /* EMC_DLL_XFORM_DQ4 */
+                       0x00004400, /* EMC_DLL_XFORM_DQ5 */
+                       0x00004400, /* EMC_DLL_XFORM_DQ6 */
+                       0x00004400, /* EMC_DLL_XFORM_DQ7 */
+                       0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
-                       0x0123133d, /* EMC_XM2DQSPADCTRL2 */
+                       0x01231339, /* EMC_XM2DQSPADCTRL2 */
                        0x00000000, /* EMC_XM2DQPADCTRL2 */
                        0x00000000, /* EMC_XM2DQPADCTRL3 */
-                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x77ffc081, /* EMC_XM2CLKPADCTRL */
                        0x00000606, /* EMC_XM2CLKPADCTRL2 */
                        0x81f1f108, /* EMC_XM2COMPPADCTRL */
                        0x07070004, /* EMC_XM2VTTGENPADCTRL */
@@ -1749,23 +1749,20 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x015b000e, /* EMC_MRS_WAIT_CNT */
-                       0x015b000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x015b0010, /* EMC_MRS_WAIT_CNT */
+                       0x015b0010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
-                       0x00000004, /* EMC_CTT_DURATION */
-                       0x0000d2b3, /* EMC_CFG_PIPE */
+                       0x00000003, /* EMC_CTT_DURATION */
+                       0x0000d3b3, /* EMC_CFG_PIPE */
                        0x8000188b, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x0000000b, /* EMC_QPOP */
+                       0x00000009, /* EMC_QPOP */
                        0x0f000005, /* MC_EMEM_ARB_CFG */
                        0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
                        0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
                        0x00000002, /* MC_EMEM_ARB_TIMING_RP */
                        0x00000009, /* MC_EMEM_ARB_TIMING_RC */
                        0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
                        0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
                        0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
                        0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
@@ -1816,36 +1813,39 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                0x00000802, /* EMC_CTT_TERM_CTRL */
                0x73340000, /* EMC_CFG */
                0x0000088d, /* EMC_CFG_2 */
-               0x0004012c, /* EMC_SEL_DPD_CTRL */
+               0x00040008, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000521, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200000, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1750,       /* expected dvfs latency (ns) */
        },
        {
-               0x15,       /* V5.0.2 */
-               "01_528000_V01_V5.0.2_V0.3", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_528000_01_V5.0.6_V0.8", /* DVFS table version */
                528000,     /* SDRAM frequency */
-               900,        /* min voltage */
+               920,        /* min voltage */
                900,        /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
-                       0x00000018, /* EMC_RC */
+                       0x00000017, /* EMC_RC */
                        0x00000088, /* EMC_RFC */
                        0x00000000, /* EMC_RFC_SLR */
                        0x00000010, /* EMC_RAS */
-                       0x00000006, /* EMC_RP */
+                       0x00000005, /* EMC_RP */
                        0x00000006, /* EMC_R2W */
                        0x00000009, /* EMC_W2R */
                        0x00000002, /* EMC_R2P */
                        0x0000000d, /* EMC_W2P */
-                       0x00000006, /* EMC_RD_RCD */
-                       0x00000006, /* EMC_WR_RCD */
+                       0x00000005, /* EMC_RD_RCD */
+                       0x00000005, /* EMC_WR_RCD */
                        0x00000002, /* EMC_RRD */
                        0x00000002, /* EMC_REXT */
                        0x00000000, /* EMC_WEXT */
@@ -1854,10 +1854,10 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000008, /* EMC_QUSE */
                        0x00000002, /* EMC_QUSE_WIDTH */
                        0x00000000, /* EMC_IBDLY */
-                       0x00000003, /* EMC_EINPUT */
+                       0x00000005, /* EMC_EINPUT */
                        0x00000007, /* EMC_EINPUT_DURATION */
                        0x00060000, /* EMC_PUTERM_EXTRA */
-                       0x00000004, /* EMC_PUTERM_WIDTH */
+                       0x00000003, /* EMC_PUTERM_WIDTH */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -1880,15 +1880,15 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000004, /* EMC_TCKE */
                        0x00000005, /* EMC_TCKESR */
                        0x00000004, /* EMC_TPD */
-                       0x00000013, /* EMC_TFAW */
+                       0x0000000b, /* EMC_TFAW */
                        0x00000000, /* EMC_TRPAB */
                        0x00000006, /* EMC_TCLKSTABLE */
                        0x00000006, /* EMC_TCLKSTOP */
                        0x00001017, /* EMC_TREFBW */
-                       0x00000002, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
-                       0x1047b898, /* EMC_FBIO_CFG5 */
+                       0x1040b098, /* EMC_FBIO_CFG5 */
                        0xe01200b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x0000000a, /* EMC_DLL_XFORM_DQS0 */
@@ -1915,11 +1915,11 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR0 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00058000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00058000, /* EMC_DLL_XFORM_ADDR1 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR3 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR4 */
+                       0x00058000, /* EMC_DLL_XFORM_ADDR3 */
+                       0x00058000, /* EMC_DLL_XFORM_ADDR4 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE8 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -1945,14 +1945,14 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ0 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ1 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ2 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000000b, /* EMC_DLL_XFORM_DQ7 */
+                       0x0000000e, /* EMC_DLL_XFORM_DQ0 */
+                       0x0000000e, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000e, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000e, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000000e, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000000e, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000000e, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000000e, /* EMC_DLL_XFORM_DQ7 */
                        0x100002a0, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -1960,7 +1960,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_XM2DQPADCTRL2 */
                        0x00000000, /* EMC_XM2DQPADCTRL3 */
                        0x77ffc085, /* EMC_XM2CLKPADCTRL */
-                       0x00000c0c, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000606, /* EMC_XM2CLKPADCTRL2 */
                        0x81f1f108, /* EMC_XM2COMPPADCTRL */
                        0x07070004, /* EMC_XM2VTTGENPADCTRL */
                        0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
@@ -1974,13 +1974,10 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x013a000e, /* EMC_MRS_WAIT_CNT */
-                       0x013a000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x013a0010, /* EMC_MRS_WAIT_CNT */
+                       0x013a0010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
-                       0x00000004, /* EMC_CTT_DURATION */
+                       0x00000003, /* EMC_CTT_DURATION */
                        0x000052a0, /* EMC_CFG_PIPE */
                        0x80002062, /* EMC_DYN_SELF_REF_CONTROL */
                        0x0000000c, /* EMC_QPOP */
@@ -1990,7 +1987,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000003, /* MC_EMEM_ARB_TIMING_RP */
                        0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
                        0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
                        0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
                        0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
                        0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
@@ -1999,7 +1996,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
                        0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
                        0x06050202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
+                       0x000f080c, /* MC_EMEM_ARB_DA_COVERS */
                        0x7428180d, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
                },
@@ -2041,36 +2038,39 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                0x00000802, /* EMC_CTT_TERM_CTRL */
                0x73300000, /* EMC_CFG */
                0x00000895, /* EMC_CFG_2 */
-               0x00040128, /* EMC_SEL_DPD_CTRL */
+               0x00040008, /* EMC_SEL_DPD_CTRL */
                0xe0120069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000941, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1440,       /* expected dvfs latency (ns) */
        },
        {
-               0x15,       /* V5.0.2 */
-               "01_624000_V01_V5.0.2_V0.3", /* DVFS table version */
-               624000,     /* SDRAM frequency */
-               910,        /* min voltage */
+               0x18,       /* V5.0.6 */
+               "06_600000_01_V5.0.6_V0.8", /* DVFS table version */
+               600000,     /* SDRAM frequency */
+               920,        /* min voltage */
                900,        /* gpu min voltage */
-               "pllm_ud",  /* clock source id */
-               0x80000000, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
+               "pllc_ud",  /* clock source id */
+               0xe0000000, /* CLK_SOURCE_EMC */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
-                       0x0000001c, /* EMC_RC */
-                       0x000000a1, /* EMC_RFC */
+                       0x0000001a, /* EMC_RC */
+                       0x0000009a, /* EMC_RFC */
                        0x00000000, /* EMC_RFC_SLR */
-                       0x00000014, /* EMC_RAS */
-                       0x00000007, /* EMC_RP */
+                       0x00000012, /* EMC_RAS */
+                       0x00000006, /* EMC_RP */
                        0x00000007, /* EMC_R2W */
                        0x0000000b, /* EMC_W2R */
                        0x00000003, /* EMC_R2P */
                        0x00000010, /* EMC_W2P */
-                       0x00000007, /* EMC_RD_RCD */
-                       0x00000007, /* EMC_WR_RCD */
+                       0x00000006, /* EMC_RD_RCD */
+                       0x00000006, /* EMC_WR_RCD */
                        0x00000002, /* EMC_RRD */
                        0x00000002, /* EMC_REXT */
                        0x00000000, /* EMC_WEXT */
@@ -2081,40 +2081,40 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_IBDLY */
                        0x00000003, /* EMC_EINPUT */
                        0x0000000b, /* EMC_EINPUT_DURATION */
-                       0x00080000, /* EMC_PUTERM_EXTRA */
-                       0x00000004, /* EMC_PUTERM_WIDTH */
+                       0x00070000, /* EMC_PUTERM_EXTRA */
+                       0x00000003, /* EMC_PUTERM_WIDTH */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
                        0x00000000, /* EMC_CDB_CNTL_3 */
                        0x00000002, /* EMC_QRST */
-                       0x00000013, /* EMC_QSAFE */
+                       0x00000012, /* EMC_QSAFE */
                        0x00000016, /* EMC_RDV */
                        0x00000018, /* EMC_RDV_MASK */
-                       0x000012c3, /* EMC_REFRESH */
+                       0x00001208, /* EMC_REFRESH */
                        0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x000004b0, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000482, /* EMC_PRE_REFRESH_REQ_CNT */
                        0x00000002, /* EMC_PDEX2WR */
                        0x0000000d, /* EMC_PDEX2RD */
                        0x00000001, /* EMC_PCHG2PDEN */
                        0x00000000, /* EMC_ACT2PDEN */
-                       0x0000009c, /* EMC_AR2PDEN */
+                       0x00000096, /* EMC_AR2PDEN */
                        0x00000015, /* EMC_RW2PDEN */
-                       0x000000a9, /* EMC_TXSR */
+                       0x000000a2, /* EMC_TXSR */
                        0x00000200, /* EMC_TXSRDLL */
                        0x00000004, /* EMC_TCKE */
                        0x00000005, /* EMC_TCKESR */
                        0x00000004, /* EMC_TPD */
-                       0x00000016, /* EMC_TFAW */
+                       0x0000000c, /* EMC_TFAW */
                        0x00000000, /* EMC_TRPAB */
-                       0x00000007, /* EMC_TCLKSTABLE */
-                       0x00000007, /* EMC_TCLKSTOP */
-                       0x00001304, /* EMC_TREFBW */
-                       0x00000002, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_TCLKSTABLE */
+                       0x00000006, /* EMC_TCLKSTOP */
+                       0x00001248, /* EMC_TREFBW */
+                       0x00000000, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
-                       0x1047b898, /* EMC_FBIO_CFG5 */
-                       0xe00d01b1, /* EMC_CFG_DIG_DLL */
+                       0x1040b098, /* EMC_FBIO_CFG5 */
+                       0xe00e00b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x0000000a, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000a, /* EMC_DLL_XFORM_DQS1 */
@@ -2140,11 +2140,11 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR0 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR1 */
+                       0x0004c000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x0004c000, /* EMC_DLL_XFORM_ADDR1 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR3 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR4 */
+                       0x0004c000, /* EMC_DLL_XFORM_ADDR3 */
+                       0x0004c000, /* EMC_DLL_XFORM_ADDR4 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE8 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -2170,14 +2170,14 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x007f800d, /* EMC_DLL_XFORM_DQ0 */
-                       0x007f800e, /* EMC_DLL_XFORM_DQ1 */
-                       0x007f800d, /* EMC_DLL_XFORM_DQ2 */
-                       0x007f800e, /* EMC_DLL_XFORM_DQ3 */
-                       0x0007f80d, /* EMC_DLL_XFORM_DQ4 */
-                       0x0007f80d, /* EMC_DLL_XFORM_DQ5 */
-                       0x0007f80d, /* EMC_DLL_XFORM_DQ6 */
-                       0x0007f80d, /* EMC_DLL_XFORM_DQ7 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ0 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ7 */
                        0x100002a0, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -2185,7 +2185,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_XM2DQPADCTRL2 */
                        0x00000000, /* EMC_XM2DQPADCTRL3 */
                        0x77ffc085, /* EMC_XM2CLKPADCTRL */
-                       0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000606, /* EMC_XM2CLKPADCTRL2 */
                        0x81f1f108, /* EMC_XM2COMPPADCTRL */
                        0x07070004, /* EMC_XM2VTTGENPADCTRL */
                        0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
@@ -2199,23 +2199,20 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x0122000e, /* EMC_MRS_WAIT_CNT */
-                       0x0122000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x01280010, /* EMC_MRS_WAIT_CNT */
+                       0x01280010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
-                       0x00000004, /* EMC_CTT_DURATION */
+                       0x00000003, /* EMC_CTT_DURATION */
                        0x000040a0, /* EMC_CFG_PIPE */
-                       0x80002617, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x800024aa, /* EMC_DYN_SELF_REF_CONTROL */
                        0x0000000e, /* EMC_QPOP */
-                       0x06000009, /* MC_EMEM_ARB_CFG */
+                       0x00000009, /* MC_EMEM_ARB_CFG */
                        0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
-                       0x00000004, /* MC_EMEM_ARB_TIMING_RP */
-                       0x0000000f, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RP */
+                       0x0000000d, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
                        0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
                        0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
                        0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
@@ -2224,79 +2221,82 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
                        0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
                        0x07050202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */
-                       0x736a1d10, /* MC_EMEM_ARB_MISC0 */
+                       0x00120a0d, /* MC_EMEM_ARB_DA_COVERS */
+                       0x73a91b0e, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
                },
                {
                        0x0000000f, /* MC_MLL_MPCORER_PTSA_RATE */
-                       0x0000012b, /* MC_PTSA_GRANT_DECREMENT */
-                       0x00a40038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-                       0x00a40038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-                       0x00a4003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-                       0x00a40090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-                       0x00a40041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-                       0x00a40090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-                       0x00a40041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+                       0x00000120, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00aa0038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+                       0x00aa0038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+                       0x00aa003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+                       0x00aa0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+                       0x00aa0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+                       0x00aa0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+                       0x00aa0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
                        0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-                       0x00a40080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-                       0x00a40004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-                       0x00a40004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-                       0x0008001c, /* MC_LATENCY_ALLOWANCE_HC_0 */
-                       0x000000a4, /* MC_LATENCY_ALLOWANCE_HC_1 */
-                       0x00a40004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-                       0x00a40020, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-                       0x00a40018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-                       0x00a40024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-                       0x00a40023, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-                       0x000000a4, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+                       0x00aa0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+                       0x00aa0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+                       0x00aa0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+                       0x0008001d, /* MC_LATENCY_ALLOWANCE_HC_0 */
+                       0x000000aa, /* MC_LATENCY_ALLOWANCE_HC_1 */
+                       0x00aa0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+                       0x00aa0022, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+                       0x00aa0018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+                       0x00aa0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+                       0x00aa0024, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+                       0x000000aa, /* MC_LATENCY_ALLOWANCE_VI2_0 */
                        0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-                       0x00a400a4, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+                       0x00aa00aa, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
                        0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-                       0x00a400a4, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+                       0x00aa00aa, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
                        0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
                        0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-                       0x00a400a4, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-                       0x00a400a4, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-                       0x00a40065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-                       0x00a40024, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+                       0x00aa00aa, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+                       0x00aa00aa, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+                       0x00aa0065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+                       0x00aa0025, /* MC_LATENCY_ALLOWANCE_AFI_0 */
                },
                0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0x00000802, /* EMC_CTT_TERM_CTRL */
                0x73300000, /* EMC_CFG */
                0x0000089d, /* EMC_CFG_2 */
-               0x00040128, /* EMC_SEL_DPD_CTRL */
-               0xe00d0169, /* EMC_CFG_DIG_DLL */
+               0x00040008, /* EMC_SEL_DPD_CTRL */
+               0xe00e0069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000b61, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200010, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1230,       /* expected dvfs latency (ns) */
        },
        {
-               0x15,       /* V5.0.2 */
-               "01_792000_V01_V5.0.2_V0.3", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_792000_01_V5.0.6_V0.8", /* DVFS table version */
                792000,     /* SDRAM frequency */
                1000,       /* min voltage */
                1100,       /* gpu min voltage */
-               "pllc_out0", /* clock source id */
-               0x20000000, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
+               "pllm_ud",  /* clock source id */
+               0x80000000, /* CLK_SOURCE_EMC */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
-                       0x00000024, /* EMC_RC */
+                       0x00000023, /* EMC_RC */
                        0x000000cc, /* EMC_RFC */
                        0x00000000, /* EMC_RFC_SLR */
                        0x00000019, /* EMC_RAS */
-                       0x0000000a, /* EMC_RP */
+                       0x00000009, /* EMC_RP */
                        0x00000008, /* EMC_R2W */
                        0x0000000d, /* EMC_W2R */
                        0x00000004, /* EMC_R2P */
                        0x00000013, /* EMC_W2P */
-                       0x0000000a, /* EMC_RD_RCD */
-                       0x0000000a, /* EMC_WR_RCD */
-                       0x00000003, /* EMC_RRD */
+                       0x00000009, /* EMC_RD_RCD */
+                       0x00000009, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
                        0x00000002, /* EMC_REXT */
                        0x00000000, /* EMC_WEXT */
                        0x00000006, /* EMC_WDV */
@@ -2304,18 +2304,18 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x0000000b, /* EMC_QUSE */
                        0x00000002, /* EMC_QUSE_WIDTH */
                        0x00000000, /* EMC_IBDLY */
-                       0x00000004, /* EMC_EINPUT */
-                       0x0000000c, /* EMC_EINPUT_DURATION */
-                       0x000a0000, /* EMC_PUTERM_EXTRA */
+                       0x00000002, /* EMC_EINPUT */
+                       0x0000000d, /* EMC_EINPUT_DURATION */
+                       0x00080000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
                        0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000003, /* EMC_QRST */
-                       0x00000013, /* EMC_QSAFE */
-                       0x00000018, /* EMC_RDV */
-                       0x0000001a, /* EMC_RDV_MASK */
+                       0x00000001, /* EMC_QRST */
+                       0x00000014, /* EMC_QSAFE */
+                       0x00000017, /* EMC_RDV */
+                       0x00000019, /* EMC_RDV_MASK */
                        0x000017e2, /* EMC_REFRESH */
                        0x00000000, /* EMC_BURST_REFRESH_NUM */
                        0x000005f8, /* EMC_PRE_REFRESH_REQ_CNT */
@@ -2330,16 +2330,16 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000005, /* EMC_TCKE */
                        0x00000006, /* EMC_TCKESR */
                        0x00000005, /* EMC_TPD */
-                       0x0000001d, /* EMC_TFAW */
+                       0x00000011, /* EMC_TFAW */
                        0x00000000, /* EMC_TRPAB */
                        0x00000008, /* EMC_TCLKSTABLE */
                        0x00000008, /* EMC_TCLKSTOP */
                        0x00001822, /* EMC_TREFBW */
-                       0x00000002, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
-                       0x1047b898, /* EMC_FBIO_CFG5 */
-                       0xe00701b1, /* EMC_CFG_DIG_DLL */
+                       0x1040b098, /* EMC_FBIO_CFG5 */
+                       0xe00700b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x00000008, /* EMC_DLL_XFORM_DQS0 */
                        0x00000008, /* EMC_DLL_XFORM_DQS1 */
@@ -2365,11 +2365,11 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR0 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00038000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00038000, /* EMC_DLL_XFORM_ADDR1 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR3 */
-                       0x0000000e, /* EMC_DLL_XFORM_ADDR4 */
+                       0x00038000, /* EMC_DLL_XFORM_ADDR3 */
+                       0x00038000, /* EMC_DLL_XFORM_ADDR4 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE8 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -2395,14 +2395,14 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ0 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ1 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ2 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQ7 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ0 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ7 */
                        0x100002a0, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -2410,38 +2410,35 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_XM2DQPADCTRL2 */
                        0x00000000, /* EMC_XM2DQPADCTRL3 */
                        0x77ffc085, /* EMC_XM2CLKPADCTRL */
-                       0x00000c0c, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000606, /* EMC_XM2CLKPADCTRL2 */
                        0x81f1f108, /* EMC_XM2COMPPADCTRL */
                        0x07070004, /* EMC_XM2VTTGENPADCTRL */
                        0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
                        0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x59659600, /* EMC_XM2DQSPADCTRL3 */
+                       0x61861820, /* EMC_XM2DQSPADCTRL3 */
                        0x00514514, /* EMC_XM2DQSPADCTRL4 */
                        0x00514514, /* EMC_XM2DQSPADCTRL5 */
-                       0x59659600, /* EMC_XM2DQSPADCTRL6 */
+                       0x61861800, /* EMC_XM2DQSPADCTRL6 */
                        0x0606003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x00f8000e, /* EMC_MRS_WAIT_CNT */
-                       0x00f8000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00f80010, /* EMC_MRS_WAIT_CNT */
+                       0x00f80010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x000040a0, /* EMC_CFG_PIPE */
                        0x80003012, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x00000010, /* EMC_QPOP */
+                       0x0000000f, /* EMC_QPOP */
                        0x0e00000b, /* MC_EMEM_ARB_CFG */
                        0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
                        0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
                        0x00000005, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000013, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000012, /* MC_EMEM_ARB_TIMING_RC */
                        0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
-                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000009, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
                        0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
                        0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
                        0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
@@ -2449,8 +2446,8 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
                        0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
                        0x08060202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x00170e13, /* MC_EMEM_ARB_DA_COVERS */
-                       0x734c2414, /* MC_EMEM_ARB_MISC0 */
+                       0x00160d12, /* MC_EMEM_ARB_DA_COVERS */
+                       0x734c2413, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
                },
                {
@@ -2492,55 +2489,58 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                0x73300000, /* EMC_CFG */
                0x0000089d, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
-               0xe0070169, /* EMC_CFG_DIG_DLL */
+               0xe0070069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430606, /* EMC_AUTO_CAL_CONFIG */
                0x80000d71, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200018, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1200,       /* expected dvfs latency (ns) */
        },
        {
-               0x15,       /* V5.0.2 */
-               "01_924000_V01_V5.0.2_V0.3", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "06_924000_01_V5.0.6_V0.8", /* DVFS table version */
                924000,     /* SDRAM frequency */
-               1100,       /* min voltage */
+               1010,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               167,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
-                       0x0000002b, /* EMC_RC */
+                       0x00000029, /* EMC_RC */
                        0x000000ef, /* EMC_RFC */
                        0x00000000, /* EMC_RFC_SLR */
-                       0x0000001e, /* EMC_RAS */
+                       0x0000001d, /* EMC_RAS */
                        0x0000000b, /* EMC_RP */
-                       0x00000009, /* EMC_R2W */
+                       0x0000000a, /* EMC_R2W */
                        0x0000000f, /* EMC_W2R */
                        0x00000005, /* EMC_R2P */
                        0x00000016, /* EMC_W2P */
                        0x0000000b, /* EMC_RD_RCD */
                        0x0000000b, /* EMC_WR_RCD */
-                       0x00000004, /* EMC_RRD */
+                       0x00000003, /* EMC_RRD */
                        0x00000002, /* EMC_REXT */
                        0x00000000, /* EMC_WEXT */
                        0x00000007, /* EMC_WDV */
                        0x00000007, /* EMC_WDV_MASK */
-                       0x0000000e, /* EMC_QUSE */
+                       0x0000000d, /* EMC_QUSE */
                        0x00000002, /* EMC_QUSE_WIDTH */
                        0x00000000, /* EMC_IBDLY */
-                       0x00000004, /* EMC_EINPUT */
-                       0x0000000e, /* EMC_EINPUT_DURATION */
-                       0x000c0000, /* EMC_PUTERM_EXTRA */
+                       0x00000002, /* EMC_EINPUT */
+                       0x0000000f, /* EMC_EINPUT_DURATION */
+                       0x000a0000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
                        0x00000000, /* EMC_CDB_CNTL_3 */
-                       0x00000003, /* EMC_QRST */
-                       0x00000015, /* EMC_QSAFE */
-                       0x0000001b, /* EMC_RDV */
-                       0x0000001d, /* EMC_RDV_MASK */
+                       0x00000001, /* EMC_QRST */
+                       0x00000016, /* EMC_QSAFE */
+                       0x0000001a, /* EMC_RDV */
+                       0x0000001c, /* EMC_RDV_MASK */
                        0x00001be7, /* EMC_REFRESH */
                        0x00000000, /* EMC_BURST_REFRESH_NUM */
                        0x000006f9, /* EMC_PRE_REFRESH_REQ_CNT */
@@ -2555,7 +2555,7 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000006, /* EMC_TCKE */
                        0x00000007, /* EMC_TCKESR */
                        0x00000006, /* EMC_TPD */
-                       0x00000022, /* EMC_TFAW */
+                       0x00000015, /* EMC_TFAW */
                        0x00000000, /* EMC_TRPAB */
                        0x0000000a, /* EMC_TCLKSTABLE */
                        0x0000000a, /* EMC_TCLKSTOP */
@@ -2563,25 +2563,25 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
-                       0x1047b898, /* EMC_FBIO_CFG5 */
-                       0xe00401b1, /* EMC_CFG_DIG_DLL */
+                       0x1040b898, /* EMC_FBIO_CFG5 */
+                       0xe00400b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS0 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS1 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS2 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS3 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS4 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS5 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS6 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS7 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS8 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS9 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS10 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS11 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS12 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS13 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS14 */
-                       0x007f800a, /* EMC_DLL_XFORM_DQS15 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS0 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS1 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS2 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS3 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS4 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS5 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS6 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS7 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS8 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS9 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS10 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS11 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS12 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS13 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS14 */
+                       0x007f400a, /* EMC_DLL_XFORM_DQS15 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE1 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -2590,11 +2590,11 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x00000010, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000010, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00028000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00028000, /* EMC_DLL_XFORM_ADDR1 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00000010, /* EMC_DLL_XFORM_ADDR3 */
-                       0x00000010, /* EMC_DLL_XFORM_ADDR4 */
+                       0x00028000, /* EMC_DLL_XFORM_ADDR3 */
+                       0x00028000, /* EMC_DLL_XFORM_ADDR4 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE8 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -2620,14 +2620,14 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x007f800c, /* EMC_DLL_XFORM_DQ0 */
-                       0x007f800c, /* EMC_DLL_XFORM_DQ1 */
-                       0x007f800c, /* EMC_DLL_XFORM_DQ2 */
-                       0x007f800c, /* EMC_DLL_XFORM_DQ3 */
-                       0x0007f80c, /* EMC_DLL_XFORM_DQ4 */
-                       0x0007f80c, /* EMC_DLL_XFORM_DQ5 */
-                       0x0007f80c, /* EMC_DLL_XFORM_DQ6 */
-                       0x0007f80c, /* EMC_DLL_XFORM_DQ7 */
+                       0x007f800d, /* EMC_DLL_XFORM_DQ0 */
+                       0x007f800d, /* EMC_DLL_XFORM_DQ1 */
+                       0x007f800d, /* EMC_DLL_XFORM_DQ2 */
+                       0x007f800d, /* EMC_DLL_XFORM_DQ3 */
+                       0x0007f80d, /* EMC_DLL_XFORM_DQ4 */
+                       0x0007f80d, /* EMC_DLL_XFORM_DQ5 */
+                       0x0007f80d, /* EMC_DLL_XFORM_DQ6 */
+                       0x0007f80d, /* EMC_DLL_XFORM_DQ7 */
                        0x100002a0, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -2635,47 +2635,44 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                        0x00000000, /* EMC_XM2DQPADCTRL2 */
                        0x00000000, /* EMC_XM2DQPADCTRL3 */
                        0x77ffc085, /* EMC_XM2CLKPADCTRL */
-                       0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
                        0x81f1f108, /* EMC_XM2COMPPADCTRL */
                        0x07070004, /* EMC_XM2VTTGENPADCTRL */
                        0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
                        0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x5d75d720, /* EMC_XM2DQSPADCTRL3 */
-                       0x00492492, /* EMC_XM2DQSPADCTRL4 */
-                       0x00492492, /* EMC_XM2DQSPADCTRL5 */
-                       0x5d75d700, /* EMC_XM2DQSPADCTRL6 */
+                       0x55555520, /* EMC_XM2DQSPADCTRL3 */
+                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
+                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
+                       0x55555500, /* EMC_XM2DQSPADCTRL6 */
                        0x0606003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000128, /* EMC_ZCAL_WAIT_CNT */
-                       0x00ce000e, /* EMC_MRS_WAIT_CNT */
-                       0x00ce000e, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00ce0010, /* EMC_MRS_WAIT_CNT */
+                       0x00ce0010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x00004080, /* EMC_CFG_PIPE */
                        0x800037ea, /* EMC_DYN_SELF_REF_CONTROL */
-                       0x00000012, /* EMC_QPOP */
+                       0x00000011, /* EMC_QPOP */
                        0x0e00000d, /* MC_EMEM_ARB_CFG */
                        0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
                        0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
                        0x00000006, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000016, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000015, /* MC_EMEM_ARB_TIMING_RC */
                        0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
-                       0x00000011, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
                        0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
                        0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
                        0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
                        0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
                        0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
                        0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
-                       0x09060202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x001a1016, /* MC_EMEM_ARB_DA_COVERS */
-                       0x734e2a17, /* MC_EMEM_ARB_MISC0 */
+                       0x09070202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x001a1015, /* MC_EMEM_ARB_DA_COVERS */
+                       0x734e2a16, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
                },
                {
@@ -2717,25 +2714,253 @@ static struct tegra12_emc_table loki_a02_emc_table[] = {
                0x73300000, /* EMC_CFG */
                0x0000089d, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
-               0xe0040169, /* EMC_CFG_DIG_DLL */
+               0xe0040069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430606, /* EMC_AUTO_CAL_CONFIG */
                0x80000f15, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200020, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1180,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x18,       /* V5.0.6 */
+               "06_1056000_01_V5.0.6_V0.8", /* DVFS table version */
+               1056000,    /* SDRAM frequency */
+               1100,       /* min voltage */
+               1100,       /* gpu min voltage */
+               "pllm_ud",  /* clock source id */
+               0x80000000, /* CLK_SOURCE_EMC */
+               164,        /* number of burst_regs */
+               31,         /* number of up_down_regs */
+               {
+                       0x0000002f, /* EMC_RC */
+                       0x00000111, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000021, /* EMC_RAS */
+                       0x0000000c, /* EMC_RP */
+                       0x0000000a, /* EMC_R2W */
+                       0x00000011, /* EMC_W2R */
+                       0x00000006, /* EMC_R2P */
+                       0x00000019, /* EMC_W2P */
+                       0x0000000c, /* EMC_RD_RCD */
+                       0x0000000c, /* EMC_WR_RCD */
+                       0x00000004, /* EMC_RRD */
+                       0x00000002, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000007, /* EMC_WDV */
+                       0x00000007, /* EMC_WDV_MASK */
+                       0x0000000e, /* EMC_QUSE */
+                       0x00000002, /* EMC_QUSE_WIDTH */
+                       0x00000000, /* EMC_IBDLY */
+                       0x00000002, /* EMC_EINPUT */
+                       0x00000010, /* EMC_EINPUT_DURATION */
+                       0x000b0000, /* EMC_PUTERM_EXTRA */
+                       0x00000004, /* EMC_PUTERM_WIDTH */
+                       0x00000000, /* EMC_PUTERM_ADJ */
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000000, /* EMC_CDB_CNTL_3 */
+                       0x00000001, /* EMC_QRST */
+                       0x00000017, /* EMC_QSAFE */
+                       0x0000001d, /* EMC_RDV */
+                       0x0000001f, /* EMC_RDV_MASK */
+                       0x00001fed, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000007fb, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000005, /* EMC_PDEX2WR */
+                       0x00000018, /* EMC_PDEX2RD */
+                       0x00000002, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000106, /* EMC_AR2PDEN */
+                       0x0000001e, /* EMC_RW2PDEN */
+                       0x0000011e, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000007, /* EMC_TCKE */
+                       0x00000008, /* EMC_TCKESR */
+                       0x00000007, /* EMC_TPD */
+                       0x00000018, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x0000000b, /* EMC_TCLKSTABLE */
+                       0x0000000b, /* EMC_TCLKSTOP */
+                       0x0000202d, /* EMC_TREFBW */
+                       0x00000000, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x1040b898, /* EMC_FBIO_CFG5 */
+                       0xe00400b1, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00000002, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS1 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS2 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS8 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS9 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS10 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS11 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS12 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS13 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS14 */
+                       0x00000002, /* EMC_DLL_XFORM_DQS15 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x0000000a, /* EMC_DLL_XFORM_ADDR0 */
+                       0x0000000a, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0000000a, /* EMC_DLL_XFORM_ADDR3 */
+                       0x0000000a, /* EMC_DLL_XFORM_ADDR4 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ0 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ7 */
+                       0x100002a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
+                       0x0120113d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL3 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+                       0x55555520, /* EMC_XM2DQSPADCTRL3 */
+                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
+                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
+                       0x55555500, /* EMC_XM2DQSPADCTRL6 */
+                       0x0606003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x00000000, /* EMC_FBIO_SPARE */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000152, /* EMC_ZCAL_WAIT_CNT */
+                       0x00a30010, /* EMC_MRS_WAIT_CNT */
+                       0x00a30010, /* EMC_MRS_WAIT_CNT2 */
+                       0x0000000a, /* EMC_CTT */
+                       0x00000004, /* EMC_CTT_DURATION */
+                       0x00000000, /* EMC_CFG_PIPE */
+                       0x80003fc1, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000012, /* EMC_QPOP */
+                       0x0d00000f, /* MC_EMEM_ARB_CFG */
+                       0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000018, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000010, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x0000000f, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x0000000a, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x0a070202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x001c1118, /* MC_EMEM_ARB_DA_COVERS */
+                       0x73503019, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x0000001a, /* MC_MLL_MPCORER_PTSA_RATE */
+                       0x000001fa, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00600038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+                       0x00600038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+                       0x0060003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+                       0x00600090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+                       0x00600041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+                       0x00600090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+                       0x00600041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+                       0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+                       0x00600080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+                       0x00600004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+                       0x00600004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+                       0x00080016, /* MC_LATENCY_ALLOWANCE_HC_0 */
+                       0x00000060, /* MC_LATENCY_ALLOWANCE_HC_1 */
+                       0x00600004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+                       0x00600019, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+                       0x00600018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+                       0x00600024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+                       0x0060001b, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+                       0x00000060, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+                       0x00600060, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+                       0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+                       0x00600060, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+                       0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+                       0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+                       0x00600060, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+                       0x00600060, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+                       0x00600065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+                       0x0060001c, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+               },
+               0x00000057, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000802, /* EMC_CTT_TERM_CTRL */
+               0x73300000, /* EMC_CFG */
+               0x000008a5, /* EMC_CFG_2 */
+               0x00040000, /* EMC_SEL_DPD_CTRL */
+               0xe0040069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x06060606, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000606, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430606, /* EMC_AUTO_CAL_CONFIG */
+               0x80000125, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200028, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
        },
 };
 
-static struct tegra12_emc_table loki_b00_emc_table[] = {
+static struct tegra12_emc_table loki_b00_sku100_emc_table[] = {
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_12750_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "01_12750_01_V5.0.6_V0.8", /* DVFS table version */
                12750,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x4000003e, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000000, /* EMC_RC */
@@ -2761,7 +2986,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -2795,22 +3019,22 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x10604098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS8 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS9 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS10 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS11 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS12 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS13 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS14 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS15 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE1 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -2849,14 +3073,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ4 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ5 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ6 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -2878,11 +3102,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00000000, /* EMC_ZCAL_INTERVAL */
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x00100010, /* EMC_MRS_WAIT_CNT */
-                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x000f000f, /* EMC_MRS_WAIT_CNT */
+                       0x000f000f, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -2947,21 +3168,24 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               57820,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_20400_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "01_20400_01_V5.0.6_V0.8", /* DVFS table version */
                20400,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000026, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000000, /* EMC_RC */
@@ -2987,7 +3211,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -3021,22 +3244,22 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x10604098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS8 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS9 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS10 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS11 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS12 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS13 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS14 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS15 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE1 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -3075,14 +3298,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ4 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ5 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ6 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -3104,11 +3327,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00000000, /* EMC_ZCAL_INTERVAL */
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x00100010, /* EMC_MRS_WAIT_CNT */
-                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x000f000f, /* EMC_MRS_WAIT_CNT */
+                       0x000f000f, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -3173,21 +3393,24 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               35610,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_40800_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "01_40800_01_V5.0.6_V0.8", /* DVFS table version */
                40800,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000012, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000001, /* EMC_RC */
@@ -3213,7 +3436,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -3247,22 +3469,22 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x10604098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS8 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS9 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS10 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS11 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS12 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS13 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS14 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS15 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE1 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -3301,14 +3523,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ4 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ5 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ6 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -3330,11 +3552,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00000000, /* EMC_ZCAL_INTERVAL */
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x00100010, /* EMC_MRS_WAIT_CNT */
-                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x000f000f, /* EMC_MRS_WAIT_CNT */
+                       0x000f000f, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -3399,21 +3618,24 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               20850,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_68000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "01_68000_01_V5.0.6_V0.8", /* DVFS table version */
                68000,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x4000000a, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000003, /* EMC_RC */
@@ -3439,7 +3661,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -3473,22 +3694,22 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x10604098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS8 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS9 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS10 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS11 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS12 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS13 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS14 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS15 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE1 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -3527,14 +3748,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ4 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ5 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ6 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -3556,11 +3777,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00000000, /* EMC_ZCAL_INTERVAL */
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x00100010, /* EMC_MRS_WAIT_CNT */
-                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x000f000f, /* EMC_MRS_WAIT_CNT */
+                       0x000f000f, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -3625,21 +3843,24 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               10720,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_102000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "01_102000_01_V5.0.6_V0.8", /* DVFS table version */
                102000,     /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000006, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000004, /* EMC_RC */
@@ -3665,7 +3886,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -3699,22 +3919,22 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x10604098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS8 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS9 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS10 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS11 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS12 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS13 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS14 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS15 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE1 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -3753,14 +3973,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
-                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
-                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ4 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ5 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ6 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -3782,11 +4002,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00000000, /* EMC_ZCAL_INTERVAL */
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
-                       0x00100010, /* EMC_MRS_WAIT_CNT */
-                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x000f000f, /* EMC_MRS_WAIT_CNT */
+                       0x000f000f, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -3851,21 +4068,24 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               6890,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_204000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "01_204000_01_V5.0.6_V0.8", /* DVFS table version */
                204000,     /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000009, /* EMC_RC */
@@ -3891,7 +4111,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000005, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -3925,22 +4144,22 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x10604098, /* EMC_FBIO_CFG5 */
                        0x002c00a0, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
-                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS8 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS9 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS10 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS11 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS12 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS13 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS14 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS15 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE1 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -3979,14 +4198,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x00090000, /* EMC_DLL_XFORM_DQ0 */
-                       0x00090000, /* EMC_DLL_XFORM_DQ1 */
-                       0x00090000, /* EMC_DLL_XFORM_DQ2 */
-                       0x00090000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00009000, /* EMC_DLL_XFORM_DQ4 */
-                       0x00009000, /* EMC_DLL_XFORM_DQ5 */
-                       0x00009000, /* EMC_DLL_XFORM_DQ6 */
-                       0x00009000, /* EMC_DLL_XFORM_DQ7 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ4 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ5 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ6 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -4008,11 +4227,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x00100010, /* EMC_MRS_WAIT_CNT */
-                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x000f000f, /* EMC_MRS_WAIT_CNT */
+                       0x000f000f, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -4077,27 +4293,30 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008cd, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               3420,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_300000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "01_300000_01_V5.0.6_V0.8", /* DVFS table version */
                300000,     /* SDRAM frequency */
-               800,        /* min voltage */
+               810,        /* min voltage */
                800,        /* gpu min voltage */
                "pllc_out0", /* clock source id */
                0x20000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000000c, /* EMC_RC */
                        0x0000004c, /* EMC_RFC */
                        0x00000000, /* EMC_RFC_SLR */
-                       0x00000008, /* EMC_RAS */
+                       0x00000009, /* EMC_RAS */
                        0x00000002, /* EMC_RP */
                        0x00000004, /* EMC_R2W */
                        0x00000008, /* EMC_W2R */
@@ -4117,7 +4336,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000006, /* EMC_EINPUT_DURATION */
                        0x00030000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -4175,11 +4393,11 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-                       0x0009c000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x0009c000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00068000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00068000, /* EMC_DLL_XFORM_ADDR1 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x0009c000, /* EMC_DLL_XFORM_ADDR3 */
-                       0x0009c000, /* EMC_DLL_XFORM_ADDR4 */
+                       0x00068000, /* EMC_DLL_XFORM_ADDR3 */
+                       0x00068000, /* EMC_DLL_XFORM_ADDR4 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE8 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -4205,14 +4423,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x00060000, /* EMC_DLL_XFORM_DQ0 */
-                       0x00060000, /* EMC_DLL_XFORM_DQ1 */
-                       0x00060000, /* EMC_DLL_XFORM_DQ2 */
-                       0x00060000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00006000, /* EMC_DLL_XFORM_DQ4 */
-                       0x00006000, /* EMC_DLL_XFORM_DQ5 */
-                       0x00006000, /* EMC_DLL_XFORM_DQ6 */
-                       0x00006000, /* EMC_DLL_XFORM_DQ7 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ4 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ5 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ6 */
+                       0x00008000, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -4234,11 +4452,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x01740010, /* EMC_MRS_WAIT_CNT */
-                       0x01740010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x0174000f, /* EMC_MRS_WAIT_CNT */
+                       0x0174000f, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -4248,8 +4463,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
                        0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
                        0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000006, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
                        0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
                        0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
                        0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
@@ -4259,8 +4474,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
                        0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
                        0x06040202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x000a0506, /* MC_EMEM_ARB_DA_COVERS */
-                       0x77450e07, /* MC_EMEM_ARB_MISC0 */
+                       0x000a0507, /* MC_EMEM_ARB_DA_COVERS */
+                       0x77450e08, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
                },
                {
@@ -4303,21 +4518,24 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x000008cd, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000321, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200000, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               2680,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_396000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "01_396000_01_V5.0.6_V0.8", /* DVFS table version */
                396000,     /* SDRAM frequency */
-               870,        /* min voltage */
+               860,        /* min voltage */
                900,        /* gpu min voltage */
                "pllm_out0", /* clock source id */
                0x00000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000011, /* EMC_RC */
@@ -4343,7 +4561,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000006, /* EMC_EINPUT_DURATION */
                        0x00030000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -4431,14 +4648,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x00044000, /* EMC_DLL_XFORM_DQ0 */
-                       0x00044000, /* EMC_DLL_XFORM_DQ1 */
-                       0x00044000, /* EMC_DLL_XFORM_DQ2 */
-                       0x00044000, /* EMC_DLL_XFORM_DQ3 */
-                       0x00004400, /* EMC_DLL_XFORM_DQ4 */
-                       0x00004400, /* EMC_DLL_XFORM_DQ5 */
-                       0x00004400, /* EMC_DLL_XFORM_DQ6 */
-                       0x00004400, /* EMC_DLL_XFORM_DQ7 */
+                       0x00068000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00068000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00068000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00068000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00006800, /* EMC_DLL_XFORM_DQ4 */
+                       0x00006800, /* EMC_DLL_XFORM_DQ5 */
+                       0x00006800, /* EMC_DLL_XFORM_DQ6 */
+                       0x00006800, /* EMC_DLL_XFORM_DQ7 */
                        0x10000280, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -4460,11 +4677,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x015b0010, /* EMC_MRS_WAIT_CNT */
-                       0x015b0010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x015b000f, /* EMC_MRS_WAIT_CNT */
+                       0x015b000f, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -4529,21 +4743,24 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x0000088d, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000521, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200000, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               2180,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_528000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "01_528000_01_V5.0.6_V0.8", /* DVFS table version */
                528000,     /* SDRAM frequency */
-               900,        /* min voltage */
+               920,        /* min voltage */
                900,        /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000017, /* EMC_RC */
@@ -4569,7 +4786,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000007, /* EMC_EINPUT_DURATION */
                        0x00060000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -4601,7 +4817,7 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
                        0x1040b098, /* EMC_FBIO_CFG5 */
-                       0xe01200b1, /* EMC_CFG_DIG_DLL */
+                       0xe01d00b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x0000000a, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000a, /* EMC_DLL_XFORM_DQS1 */
@@ -4686,11 +4902,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x013a0010, /* EMC_MRS_WAIT_CNT */
-                       0x013a0010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x013a000f, /* EMC_MRS_WAIT_CNT */
+                       0x013a000f, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x000052a0, /* EMC_CFG_PIPE */
@@ -4754,28 +4967,31 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x73300000, /* EMC_CFG */
                0x00000895, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
-               0xe0120069, /* EMC_CFG_DIG_DLL */
+               0xe01d0069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000941, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1440,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_600000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "01_600000_01_V5.0.6_V0.8", /* DVFS table version */
                600000,     /* SDRAM frequency */
-               900,        /* min voltage */
+               920,        /* min voltage */
                900,        /* gpu min voltage */
                "pllc_ud",  /* clock source id */
                0xe0000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000001a, /* EMC_RC */
                        0x0000009a, /* EMC_RFC */
                        0x00000000, /* EMC_RFC_SLR */
-                       0x00000012, /* EMC_RAS */
+                       0x00000013, /* EMC_RAS */
                        0x00000006, /* EMC_RP */
                        0x00000007, /* EMC_R2W */
                        0x0000000b, /* EMC_W2R */
@@ -4795,7 +5011,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x0000000b, /* EMC_EINPUT_DURATION */
                        0x00070000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -4827,7 +5042,7 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
                        0x1040b098, /* EMC_FBIO_CFG5 */
-                       0xe00e00b1, /* EMC_CFG_DIG_DLL */
+                       0xe01900b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x0000000a, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000a, /* EMC_DLL_XFORM_DQS1 */
@@ -4912,11 +5127,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x01280010, /* EMC_MRS_WAIT_CNT */
-                       0x01280010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+                       0x0128000f, /* EMC_MRS_WAIT_CNT */
+                       0x0128000f, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x000040a0, /* EMC_CFG_PIPE */
@@ -4926,8 +5138,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
                        0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
                        0x00000003, /* MC_EMEM_ARB_TIMING_RP */
-                       0x0000000d, /* MC_EMEM_ARB_TIMING_RC */
-                       0x00000008, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000e, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
                        0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
                        0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
                        0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
@@ -4937,8 +5149,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
                        0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
                        0x07050202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x00120a0d, /* MC_EMEM_ARB_DA_COVERS */
-                       0x73a91b0e, /* MC_EMEM_ARB_MISC0 */
+                       0x00120a0e, /* MC_EMEM_ARB_DA_COVERS */
+                       0x73a91b0f, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
                },
                {
@@ -4980,22 +5192,25 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x73300000, /* EMC_CFG */
                0x0000089d, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
-               0xe00e0069, /* EMC_CFG_DIG_DLL */
+               0xe0190069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000b61, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200010, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1440,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_792000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "01_792000_01_V5.0.6_V0.8", /* DVFS table version */
                792000,     /* SDRAM frequency */
                1000,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000023, /* EMC_RC */
@@ -5021,7 +5236,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x0000000d, /* EMC_EINPUT_DURATION */
                        0x00080000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -5053,7 +5267,7 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
                        0x1040b098, /* EMC_FBIO_CFG5 */
-                       0xe00700b1, /* EMC_CFG_DIG_DLL */
+                       0xe01100b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x00000008, /* EMC_DLL_XFORM_DQS0 */
                        0x00000008, /* EMC_DLL_XFORM_DQS1 */
@@ -5138,11 +5352,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
-                       0x00f80010, /* EMC_MRS_WAIT_CNT */
-                       0x00f80010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430606, /* EMC_AUTO_CAL_CONFIG */
+                       0x00f8000f, /* EMC_MRS_WAIT_CNT */
+                       0x00f8000f, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x000040a0, /* EMC_CFG_PIPE */
@@ -5206,28 +5417,31 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x73300000, /* EMC_CFG */
                0x0000089d, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
-               0xe0070069, /* EMC_CFG_DIG_DLL */
+               0xe0110069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000d71, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200018, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1200,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "05_924000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "01_924000_01_V5.0.6_V0.8", /* DVFS table version */
                924000,     /* SDRAM frequency */
-               1100,       /* min voltage */
+               1010,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000029, /* EMC_RC */
                        0x000000ef, /* EMC_RFC */
                        0x00000000, /* EMC_RFC_SLR */
-                       0x0000001d, /* EMC_RAS */
+                       0x0000001e, /* EMC_RAS */
                        0x0000000b, /* EMC_RP */
                        0x0000000a, /* EMC_R2W */
                        0x0000000f, /* EMC_W2R */
@@ -5247,7 +5461,6 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x0000000f, /* EMC_EINPUT_DURATION */
                        0x000a0000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -5279,7 +5492,7 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
                        0x1040b898, /* EMC_FBIO_CFG5 */
-                       0xe00400b1, /* EMC_CFG_DIG_DLL */
+                       0xe00d00b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
                        0x007f400a, /* EMC_DLL_XFORM_DQS0 */
                        0x007f400a, /* EMC_DLL_XFORM_DQS1 */
@@ -5335,14 +5548,14 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x007f800d, /* EMC_DLL_XFORM_DQ0 */
-                       0x007f800d, /* EMC_DLL_XFORM_DQ1 */
-                       0x007f800d, /* EMC_DLL_XFORM_DQ2 */
-                       0x007f800d, /* EMC_DLL_XFORM_DQ3 */
-                       0x0007f80d, /* EMC_DLL_XFORM_DQ4 */
-                       0x0007f80d, /* EMC_DLL_XFORM_DQ5 */
-                       0x0007f80d, /* EMC_DLL_XFORM_DQ6 */
-                       0x0007f80d, /* EMC_DLL_XFORM_DQ7 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ0 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000000d, /* EMC_DLL_XFORM_DQ7 */
                        0x100002a0, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -5364,11 +5577,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000000, /* EMC_FBIO_SPARE */
                        0x00020000, /* EMC_ZCAL_INTERVAL */
                        0x00000128, /* EMC_ZCAL_WAIT_CNT */
-                       0x00ce0010, /* EMC_MRS_WAIT_CNT */
-                       0x00ce0010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430606, /* EMC_AUTO_CAL_CONFIG */
+                       0x00ce000f, /* EMC_MRS_WAIT_CNT */
+                       0x00ce000f, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x00004080, /* EMC_CFG_PIPE */
@@ -5378,7 +5588,7 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
                        0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
                        0x00000006, /* MC_EMEM_ARB_TIMING_RP */
-                       0x00000015, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000016, /* MC_EMEM_ARB_TIMING_RC */
                        0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
                        0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
                        0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
@@ -5389,8 +5599,8 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                        0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
                        0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
                        0x09070202, /* MC_EMEM_ARB_DA_TURNS */
-                       0x001a1015, /* MC_EMEM_ARB_DA_COVERS */
-                       0x734e2a16, /* MC_EMEM_ARB_MISC0 */
+                       0x001a1016, /* MC_EMEM_ARB_DA_COVERS */
+                       0x734e2a17, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
                },
                {
@@ -5432,25 +5642,28 @@ static struct tegra12_emc_table loki_b00_emc_table[] = {
                0x73300000, /* EMC_CFG */
                0x0000089d, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
-               0xe0040069, /* EMC_CFG_DIG_DLL */
+               0xe00d0069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430606, /* EMC_AUTO_CAL_CONFIG */
                0x80000f15, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200020, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1180,       /* expected dvfs latency (ns) */
        },
 };
 
 static struct tegra12_emc_table thor_195_b00_emc_table[] = {
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_12750_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_12750_01_V5.0.6_V0.8", /* DVFS table version */
                12750,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x4000003e, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000000, /* EMC_RC */
@@ -5476,7 +5689,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -5595,9 +5807,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -5662,21 +5871,24 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               57820,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_20400_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_20400_01_V5.0.6_V0.8", /* DVFS table version */
                20400,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000026, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000000, /* EMC_RC */
@@ -5702,7 +5914,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -5821,9 +6032,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -5888,21 +6096,24 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               35610,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_40800_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_40800_01_V5.0.6_V0.8", /* DVFS table version */
                40800,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000012, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000001, /* EMC_RC */
@@ -5928,7 +6139,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -6047,9 +6257,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -6114,21 +6321,24 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               20850,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_68000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_68000_01_V5.0.6_V0.8", /* DVFS table version */
                68000,      /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x4000000a, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000003, /* EMC_RC */
@@ -6154,7 +6364,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -6273,9 +6482,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -6340,21 +6546,24 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               10720,      /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_102000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_102000_01_V5.0.6_V0.8", /* DVFS table version */
                102000,     /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000006, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000004, /* EMC_RC */
@@ -6380,7 +6589,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000004, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -6499,9 +6707,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000042, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000f3f3, /* EMC_CFG_PIPE */
@@ -6566,21 +6771,24 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008c5, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               6890,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_204000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_204000_01_V5.0.6_V0.8", /* DVFS table version */
                204000,     /* SDRAM frequency */
                800,        /* min voltage */
                800,        /* gpu min voltage */
                "pllp_out0", /* clock source id */
                0x40000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000009, /* EMC_RC */
@@ -6606,7 +6814,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000005, /* EMC_EINPUT_DURATION */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000001, /* EMC_PUTERM_WIDTH */
-                       0x00000008, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -6725,9 +6932,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT */
                        0x00100010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000001, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -6792,21 +6996,24 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008cd, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80001221, /* Mode Register 0 */
                0x80100003, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               3420,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_300000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_300000_01_V5.0.6_V0.8", /* DVFS table version */
                300000,     /* SDRAM frequency */
-               800,        /* min voltage */
+               810,        /* min voltage */
                800,        /* gpu min voltage */
                "pllc_out0", /* clock source id */
                0x20000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000000c, /* EMC_RC */
@@ -6832,7 +7039,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000006, /* EMC_EINPUT_DURATION */
                        0x00030000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -6951,9 +7157,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x01740010, /* EMC_MRS_WAIT_CNT */
                        0x01740010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -7018,21 +7221,24 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008cd, /* EMC_CFG_2 */
                0x00040128, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000321, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200000, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               2680,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_396000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_396000_01_V5.0.6_V0.8", /* DVFS table version */
                396000,     /* SDRAM frequency */
-               870,        /* min voltage */
+               860,        /* min voltage */
                900,        /* gpu min voltage */
                "pllm_out0", /* clock source id */
                0x00000002, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000011, /* EMC_RC */
@@ -7058,7 +7264,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000006, /* EMC_EINPUT_DURATION */
                        0x00030000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -7177,9 +7382,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x015b0010, /* EMC_MRS_WAIT_CNT */
                        0x015b0010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x0000d3b3, /* EMC_CFG_PIPE */
@@ -7244,21 +7446,24 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x0000088d, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000521, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200000, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               2180,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_528000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_528000_01_V5.0.6_V0.8", /* DVFS table version */
                528000,     /* SDRAM frequency */
-               900,        /* min voltage */
+               920,        /* min voltage */
                900,        /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000017, /* EMC_RC */
@@ -7284,7 +7489,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000007, /* EMC_EINPUT_DURATION */
                        0x00060000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -7403,9 +7607,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x013a0010, /* EMC_MRS_WAIT_CNT */
                        0x013a0010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x000052a0, /* EMC_CFG_PIPE */
@@ -7470,21 +7671,24 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x00000895, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0xe0120069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000941, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200008, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1440,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_600000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_600000_01_V5.0.6_V0.8", /* DVFS table version */
                600000,     /* SDRAM frequency */
-               910,        /* min voltage */
+               920,        /* min voltage */
                900,        /* gpu min voltage */
                "pllc_out0", /* clock source id */
                0x20000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000001a, /* EMC_RC */
@@ -7510,7 +7714,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x0000000b, /* EMC_EINPUT_DURATION */
                        0x00070000, /* EMC_PUTERM_EXTRA */
                        0x00000003, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -7629,9 +7832,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x01280010, /* EMC_MRS_WAIT_CNT */
                        0x01280010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000003, /* EMC_CTT_DURATION */
                        0x000040a0, /* EMC_CFG_PIPE */
@@ -7696,22 +7896,24 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x0000089d, /* EMC_CFG_2 */
                0x00040008, /* EMC_SEL_DPD_CTRL */
                0xe00e0069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000b61, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200010, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1440,       /* expected dvfs latency (ns) */
-
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_792000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_792000_01_V5.0.6_V0.8", /* DVFS table version */
                792000,     /* SDRAM frequency */
                1000,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000023, /* EMC_RC */
@@ -7737,7 +7939,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x0000000d, /* EMC_EINPUT_DURATION */
                        0x00080000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -7856,9 +8057,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000100, /* EMC_ZCAL_WAIT_CNT */
                        0x00f80010, /* EMC_MRS_WAIT_CNT */
                        0x00f80010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x000040a0, /* EMC_CFG_PIPE */
@@ -7923,21 +8121,24 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x0000089d, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
                0xe0070069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000d71, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200018, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1200,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_924000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_924000_01_V5.0.6_V0.8", /* DVFS table version */
                924000,     /* SDRAM frequency */
-               1100,       /* min voltage */
+               1010,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x00000029, /* EMC_RC */
@@ -7963,7 +8164,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x0000000f, /* EMC_EINPUT_DURATION */
                        0x000a0000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -8082,9 +8282,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000128, /* EMC_ZCAL_WAIT_CNT */
                        0x00ce0010, /* EMC_MRS_WAIT_CNT */
                        0x00ce0010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                        0x00000000, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x00004080, /* EMC_CFG_PIPE */
@@ -8149,21 +8346,24 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x0000089d, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
                0xe0040069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
                0x80000f15, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200020, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1180,       /* expected dvfs latency (ns) */
        },
        {
-               0x16,       /* NoRegCalcVersion */
-               "01_1056000_01_NoRegCalcVersion_V0.4", /* DVFS table version */
+               0x18,       /* V5.0.6 */
+               "03_1056000_01_V5.0.6_V0.8", /* DVFS table version */
                1056000,    /* SDRAM frequency */
                1100,       /* min voltage */
                1100,       /* gpu min voltage */
                "pllm_ud",  /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
-               168,        /* number of burst_regs */
+               164,        /* number of burst_regs */
                31,         /* number of up_down_regs */
                {
                        0x0000002f, /* EMC_RC */
@@ -8182,14 +8382,13 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000000, /* EMC_WEXT */
                        0x00000007, /* EMC_WDV */
                        0x00000007, /* EMC_WDV_MASK */
-                       0x0000000e, /* EMC_QUSE */
+                       0x0000000d, /* EMC_QUSE */
                        0x00000002, /* EMC_QUSE_WIDTH */
                        0x00000000, /* EMC_IBDLY */
                        0x00000002, /* EMC_EINPUT */
                        0x00000010, /* EMC_EINPUT_DURATION */
                        0x000b0000, /* EMC_PUTERM_EXTRA */
                        0x00000004, /* EMC_PUTERM_WIDTH */
-                       0x00000000, /* EMC_BGBIAS_CTL0 */
                        0x00000000, /* EMC_PUTERM_ADJ */
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000000, /* EMC_CDB_CNTL_2 */
@@ -8217,28 +8416,28 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x0000000b, /* EMC_TCLKSTABLE */
                        0x0000000b, /* EMC_TCLKSTOP */
                        0x0000202d, /* EMC_TREFBW */
-                       0x00000000, /* EMC_FBIO_CFG6 */
+                       0x00000002, /* EMC_FBIO_CFG6 */
                        0x00000000, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
                        0x1040b8d8, /* EMC_FBIO_CFG5 */
                        0xd00100b1, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS0 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS1 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS2 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS3 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS4 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS5 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS6 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS7 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS8 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS9 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS10 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS11 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS12 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS13 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS14 */
-                       0x007f400a, /* EMC_DLL_XFORM_DQS15 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS1 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS2 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS8 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS9 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS10 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS11 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS12 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS13 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS14 */
+                       0x00000004, /* EMC_DLL_XFORM_DQS15 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE1 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -8277,14 +8476,14 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-                       0x007fc00c, /* EMC_DLL_XFORM_DQ0 */
-                       0x007fc00c, /* EMC_DLL_XFORM_DQ1 */
-                       0x007fc00c, /* EMC_DLL_XFORM_DQ2 */
-                       0x007fc00c, /* EMC_DLL_XFORM_DQ3 */
-                       0x0007fc0c, /* EMC_DLL_XFORM_DQ4 */
-                       0x0007fc0c, /* EMC_DLL_XFORM_DQ5 */
-                       0x0007fc0c, /* EMC_DLL_XFORM_DQ6 */
-                       0x0007fc0c, /* EMC_DLL_XFORM_DQ7 */
+                       0x00000008, /* EMC_DLL_XFORM_DQ0 */
+                       0x00000008, /* EMC_DLL_XFORM_DQ1 */
+                       0x00000008, /* EMC_DLL_XFORM_DQ2 */
+                       0x00000008, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000008, /* EMC_DLL_XFORM_DQ4 */
+                       0x00000008, /* EMC_DLL_XFORM_DQ5 */
+                       0x00000008, /* EMC_DLL_XFORM_DQ6 */
+                       0x00000008, /* EMC_DLL_XFORM_DQ7 */
                        0x100002a0, /* EMC_XM2CMDPADCTRL */
                        0x00000000, /* EMC_XM2CMDPADCTRL4 */
                        0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -8297,10 +8496,10 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x07070004, /* EMC_XM2VTTGENPADCTRL */
                        0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
                        0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-                       0x5d75d720, /* EMC_XM2DQSPADCTRL3 */
-                       0x00555555, /* EMC_XM2DQSPADCTRL4 */
-                       0x00555555, /* EMC_XM2DQSPADCTRL5 */
-                       0x5d75d700, /* EMC_XM2DQSPADCTRL6 */
+                       0x4d34d320, /* EMC_XM2DQSPADCTRL3 */
+                       0x00451451, /* EMC_XM2DQSPADCTRL4 */
+                       0x00451451, /* EMC_XM2DQSPADCTRL5 */
+                       0x4d34d320, /* EMC_XM2DQSPADCTRL6 */
                        0x0606003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x00000000, /* EMC_FBIO_SPARE */
@@ -8308,9 +8507,6 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                        0x00000152, /* EMC_ZCAL_WAIT_CNT */
                        0x00a30010, /* EMC_MRS_WAIT_CNT */
                        0x00a30010, /* EMC_MRS_WAIT_CNT2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-                       0xa1430606, /* EMC_AUTO_CAL_CONFIG */
                        0x0000000a, /* EMC_CTT */
                        0x00000004, /* EMC_CTT_DURATION */
                        0x00000000, /* EMC_CFG_PIPE */
@@ -8375,24 +8571,6108 @@ static struct tegra12_emc_table thor_195_b00_emc_table[] = {
                0x000008a5, /* EMC_CFG_2 */
                0x00040000, /* EMC_SEL_DPD_CTRL */
                0xd0010069, /* EMC_CFG_DIG_DLL */
+               0x00000000, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430606, /* EMC_AUTO_CAL_CONFIG */
                0x80000125, /* Mode Register 0 */
                0x80100002, /* Mode Register 1 */
                0x80200028, /* Mode Register 2 */
                0x00000000, /* Mode Register 4 */
-               1180,       /* expected dvfs latency (ns) */
        },
 };
-static struct tegra12_emc_pdata loki_a02_emc_pdata = {
-       .description = "loki_a02_emc_tables",
-       .tables = loki_a02_emc_table,
-       .num_tables = ARRAY_SIZE(loki_a02_emc_table),
+
+static struct tegra12_emc_table loki_ffd_sku0_emc_table[] = {
+       {
+               0x18,       /* V5.0.9 */
+               "05_12750_01_V5.0.9_V0.8", /* DVFS table version */
+               12750,      /* SDRAM frequency */
+               800,        /* min voltage */
+               800,        /* gpu min voltage */
+               "pllp_out0", /* clock source id */
+               0x4000003e, /* CLK_SOURCE_EMC */
+               164,        /* number of burst_regs */
+               31,         /* number of up_down_regs */
+               {
+                       0x00000000, /* EMC_RC */
+                       0x00000003, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000000, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000003, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000006, /* EMC_WDV */
+                       0x00000006, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000002, /* EMC_QUSE_WIDTH */
+                       0x00000000, /* EMC_IBDLY */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000005, /* EMC_EINPUT_DURATION */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000003, /* EMC_PUTERM_WIDTH */
+                       0x00000000, /* EMC_PUTERM_ADJ */
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000000, /* EMC_CDB_CNTL_3 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x0000000d, /* EMC_RDV */
+                       0x0000000f, /* EMC_RDV_MASK */
+                       0x00000060, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000005, /* EMC_TXSR */
+                       0x00000005, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000005, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000000, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000005, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000064, /* EMC_TREFBW */
+                       0x00000000, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x1060a298, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR3 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR4 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+                       0x10000280, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
+                       0x0130b118, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL3 */
+                       0x77ffc081, /* EMC_XM2CLKPADCTRL */
+                       0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+                       0x51451400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
+                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
+                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000007, /* EMC_TXDSRVTTGEN */
+                       0x00000000, /* EMC_FBIO_SPARE */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x00110011, /* EMC_MRS_WAIT_CNT */
+                       0x00110011, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000003, /* EMC_CTT_DURATION */
+                       0x0000f2f3, /* EMC_CFG_PIPE */
+                       0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x0000000a, /* EMC_QPOP */
+                       0x40040001, /* MC_EMEM_ARB_CFG */
+                       0x8000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030203, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x77e30303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
+                       0x00000007, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+                       0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+                       0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+                       0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
+                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+                       0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000802, /* EMC_CTT_TERM_CTRL */
+               0x73240000, /* EMC_CFG */
+               0x000008c5, /* EMC_CFG_2 */
+               0x00040128, /* EMC_SEL_DPD_CTRL */
+               0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+       },
+       {
+               0x18,       /* V5.0.9 */
+               "05_20400_01_V5.0.9_V0.8", /* DVFS table version */
+               20400,      /* SDRAM frequency */
+               800,        /* min voltage */
+               800,        /* gpu min voltage */
+               "pllp_out0", /* clock source id */
+               0x40000026, /* CLK_SOURCE_EMC */
+               164,        /* number of burst_regs */
+               31,         /* number of up_down_regs */
+               {
+                       0x00000000, /* EMC_RC */
+                       0x00000005, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000000, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000003, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000006, /* EMC_WDV */
+                       0x00000006, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000002, /* EMC_QUSE_WIDTH */
+                       0x00000000, /* EMC_IBDLY */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000005, /* EMC_EINPUT_DURATION */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000003, /* EMC_PUTERM_WIDTH */
+                       0x00000000, /* EMC_PUTERM_ADJ */
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000000, /* EMC_CDB_CNTL_3 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x0000000d, /* EMC_RDV */
+                       0x0000000f, /* EMC_RDV_MASK */
+                       0x0000009a, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000006, /* EMC_TXSR */
+                       0x00000006, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000005, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000000, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000005, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x000000a0, /* EMC_TREFBW */
+                       0x00000000, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x1060a298, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR3 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR4 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+                       0x10000280, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
+                       0x0130b118, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL3 */
+                       0x77ffc081, /* EMC_XM2CLKPADCTRL */
+                       0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+                       0x51451400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
+                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
+                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x0000000b, /* EMC_TXDSRVTTGEN */
+                       0x00000000, /* EMC_FBIO_SPARE */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x00110011, /* EMC_MRS_WAIT_CNT */
+                       0x00110011, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000003, /* EMC_CTT_DURATION */
+                       0x0000f2f3, /* EMC_CFG_PIPE */
+                       0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x0000000a, /* EMC_QPOP */
+                       0x40020001, /* MC_EMEM_ARB_CFG */
+                       0x80000012, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030203, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x76230303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
+                       0x0000000a, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+                       0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+                       0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+                       0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
+                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+                       0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000802, /* EMC_CTT_TERM_CTRL */
+               0x73240000, /* EMC_CFG */
+               0x000008c5, /* EMC_CFG_2 */
+               0x00040128, /* EMC_SEL_DPD_CTRL */
+               0x002c0068, /* EMC_CFG_DIG_DLL */
+               0x00000008, /* EMC_BGBIAS_CTL0 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+               0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+               0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+       },
+       {
+               0x18,       /* V5.0.9 */
+               "05_40800_01_V5.0.9_V0.8", /* DVFS table version */
+               40800,      /* SDRAM frequency */
+               800,        /* min voltage */
+               800,        /* gpu min voltage */
+               "pllp_out0", /* clock source id */
+               0x40000012, /* CLK_SOURCE_EMC */
+               164,        /* number of burst_regs */
+               31,         /* number of up_down_regs */
+               {
+                       0x00000001, /* EMC_RC */
+                       0x0000000a, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000001, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000003, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000006, /* EMC_WDV */
+                       0x00000006, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000002, /* EMC_QUSE_WIDTH */
+                       0x00000000, /* EMC_IBDLY */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000005, /* EMC_EINPUT_DURATION */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000003, /* EMC_PUTERM_WIDTH */
+                       0x00000000, /* EMC_PUTERM_ADJ */
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000000, /* EMC_CDB_CNTL_3 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x0000000d, /* EMC_RDV */
+                       0x0000000f, /* EMC_RDV_MASK */
+                       0x00000134, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000008, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x0000000c, /* EMC_TXSR */
+                       0x0000000c, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000005, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000000, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000005, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x0000013f, /* EMC_TREFBW */
+                       0x00000000, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x1060a298, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00064000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS8 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS9 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS10 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS11 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS12 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS13 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS14 */
+                       0x00064000, /* EMC_DLL_XFORM_DQS15 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR3 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR4 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+                       0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+                       0x10000280, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x00111111, /* EMC_XM2CMDPADCTRL5 */
+                       0x0130b118, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL3 */
+                       0x77ffc081, /* EMC_XM2CLKPADCTRL */
+                       0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x07070004, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+                       0x51451400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00514514, /* EMC_XM2DQSPADCTRL4 */
+                       0x00514514, /* EMC_XM2DQSPADCTRL5 */
+                       0x51451400, /* EMC_XM2DQSPADCTRL6 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000015, /* EMC_TXDSRVTTGEN */
+                       0x00000000, /* EMC_FBIO_SPARE */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x00110011, /* EMC_MRS_WAIT_CNT */
+                       0x00110011, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000003, /* EMC_CTT_DURATION */
+                       0x0000f2f3, /* EMC_CFG_PIPE */
+                       0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x0000000a, /* EMC_QPOP */
+                       0xa0000001, /* MC_EMEM_ARB_CFG */
+                       0x80000017, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030203, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x74a30303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
+                       0x00000014, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+                       0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+                       0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+                       0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
+                       0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+                       0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+               },
+               0x00000042, /*&nb