ARM: tegra11x: Define ncpu residency for 2 clusters
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-power.c
index 61ae931..fe6084a 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/board-dalmore-power.c
  *
- * Copyright (C) 2012 NVIDIA Corporation.
+ * Copyright (C) 2012-2013 NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -38,7 +38,6 @@
 #include <asm/mach-types.h>
 #include <linux/power/sbs-battery.h>
 
-#include <mach/iomap.h>
 #include <mach/irqs.h>
 #include <mach/edp.h>
 #include <mach/gpio-tegra.h>
 #include "tegra-board-id.h"
 #include "board.h"
 #include "gpio-names.h"
+#include "board-common.h"
 #include "board-dalmore.h"
 #include "tegra_cl_dvfs.h"
 #include "devices.h"
 #include "tegra11_soctherm.h"
+#include "iomap.h"
+#include "tegra3_tsensor.h"
 
 #define PMC_CTRL               0x0
 #define PMC_CTRL_INTR_LOW      (1 << 17)
@@ -204,7 +206,7 @@ static struct regulator_consumer_supply max77663_sd2_supply[] = {
        REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
        REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
        REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
-       REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
+       REGULATOR_SUPPLY("vddio_cam", "vi"),
        REGULATOR_SUPPLY("pwrdet_cam", NULL),
        REGULATOR_SUPPLY("avdd_osc", NULL),
        REGULATOR_SUPPLY("vddio_sys", NULL),
@@ -252,7 +254,7 @@ static struct regulator_consumer_supply max77663_ldo0_supply[] = {
        REGULATOR_SUPPLY("avdd_pllu", NULL),
        REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
        REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
-       REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
+       REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
 };
 
 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
@@ -279,9 +281,10 @@ static struct regulator_consumer_supply max77663_ldo4_supply[] = {
 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
        REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
        REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
-       REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
+       REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
        REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
        REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
+       REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
        REGULATOR_SUPPLY("pwrdet_mipi", NULL),
        REGULATOR_SUPPLY("vddio_bb_hsic", NULL),
 };
@@ -563,11 +566,12 @@ static struct regulator_consumer_supply palmas_smps8_supply[] = {
        REGULATOR_SUPPLY("avdd_plle", NULL),
        REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
        REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
-       REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
+       REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
        REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
        REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
        REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
-
+       REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
+       REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
 };
 
 static struct regulator_consumer_supply palmas_smps9_supply[] = {
@@ -594,6 +598,7 @@ static struct regulator_consumer_supply palmas_ldo7_supply[] = {
 
 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
        REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
+       REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
 };
 
 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
@@ -818,6 +823,7 @@ static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = {
 /* EN_USB3_VBUS From TEGRA GPIO PM5 */
 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
        REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
+       REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
 };
 
 /* EN_1V8_TS From TEGRA_GPIO_PH5 */
@@ -986,8 +992,8 @@ static struct tegra_suspend_platform_data dalmore_suspend_data = {
        .core_off_timer = 2000,
        .corereq_high   = true,
        .sysclkreq_high = true,
-       .min_residency_noncpu = 600,
-       .min_residency_crail = 1000,
+       .cpu_lp2_min_residency = 1000,
+       .min_residency_crail = 20000,
 };
 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
 /* board parameters for cpu dfll */
@@ -1170,69 +1176,88 @@ int __init dalmore_edp_init(void)
        return 0;
 }
 
+static struct tegra_tsensor_pmu_data tpdata_palmas = {
+       .reset_tegra = 1,
+       .pmu_16bit_ops = 0,
+       .controller_type = 0,
+       .pmu_i2c_addr = 0x58,
+       .i2c_controller_id = 4,
+       .poweroff_reg_addr = 0xa0,
+       .poweroff_reg_data = 0x0,
+};
+
+static struct tegra_tsensor_pmu_data tpdata_max77663 = {
+       .reset_tegra = 1,
+       .pmu_16bit_ops = 0,
+       .controller_type = 0,
+       .pmu_i2c_addr = 0x3c,
+       .i2c_controller_id = 4,
+       .poweroff_reg_addr = 0x41,
+       .poweroff_reg_data = 0x80,
+};
+
 static struct soctherm_platform_data dalmore_soctherm_data = {
-       .soctherm_clk_rate = 136000000,
-       .tsensor_clk_rate = 500000,
-       .sensor_data = {
-               [TSENSE_CPU0] = {
-                       .enable = true,
-                       .tall = 16300,
-                       .tiddq = 1,
-                       .ten_count = 1,
-                       .tsample = 163,
-                       .pdiv = 10,
-               },
-               [TSENSE_CPU1] = {
-                       .enable = true,
-                       .tall = 16300,
-                       .tiddq = 1,
-                       .ten_count = 1,
-                       .tsample = 163,
-                       .pdiv = 10,
-               },
-               [TSENSE_CPU2] = {
-                       .enable = true,
-                       .tall = 16300,
-                       .tiddq = 1,
-                       .ten_count = 1,
-                       .tsample = 163,
-                       .pdiv = 10,
-               },
-               [TSENSE_CPU3] = {
-                       .enable = true,
-                       .tall = 16300,
-                       .tiddq = 1,
-                       .ten_count = 1,
-                       .tsample = 163,
-                       .pdiv = 10,
+       .therm = {
+               [THERM_CPU] = {
+                       .zone_enable = true,
+                       .passive_delay = 1000,
+                       .num_trips = 3,
+                       .trips = {
+                               {
+                                       .cdev_type = "tegra-balanced",
+                                       .trip_temp = 84000,
+                                       .trip_type = THERMAL_TRIP_PASSIVE,
+                                       .upper = THERMAL_NO_LIMIT,
+                                       .lower = THERMAL_NO_LIMIT,
+                               },
+                               {
+                                       .cdev_type = "tegra-heavy",
+                                       .trip_temp = 94000,
+                                       .trip_type = THERMAL_TRIP_HOT,
+                                       .upper = THERMAL_NO_LIMIT,
+                                       .lower = THERMAL_NO_LIMIT,
+                               },
+                               {
+                                       .cdev_type = "tegra-shutdown",
+                                       .trip_temp = 104000,
+                                       .trip_type = THERMAL_TRIP_CRITICAL,
+                                       .upper = THERMAL_NO_LIMIT,
+                                       .lower = THERMAL_NO_LIMIT,
+                               },
+                       },
                },
-               /* MEM0/MEM1 won't be used */
-               [TSENSE_MEM0] = {
-                       .enable = false,
+               [THERM_GPU] = {
+                       .zone_enable = true,
                },
-               [TSENSE_MEM1] = {
-                       .enable = false,
+               [THERM_PLL] = {
+                       .zone_enable = true,
                },
-               [TSENSE_GPU] = {
-                       .enable = true,
-                       .tall = 16300,
-                       .tiddq = 1,
-                       .ten_count = 1,
-                       .tsample = 163,
-                       .pdiv = 10,
-               },
-               [TSENSE_PLLX] = {
-                       .enable = true,
-                       .tall = 16300,
-                       .tiddq = 1,
-                       .ten_count = 1,
-                       .tsample = 163,
-                       .pdiv = 10,
+       },
+       .throttle = {
+               [THROTTLE_HEAVY] = {
+                       .devs = {
+                               [THROTTLE_DEV_CPU] = {
+                                       .enable = 1,
+                               },
+                       },
                },
        },
+       .tshut_pmu_trip_data = &tpdata_palmas,
 };
 
 int __init dalmore_soctherm_init(void)
 {
+       struct board_info board_info;
+
+       tegra_get_board_info(&board_info);
+       if (!(board_info.board_id == BOARD_E1611 ||
+               board_info.board_id == BOARD_P2454))
+               dalmore_soctherm_data.tshut_pmu_trip_data = &tpdata_max77663;
+
+       tegra_platform_edp_init(dalmore_soctherm_data.therm[THERM_CPU].trips,
+                       &dalmore_soctherm_data.therm[THERM_CPU].num_trips);
+       tegra_add_tj_trips(dalmore_soctherm_data.therm[THERM_CPU].trips,
+                       &dalmore_soctherm_data.therm[THERM_CPU].num_trips);
+
        return tegra11_soctherm_init(&dalmore_soctherm_data);
 }