ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-common.c
index 6da3af3..c259533 100644 (file)
@@ -2,7 +2,7 @@
  * board-common.c: Implement function which is common across
  * different boards.
  *
- * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
 
 #include <linux/clk.h>
 #include <linux/serial_8250.h>
+#include <linux/clk/tegra.h>
 
-#include <mach/clk.h>
+#include <mach/edp.h>
 
 #include "board.h"
 #include "board-common.h"
 #include "devices.h"
 #include "clock.h"
+#include "dvfs.h"
+#include "cpu-tegra.h"
 
 extern unsigned long  debug_uart_port_base;
 extern struct clk *debug_uart_clk;
@@ -70,7 +73,7 @@ int uart_console_debug_init(int default_debug_port)
        case 1:
                /* UARTB is the debug port. */
                pr_info("Selecting UARTB as the debug console\n");
-               debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
+               debug_uart_clk =  clk_get_sys("serial8250.1", "uartb");
                debug_uart_port_base = ((struct plat_serial8250_port *)(
                        debug_uartb_device.dev.platform_data))->mapbase;
                uart_console_debug_device = &debug_uartb_device;
@@ -79,7 +82,7 @@ int uart_console_debug_init(int default_debug_port)
        case 2:
                /* UARTC is the debug port. */
                pr_info("Selecting UARTC as the debug console\n");
-               debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
+               debug_uart_clk =  clk_get_sys("serial8250.2", "uartc");
                debug_uart_port_base = ((struct plat_serial8250_port *)(
                        debug_uartc_device.dev.platform_data))->mapbase;
                uart_console_debug_device = &debug_uartc_device;
@@ -88,7 +91,7 @@ int uart_console_debug_init(int default_debug_port)
        case 3:
                /* UARTD is the debug port. */
                pr_info("Selecting UARTD as the debug console\n");
-               debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
+               debug_uart_clk =  clk_get_sys("serial8250.3", "uartd");
                debug_uart_port_base = ((struct plat_serial8250_port *)(
                        debug_uartd_device.dev.platform_data))->mapbase;
                uart_console_debug_device = &debug_uartd_device;
@@ -98,7 +101,7 @@ int uart_console_debug_init(int default_debug_port)
        case 4:
                /* UARTE is the debug port. */
                pr_info("Selecting UARTE as the debug console\n");
-               debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
+               debug_uart_clk =  clk_get_sys("serial8250.4", "uarte");
                debug_uart_port_base = ((struct plat_serial8250_port *)(
                        debug_uarte_device.dev.platform_data))->mapbase;
                uart_console_debug_device = &debug_uarte_device;
@@ -116,8 +119,10 @@ int uart_console_debug_init(int default_debug_port)
 
        if (!IS_ERR_OR_NULL(debug_uart_clk)) {
                struct clk *c;
+#ifndef CONFIG_COMMON_CLK
                pr_info("The debug console clock name is %s\n",
                                                debug_uart_clk->name);
+#endif
                c = tegra_get_clock_by_name("pll_p");
                if (IS_ERR_OR_NULL(c))
                        pr_err("Not getting the parent clock pll_p\n");
@@ -132,3 +137,83 @@ int uart_console_debug_init(int default_debug_port)
        }
        return debug_port_id;
 }
+
+static void tegra_add_trip_points(struct thermal_trip_info *trips,
+                               int *num_trips,
+                               struct tegra_cooling_device *cdev_data)
+{
+       int i;
+       struct thermal_trip_info *trip_state;
+
+       if (!trips || !num_trips || !cdev_data)
+               return;
+
+       if (*num_trips + cdev_data->trip_temperatures_num > THERMAL_MAX_TRIPS) {
+               WARN(1, "%s: cooling device %s has too many trips\n",
+                    __func__, cdev_data->cdev_type);
+               return;
+       }
+
+       for (i = 0; i < cdev_data->trip_temperatures_num; i++) {
+               trip_state = &trips[*num_trips];
+
+               trip_state->cdev_type = cdev_data->cdev_type;
+               trip_state->trip_temp = cdev_data->trip_temperatures[i] * 1000;
+               trip_state->trip_type = THERMAL_TRIP_ACTIVE;
+               trip_state->upper = trip_state->lower = i + 1;
+               trip_state->hysteresis = 1000;
+
+               (*num_trips)++;
+       }
+}
+
+void tegra_add_all_vmin_trips(struct thermal_trip_info *trips, int *num_trips)
+{
+       tegra_add_trip_points(trips, num_trips, tegra_dvfs_get_cpu_vmin_cdev());
+       tegra_add_trip_points(trips, num_trips,
+                             tegra_dvfs_get_core_vmin_cdev());
+       tegra_add_trip_points(trips, num_trips, tegra_dvfs_get_gpu_vmin_cdev());
+}
+
+void tegra_add_cpu_vmin_trips(struct thermal_trip_info *trips, int *num_trips)
+{
+       tegra_add_trip_points(trips, num_trips,
+                                       tegra_dvfs_get_cpu_vmin_cdev());
+}
+
+void tegra_add_gpu_vmin_trips(struct thermal_trip_info *trips, int *num_trips)
+{
+       tegra_add_trip_points(trips, num_trips,
+                                       tegra_dvfs_get_gpu_vmin_cdev());
+}
+
+void tegra_add_core_vmin_trips(struct thermal_trip_info *trips, int *num_trips)
+{
+       tegra_add_trip_points(trips, num_trips,
+                                       tegra_dvfs_get_core_vmin_cdev());
+}
+
+void tegra_add_cpu_vmax_trips(struct thermal_trip_info *trips, int *num_trips)
+{
+       tegra_add_trip_points(trips, num_trips, tegra_dvfs_get_cpu_vmax_cdev());
+}
+
+void tegra_add_core_edp_trips(struct thermal_trip_info *trips, int *num_trips)
+{
+       tegra_add_trip_points(trips, num_trips, tegra_core_edp_get_cdev());
+}
+
+void tegra_add_tgpu_trips(struct thermal_trip_info *trips, int *num_trips)
+{
+       tegra_add_trip_points(trips, num_trips, tegra_dvfs_get_gpu_vts_cdev());
+}
+
+void tegra_add_vc_trips(struct thermal_trip_info *trips, int *num_trips)
+{
+       tegra_add_trip_points(trips, num_trips, tegra_vc_get_cdev());
+}
+void tegra_add_core_vmax_trips(struct thermal_trip_info *trips, int *num_trips)
+{
+       tegra_add_trip_points(trips, num_trips,
+                             tegra_dvfs_get_core_vmax_cdev());
+}