ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-sdhci.c
index 35d84a8..80ea1e8 100644 (file)
@@ -27,6 +27,7 @@
 #include <linux/wl12xx.h>
 #include <linux/platform_data/mmc-sdhci-tegra.h>
 #include <linux/mfd/max77660/max77660-core.h>
+#include <linux/tegra-fuse.h>
 
 #include <asm/mach-types.h>
 #include <mach/irqs.h>
@@ -50,6 +51,7 @@ static unsigned int wifi_states[] = {ON, OFF};
 
 #define ARDBEG_SD_CD   TEGRA_GPIO_PV2
 #define ARDBEG_SD_WP   TEGRA_GPIO_PQ4
+#define FUSE_SOC_SPEEDO_0      0x134
 
 static void (*wifi_status_cb)(int card_present, void *dev_id);
 static void *wifi_status_cb_devid;
@@ -206,7 +208,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .power_gpio = -1,
        .is_8bit = 1,
        .tap_delay = 0x4,
-       .trim_delay = 0x4,
+       .trim_delay = 0x3,
        .ddr_trim_delay = 0x0,
        .mmc_data = {
                .built_in = 1,
@@ -384,7 +386,8 @@ static int __init ardbeg_wifi_prepower(void)
                !of_machine_is_compatible("nvidia,laguna") &&
                !of_machine_is_compatible("nvidia,ardbeg_sata") &&
                !of_machine_is_compatible("nvidia,tn8") &&
-               !of_machine_is_compatible("nvidia,norrin"))
+               !of_machine_is_compatible("nvidia,norrin") &&
+               !of_machine_is_compatible("nvidia,jetson-tk1"))
                return 0;
        ardbeg_wifi_power(1);
 
@@ -399,6 +402,7 @@ int __init ardbeg_sdhci_init(void)
        int nominal_core_mv;
        int min_vcore_override_mv;
        int boot_vcore_mv;
+       u32 speedo;
        struct board_info board_info;
 
        nominal_core_mv =
@@ -425,7 +429,8 @@ int __init ardbeg_sdhci_init(void)
                tegra_sdhci_platform_data3.boot_vcore_mv = boot_vcore_mv;
        }
 
-       if (of_machine_is_compatible("nvidia,laguna"))
+       if (of_machine_is_compatible("nvidia,laguna") ||
+           of_machine_is_compatible("nvidia,jetson-tk1"))
                tegra_sdhci_platform_data2.wp_gpio = ARDBEG_SD_WP;
 
        tegra_get_board_info(&board_info);
@@ -443,10 +448,32 @@ int __init ardbeg_sdhci_init(void)
                board_info.board_id == BOARD_PM359)
                        tegra_sdhci_platform_data0.disable_clock_gate = 1;
 
+       /*
+        * FIXME: Set max clk limit to 200MHz for SDMMC3 for PM375.
+        * Requesting 208MHz results in getting 204MHz from PLL_P
+        * and CRC errors are seen with same.
+        */
+       if (board_info.board_id == BOARD_PM375)
+               tegra_sdhci_platform_data2.max_clk_limit = 200000000;
+
+       speedo = tegra_fuse_readl(FUSE_SOC_SPEEDO_0);
+       tegra_sdhci_platform_data0.cpu_speedo = speedo;
+       tegra_sdhci_platform_data2.cpu_speedo = speedo;
+       tegra_sdhci_platform_data3.cpu_speedo = speedo;
+
+       speedo = tegra_fuse_readl(FUSE_SOC_SPEEDO_0);
+       tegra_sdhci_platform_data0.cpu_speedo = speedo;
+       tegra_sdhci_platform_data2.cpu_speedo = speedo;
+       tegra_sdhci_platform_data3.cpu_speedo = speedo;
+
        platform_device_register(&tegra_sdhci_device3);
        platform_device_register(&tegra_sdhci_device2);
-       platform_device_register(&tegra_sdhci_device0);
-       ardbeg_wifi_init();
+       if (board_info.board_id != BOARD_PM359 &&
+                       board_info.board_id != BOARD_PM375 &&
+                       board_info.board_id != BOARD_PM377) {
+               platform_device_register(&tegra_sdhci_device0);
+               ardbeg_wifi_init();
+       }
 
        return 0;
 }