#include <linux/edp.h>
#include <linux/platform_data/tegra_edp.h>
#include <linux/pid_thermal_gov.h>
-#include <mach/hardware.h>
#include <linux/regulator/fixed.h>
#include <linux/mfd/palmas.h>
-#include <linux/mfd/as3722-reg.h>
#include <linux/mfd/as3722-plat.h>
+#include <linux/power/power_supply_extcon.h>
#include <linux/regulator/tps51632-regulator.h>
#include <linux/regulator/machine.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/regulator/tegra-dfll-bypass-regulator.h>
+#include <linux/power/bq2471x-charger.h>
+#include <linux/power/bq2477x-charger.h>
+#include <linux/tegra-fuse.h>
#include <asm/mach-types.h>
+#include <mach/pinmux-t12.h>
#include "pm.h"
#include "dvfs.h"
#include "board-pmu-defines.h"
#include "devices.h"
#include "iomap.h"
-#include "tegra-board-id.h"
#include "tegra_cl_dvfs.h"
#include "tegra11_soctherm.h"
#include "tegra3_tsensor.h"
+#define E1735_EMULATE_E1767_SKU 1001
+
#define PMC_CTRL 0x0
#define PMC_CTRL_INTR_LOW (1 << 17)
REGULATOR_SUPPLY("vif", "2-0036"),
REGULATOR_SUPPLY("vdd_i2c", "2-000c"),
REGULATOR_SUPPLY("vi2c", "2-0030"),
-
+ REGULATOR_SUPPLY("vif2", "2-0021"),
+ REGULATOR_SUPPLY("dovdd", "2-0010"),
+ REGULATOR_SUPPLY("vdd", "2-004a"),
+ REGULATOR_SUPPLY("vif", "2-0048"),
};
static struct regulator_consumer_supply as3722_ldo2_supply[] = {
REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
- REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
+ REGULATOR_SUPPLY("avdd_dsi_csi", "vi.0"),
+ REGULATOR_SUPPLY("avdd_dsi_csi", "vi.1"),
REGULATOR_SUPPLY("pwrdet_mipi", NULL),
REGULATOR_SUPPLY("avdd_hsic_com", NULL),
REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
REGULATOR_SUPPLY("avdd_cam3_cam", NULL),
REGULATOR_SUPPLY("vana", "2-0010"),
- REGULATOR_SUPPLY("vana", "2-0036"),
+ REGULATOR_SUPPLY("avdd_ov5693", "2-0010"),
};
static struct regulator_consumer_supply as3722_ldo5_supply[] = {
static struct regulator_consumer_supply as3722_ldo7_supply[] = {
REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
REGULATOR_SUPPLY("imx135_reg2", NULL),
+ REGULATOR_SUPPLY("vdig_lv", "2-0010"),
+ REGULATOR_SUPPLY("dvdd", "2-0010"),
};
static struct regulator_consumer_supply as3722_ldo9_supply[] = {
REGULATOR_SUPPLY("imx135_reg1", NULL),
REGULATOR_SUPPLY("vdd", "2-000c"),
REGULATOR_SUPPLY("vin", "2-0030"),
+ REGULATOR_SUPPLY("vana", "2-0036"),
+ REGULATOR_SUPPLY("vana", "2-0021"),
+ REGULATOR_SUPPLY("vdd_af1", "2-0010"),
+ REGULATOR_SUPPLY("vin", "2-004a"),
+ REGULATOR_SUPPLY("vana", "2-0048"),
};
static struct regulator_consumer_supply as3722_ldo11_supply[] = {
static struct regulator_consumer_supply as3722_sd4_supply[] = {
REGULATOR_SUPPLY("avdd_hdmi","tegradc.1"),
REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
- REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
REGULATOR_SUPPLY("avdd_pex_pll", "tegra-pcie"),
REGULATOR_SUPPLY("avddio_pex", "tegra-pcie"),
REGULATOR_SUPPLY("dvddio_pex", "tegra-pcie"),
REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
+ REGULATOR_SUPPLY("vddio_pex_sata", "tegra-sata.0"),
};
static struct regulator_consumer_supply as3722_sd5_supply[] = {
REGULATOR_SUPPLY("vddio_cam", "vi"),
REGULATOR_SUPPLY("pwrdet_cam", NULL),
REGULATOR_SUPPLY("dvdd", "spi0.0"),
- REGULATOR_SUPPLY("vlogic", "0-0069"),
- REGULATOR_SUPPLY("vid", "0-000c"),
- REGULATOR_SUPPLY("vddio", "0-0077"),
+ REGULATOR_SUPPLY("vlogic", "0-0069"),
+ REGULATOR_SUPPLY("vid", "0-000c"),
+ REGULATOR_SUPPLY("vddio", "0-0077"),
+ REGULATOR_SUPPLY("vdd_sata", "tegra-sata.0"),
+ REGULATOR_SUPPLY("avdd_sata", "tegra-sata.0"),
+ REGULATOR_SUPPLY("avdd_sata_pll", "tegra-sata.0"),
};
static struct regulator_consumer_supply as3722_sd6_supply[] = {
};
-AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1, 2);
-AMS_PDATA_INIT(sd1, NULL, 700000, 1400000, 1, 1, 1, 1);
+AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE2);
+AMS_PDATA_INIT(sd1, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 0, 1, 1, 0);
AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
-AMS_PDATA_INIT(sd6, NULL, 700000, 1400000, 1, 1, 0, 0);
-AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, 1);
+AMS_PDATA_INIT(sd6, NULL, 650000, 1400000, 0, 1, 0, 0);
+AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
AMS_PDATA_INIT(ldo3, NULL, 800000, 800000, 1, 1, 1, 0);
AMS_PDATA_INIT(ldo10, NULL, 2700000, 2700000, 0, 0, 1, 0);
AMS_PDATA_INIT(ldo11, NULL, 1800000, 1800000, 0, 0, 1, 0);
-/* config settings are OTP plus initial state
- * GPIOsignal_out at 20h not configurable through OTP and is initialized to
- * zero. To enable output, the invert bit must be turned on.
- * GPIOxcontrol register format
- * bit(s) bitname
- * ---------------------
- * 7 gpiox_invert invert input or output
- * 6:3 gpiox_iosf 0: normal
- * 2:0 gpiox_mode 0: input, 1: output push/pull, 3: ADC input (tristate)
- *
- * Examples:
- * otp meaning
- * ------------
- * 0x3 gpiox_invert=0(no invert), gpiox_iosf=0(normal), gpiox_mode=3(ADC input)
- * 0x81 gpiox_invert=1(invert), gpiox_iosf=0(normal), gpiox_mode=1(output)
- *
- * Note: output state should be defined for gpiox_mode = output. Do not change
- * the state of the invert bit for critical devices such as GPIO 7 which enables
- * SDRAM. Driver applies invert mask to output state to configure GPIOsignal_out
- * register correctly.
- * E.g. Invert = 1, (requested) output state = 1 => GPIOsignal_out = 0
- */
-static struct as3722_gpio_config as3722_gpio_cfgs[] = {
- {
- /* otp = 0x3 IGPU_PRDGD*/
- .gpio = AS3722_GPIO0,
- .mode = AS3722_GPIO_MODE_OUTPUT_VDDL,
- },
- {
- /* otp = 0x1 => REGEN_3 = LP0 gate (1.8V, 5 V)*/
- .gpio = AS3722_GPIO1,
- .invert = AS3722_GPIO_CFG_NO_INVERT,
- .mode = AS3722_GPIO_MODE_OUTPUT_VDDH,
- .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
- },
- {
- /* otp = 0x3 PMU_REGEN1*/
- .gpio = AS3722_GPIO2,
- .invert = AS3722_GPIO_CFG_NO_INVERT, /* don't go into LP0 */
- .mode = AS3722_GPIO_MODE_OUTPUT_VDDH,
- .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
- },
- {
- /* otp = 0x03 AP THERMISTOR */
- .gpio = AS3722_GPIO3,
- .mode = AS3722_GPIO_MODE_ADC_IN,
- },
- {
- /* otp = 0x81 => on by default
- * gates EN_AVDD_LCD
- */
- .gpio = AS3722_GPIO4,
- .invert = AS3722_GPIO_CFG_NO_INVERT,
- .mode = AS3722_GPIO_MODE_OUTPUT_VDDH,
- .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
- },
- {
- /* otp = 0x3 CLK 23KHZ WIFI */
- .gpio = AS3722_GPIO5,
- .mode = AS3722_GPIO_MODE_OUTPUT_VDDL,
- .iosf = AS3722_GPIO_IOSF_Q32K_OUT,
- },
- {
- /* otp = 0x3 SKIN TEMP */
- .gpio = AS3722_GPIO6,
- .mode = AS3722_GPIO_MODE_ADC_IN,
- },
- {
- /* otp = 0x81 1.6V LP0*/
- .gpio = AS3722_GPIO7,
- .invert = AS3722_GPIO_CFG_INVERT,
- .mode = AS3722_GPIO_MODE_OUTPUT_VDDH,
- .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
- },
-};
-
-static struct as3722_rtc_platform_data as3722_rtc_pdata = {
- .enable_clk32k = 1,
+static struct as3722_pinctrl_platform_data as3722_pctrl_pdata[] = {
+ AS3722_PIN_CONTROL("gpio0", "gpio", "pull-down", NULL, NULL, "output-low"),
+ AS3722_PIN_CONTROL("gpio1", "gpio", NULL, NULL, NULL, "output-high"),
+ AS3722_PIN_CONTROL("gpio2", "gpio", NULL, NULL, NULL, "output-high"),
+ AS3722_PIN_CONTROL("gpio3", "gpio", NULL, NULL, "enabled", NULL),
+ AS3722_PIN_CONTROL("gpio4", "gpio", NULL, NULL, NULL, "output-high"),
+ AS3722_PIN_CONTROL("gpio5", "clk32k-out", "pull-down", NULL, NULL, NULL),
+ AS3722_PIN_CONTROL("gpio6", "gpio", NULL, NULL, "enabled", NULL),
+ AS3722_PIN_CONTROL("gpio7", "gpio", NULL, NULL, NULL, "output-low"),
};
static struct as3722_adc_extcon_platform_data as3722_adc_extcon_pdata = {
.reg_pdata[AS3722_LDO9] = &as3722_ldo9_reg_pdata,
.reg_pdata[AS3722_LDO10] = &as3722_ldo10_reg_pdata,
.reg_pdata[AS3722_LDO11] = &as3722_ldo11_reg_pdata,
- .core_init_data = NULL,
.gpio_base = AS3722_GPIO_BASE,
.irq_base = AS3722_IRQ_BASE,
.use_internal_int_pullup = 0,
.use_internal_i2c_pullup = 0,
- .num_gpio_cfgs = ARRAY_SIZE(as3722_gpio_cfgs),
- .gpio_cfgs = as3722_gpio_cfgs,
- .rtc_pdata = &as3722_rtc_pdata,
+ .pinctrl_pdata = as3722_pctrl_pdata,
+ .num_pinctrl = ARRAY_SIZE(as3722_pctrl_pdata),
+ .enable_clk32k_out = true,
.use_power_off = true,
- .enable_ldo3_tracking = true,
- .disabe_ldo3_tracking_suspend = true,
.extcon_pdata = &as3722_adc_extcon_pdata,
};
{
void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
u32 pmc_ctrl;
-
+ struct board_info board_info;
/* AS3722: Normal state of INT request line is LOW.
* configure the power management controller to trigger PMU
/* Set vdd_gpu init uV to 1V */
as3722_sd6_reg_idata.constraints.init_uV = 900000;
- as3722_sd6_reg_pdata.oc_configure_enable = true;
- as3722_sd6_reg_pdata.oc_trip_thres_perphase = 3500;
- as3722_sd6_reg_pdata.oc_alarm_thres_perphase = 0;
+ as3722_sd6_reg_idata.constraints.min_uA = 3500000;
+ as3722_sd6_reg_idata.constraints.max_uA = 3500000;
- as3722_sd0_reg_pdata.oc_configure_enable = true;
- as3722_sd0_reg_pdata.oc_trip_thres_perphase = 3500;
- as3722_sd0_reg_pdata.oc_alarm_thres_perphase = 0;
+ as3722_sd0_reg_idata.constraints.min_uA = 3500000;
+ as3722_sd0_reg_idata.constraints.max_uA = 3500000;
- as3722_sd1_reg_pdata.oc_configure_enable = true;
- as3722_sd1_reg_pdata.oc_trip_thres_perphase = 2500;
- as3722_sd1_reg_pdata.oc_alarm_thres_perphase = 0;
+ as3722_sd1_reg_idata.constraints.min_uA = 2500000;
+ as3722_sd1_reg_idata.constraints.max_uA = 2500000;
+
+ as3722_ldo3_reg_pdata.enable_tracking = true;
+ as3722_ldo3_reg_pdata.disable_tracking_suspend = true;
+
+ tegra_get_board_info(&board_info);
+ if (board_info.board_id == BOARD_E1792) {
+ /*Default DDR voltage is 1.35V but lpddr3 supports 1.2V*/
+ as3722_sd2_reg_idata.constraints.min_uV = 1200000;
+ as3722_sd2_reg_idata.constraints.max_uV = 1200000;
+ }
pr_info("%s: i2c_register_board_info\n", __func__);
i2c_register_board_info(4, as3722_regulators,
REGULATOR_SUPPLY("hvdd_pex", "tegra-pcie"),
REGULATOR_SUPPLY("hvdd_pex_pll_e", "tegra-pcie"),
REGULATOR_SUPPLY("vddio_pex_ctl", "tegra-pcie"),
+ REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
REGULATOR_SUPPLY("vdd", "0-0069"),
REGULATOR_SUPPLY("vdd", "0-0048"),
+ REGULATOR_SUPPLY("vdd", "stm8t143.2"),
REGULATOR_SUPPLY("vdd", "0-000c"),
REGULATOR_SUPPLY("vdd", "0-0077"),
+ REGULATOR_SUPPLY("hvdd_sata", "tegra-sata.0"),
};
-PALMAS_REGS_PDATA(ti913_smps123, 700, 1400, NULL, 1, 1, 1, NORMAL,
+PALMAS_REGS_PDATA(ti913_smps123, 650, 1400, NULL, 0, 1, 1, NORMAL,
0, 0, 0, 0, 0);
-PALMAS_REGS_PDATA(ti913_smps45, 900, 1400, NULL, 1, 1, 1, NORMAL,
+PALMAS_REGS_PDATA(ti913_smps45, 700, 1400, NULL, 1, 1, 1, NORMAL,
0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_smps6, 1800, 1800, NULL, 1, 1, 1, NORMAL,
0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_smps9, 1050, 1050, NULL, 0, 0, 0, NORMAL,
0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo1, 1050, 1250, palmas_rails(ti913_smps7),
- 1, 1, 1, 0, 0, 0, 0, 0, 0);
+ 1, 1, 1, 0, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo2, 1200, 1200, palmas_rails(ti913_smps6),
0, 0, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo3, 3100, 3100, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo5, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo6, 1800, 1800, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo7, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
-PALMAS_REGS_PDATA(ti913_ldo8, 1000, 1000, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldo8, 800, 800, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo9, 1800, 3300, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldoln, 1050, 1050, palmas_rails(ti913_smps6),
0, 0, 1, 0, 0, 0, 0, 0, 0);
-PALMAS_REGS_PDATA(ti913_ldousb, 1800, 1800, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldousb, 1800, 1800, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_regen1, 2800, 3300, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
#define PALMAS_REG_PDATA(_sname) ®_idata_##_sname
NULL,
PALMAS_REG_PDATA(ti913_smps9),
NULL,
+ NULL,
PALMAS_REG_PDATA(ti913_ldo1),
PALMAS_REG_PDATA(ti913_ldo2),
PALMAS_REG_PDATA(ti913_ldo3),
NULL,
PALMAS_REG_INIT_DATA(ti913_smps9),
NULL,
+ NULL,
PALMAS_REG_INIT_DATA(ti913_ldo1),
PALMAS_REG_INIT_DATA(ti913_ldo2),
PALMAS_REG_INIT_DATA(ti913_ldo3),
};
static struct palmas_pinctrl_config palmas_ti913_pincfg[] = {
- PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
- PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO0, ID, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO5, CLK32KGAUDIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
+ PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
+ PALMAS_PINMUX("vac", "vac", NULL, NULL),
+ PALMAS_PINMUX("gpio0", "id", "pull-up", NULL),
+ PALMAS_PINMUX("gpio1", "vbus_det", NULL, NULL),
+ PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
+ PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
+ PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
+ PALMAS_PINMUX("gpio5", "clk32kgaudio", NULL, NULL),
+ PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
+ PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
};
static struct palmas_pinctrl_platform_data palmas_ti913_pinctrl_pdata = {
void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
u32 pmc_ctrl;
int i;
+ struct board_info board_info;
/* TPS65913: Normal state of INT request line is LOW.
* configure the power management controller to trigger PMU
/* Tracking configuration */
reg_init_data_ti913_ldo8.config_flags =
- PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
- PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
+ PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE;
for (i = 0; i < PALMAS_NUM_REGS ; i++) {
pmic_ti913_platform.reg_data[i] = ardbeg_1735_reg_data[i];
/* Set vdd_gpu init uV to 1V */
reg_idata_ti913_smps123.constraints.init_uV = 900000;
+ tegra_get_board_info(&board_info);
+ if (board_info.board_id == BOARD_E1792) {
+ /*Default DDR voltage is 1.35V but lpddr3 supports 1.2V*/
+ reg_idata_ti913_smps7.constraints.min_uV = 1200000;
+ reg_idata_ti913_smps7.constraints.max_uV = 1200000;
+ }
+
i2c_register_board_info(4, palma_ti913_device,
ARRAY_SIZE(palma_ti913_device));
return 0;
},
};
+struct bq2471x_platform_data ardbeg_bq2471x_pdata = {
+ .dac_ichg = 2240,
+ .dac_v = 9008,
+ .dac_minsv = 4608,
+ .dac_iin = 4992,
+ .wdt_refresh_timeout = 40,
+ .gpio = TEGRA_GPIO_PK5,
+};
+
+static struct i2c_board_info __initdata bq2471x_boardinfo[] = {
+ {
+ I2C_BOARD_INFO("bq2471x", 0x09),
+ .platform_data = &ardbeg_bq2471x_pdata,
+ },
+};
+
+struct bq2477x_platform_data ardbeg_bq2477x_pdata = {
+ .dac_ichg = 2240,
+ .dac_v = 9008,
+ .dac_minsv = 4608,
+ .dac_iin = 4992,
+ .wdt_refresh_timeout = 40,
+ .gpio = TEGRA_GPIO_PK5,
+};
+
+static struct i2c_board_info __initdata bq2477x_boardinfo[] = {
+ {
+ I2C_BOARD_INFO("bq2477x", 0x6A),
+ .platform_data = &ardbeg_bq2477x_pdata,
+ },
+};
+
static struct tegra_suspend_platform_data ardbeg_suspend_data = {
.cpu_timer = 500,
.cpu_off_timer = 300,
.corereq_high = true,
.sysclkreq_high = true,
.cpu_lp2_min_residency = 1000,
+ .min_residency_vmin_fmin = 1000,
+ .min_residency_ncpu_fast = 8000,
+ .min_residency_ncpu_slow = 5000,
+ .min_residency_mclk_stop = 5000,
.min_residency_crail = 20000,
};
+static struct power_supply_extcon_plat_data extcon_pdata = {
+ .extcon_name = "tegra-udc",
+};
+
+static struct platform_device power_supply_extcon_device = {
+ .name = "power-supply-extcon",
+ .id = -1,
+ .dev = {
+ .platform_data = &extcon_pdata,
+ },
+};
+
int __init ardbeg_suspend_init(void)
{
struct board_info pmu_board_info;
tegra_get_pmu_board_info(&pmu_board_info);
- if (pmu_board_info.board_id == BOARD_E1735) {
+ if ((pmu_board_info.board_id == BOARD_E1735) &&
+ (pmu_board_info.sku != E1735_EMULATE_E1767_SKU)) {
ardbeg_suspend_data.cpu_timer = 2000;
ardbeg_suspend_data.crail_up_early = true;
}
return 0;
}
-int __init ardbeg_regulator_init(void)
-{
- struct board_info pmu_board_info;
-
- tegra_get_pmu_board_info(&pmu_board_info);
-
- if ((pmu_board_info.board_id == BOARD_E1733) ||
- (pmu_board_info.board_id == BOARD_E1734)) {
- i2c_register_board_info(0, tca6408_expander,
- ARRAY_SIZE(tca6408_expander));
- ardbeg_ams_regulator_init();
- regulator_has_full_constraints();
- } else if (pmu_board_info.board_id == BOARD_E1735) {
- regulator_has_full_constraints();
- ardbeg_tps65913_regulator_init();
- } else if (pmu_board_info.board_id == BOARD_E1736) {
- return tn8_regulator_init();
- } else {
- pr_warn("PMU board id 0x%04x is not supported\n",
- pmu_board_info.board_id);
- }
-
- return 0;
-}
-
/* Macro for defining fixed regulator sub device data */
#define FIXED_SUPPLY(_name) "fixed_reg_en_"#_name
#define FIXED_REG(_id, _var, _name, _in_supply, \
REGULATOR_SUPPLY("vdd_cpu_fixed", NULL),
};
+static struct regulator_consumer_supply fixed_reg_en_avdd_3v3_dp_supply[] = {
+ REGULATOR_SUPPLY("avdd_3v3_dp", NULL),
+};
+
#define fixed_reg_en_ti913_gpio2_supply fixed_reg_en_as3722_gpio1_supply
#define fixed_reg_en_ti913_gpio3_supply fixed_reg_en_as3722_gpio4_supply
#define fixed_reg_en_ti913_gpio4_supply fixed_reg_en_tca6408_p0_supply
FIXED_REG(1, usb0_vbus, usb0_vbus,
NULL, 0, 0, TEGRA_GPIO_PN4,
- false, true, 0, 5000, 0);
+ true, true, 0, 5000, 0);
FIXED_REG(2, usb1_vbus, usb1_vbus,
NULL, 0, 0, TEGRA_GPIO_PN5,
FIXED_REG(3, usb2_vbus, usb2_vbus,
NULL, 0, 0, TEGRA_GPIO_PFF1,
- false, true, 0, 5000, 0);
+ true, true, 0, 5000, 0);
FIXED_REG(4, vdd_sd, vdd_sd,
NULL, 0, 0, TEGRA_GPIO_PR0,
NULL, 0, 1, -1,
false, true, 0, 1000, 0);
+FIXED_REG(21, avdd_3v3_dp, avdd_3v3_dp,
+ NULL, 0, 0, TEGRA_GPIO_PH3,
+ false, true, 0, 3300, 0);
+
/*
* Creating fixed regulator device tables
*/
ADD_FIXED_REG(ti913_gpio7), \
ADD_FIXED_REG(vdd_cpu_fixed),
+#define ARDBEG_E1824_FIXED_REG \
+ ADD_FIXED_REG(avdd_3v3_dp),
+
static struct platform_device *fixed_reg_devs_e1733[] = {
ARDBEG_COMMON_FIXED_REG
ARDBEG_E1733_FIXED_REG
ARDBEG_E1735_FIXED_REG
};
+static struct platform_device *fixed_reg_devs_e1824[] = {
+ ARDBEG_E1824_FIXED_REG
+};
+
/************************ ARDBEG CL-DVFS DATA *********************/
#define E1735_CPU_VDD_MAP_SIZE 33
#define E1735_CPU_VDD_MIN_UV 675000
#define E1735_CPU_VDD_STEP_UV 18750
#define E1735_CPU_VDD_STEP_US 80
+#define E1735_CPU_VDD_IDLE_MA 5000
#define ARDBEG_DEFAULT_CVB_ALIGNMENT 10000
#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
-/* Macro definition of dfll bypass device */
-#define DFLL_BYPASS(_board, _min, _step, _size, _us_sel) \
-static struct regulator_init_data _board##_dfll_bypass_init_data = { \
- .num_consumer_supplies = ARRAY_SIZE(_board##_dfll_bypass_consumers), \
- .consumer_supplies = _board##_dfll_bypass_consumers, \
- .constraints = { \
- .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
- REGULATOR_MODE_STANDBY), \
- .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
- REGULATOR_CHANGE_STATUS | \
- REGULATOR_CHANGE_VOLTAGE), \
- .min_uV = (_min), \
- .max_uV = ((_size) - 1) * (_step) + (_min), \
- .always_on = 1, \
- .boot_on = 1, \
- }, \
-}; \
-static struct tegra_dfll_bypass_platform_data _board##_dfll_bypass_pdata = { \
- .reg_init_data = &_board##_dfll_bypass_init_data, \
- .uV_step = (_step), \
- .linear_min_sel = 0, \
- .n_voltages = (_size), \
- .voltage_time_sel = _us_sel, \
-}; \
-static struct platform_device e1735_dfll_bypass_dev = { \
- .name = "tegra_dfll_bypass", \
- .id = -1, \
- .dev = { \
- .platform_data = &_board##_dfll_bypass_pdata, \
- }, \
-}
-
/* E1735 board parameters for cpu dfll */
static struct tegra_cl_dvfs_cfg_param e1735_cl_dvfs_param = {
.sample_rate = 50000,
REGULATOR_SUPPLY("vdd_cpu", NULL),
};
DFLL_BYPASS(e1735, E1735_CPU_VDD_MIN_UV, E1735_CPU_VDD_STEP_UV,
- E1735_CPU_VDD_MAP_SIZE, E1735_CPU_VDD_STEP_US);
+ E1735_CPU_VDD_MAP_SIZE, E1735_CPU_VDD_STEP_US, TEGRA_GPIO_PX2);
static struct tegra_cl_dvfs_platform_data e1735_cl_dvfs_data = {
.dfll_clk_name = "dfll_cpu",
.pmu_if = TEGRA_CL_DVFS_PMU_PWM,
.u.pmu_pwm = {
.pwm_rate = 12750000,
+ .pwm_pingroup = TEGRA_PINGROUP_DVFS_PWM,
.out_gpio = TEGRA_GPIO_PS5,
.out_enable_high = false,
#ifdef CONFIG_REGULATOR_TEGRA_DFLL_BYPASS
__gpio_set_value(TEGRA_GPIO_PS5, 0); /* enable PWM buffer operations */
}
+static void e1767_suspend_dfll_bypass(void)
+{
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_DVFS_PWM, TEGRA_TRI_TRISTATE);
+}
+
+static void e1767_resume_dfll_bypass(void)
+{
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_DVFS_PWM, TEGRA_TRI_NORMAL);
+}
+
static struct tegra_cl_dvfs_cfg_param e1733_ardbeg_cl_dvfs_param = {
.sample_rate = 12500,
.cfg_param = &e1733_ardbeg_cl_dvfs_param,
};
-static int __init ardbeg_cl_dvfs_init(u16 pmu_board_id)
+static struct tegra_cl_dvfs_cfg_param e1736_ardbeg_cl_dvfs_param = {
+ .sample_rate = 12500, /* i2c freq */
+
+ .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
+ .cf = 10,
+ .ci = 0,
+ .cg = 2,
+
+ .droop_cut_value = 0xF,
+ .droop_restore_ramp = 0x0,
+ .scale_out_ramp = 0x0,
+};
+
+/* E1736 volatge map. Fixed 10mv steps from 700mv to 1400mv */
+#define E1736_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
+static struct voltage_reg_map e1736_cpu_vdd_map[E1736_CPU_VDD_MAP_SIZE];
+static inline void e1736_fill_reg_map(void)
+{
+ int i;
+ for (i = 0; i < E1736_CPU_VDD_MAP_SIZE; i++) {
+ /* 0.7V corresponds to 0b0011010 = 26 */
+ /* 1.4V corresponds to 0b1100000 = 96 */
+ e1736_cpu_vdd_map[i].reg_value = i + 26;
+ e1736_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
+ }
+}
+
+static struct tegra_cl_dvfs_platform_data e1736_cl_dvfs_data = {
+ .dfll_clk_name = "dfll_cpu",
+ .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
+ .u.pmu_i2c = {
+ .fs_rate = 400000,
+ .slave_addr = 0xb0, /* pmu i2c address */
+ .reg = 0x23, /* vdd_cpu rail reg address */
+ },
+ .vdd_map = e1736_cpu_vdd_map,
+ .vdd_map_size = E1736_CPU_VDD_MAP_SIZE,
+ .pmu_undershoot_gb = 100,
+
+ .cfg_param = &e1736_ardbeg_cl_dvfs_param,
+};
+static int __init ardbeg_cl_dvfs_init(struct board_info *pmu_board_info)
{
+ u16 pmu_board_id = pmu_board_info->board_id;
struct tegra_cl_dvfs_platform_data *data = NULL;
int v = tegra_dvfs_rail_get_nominal_millivolts(tegra_cpu_rail);
if (pmu_board_id == BOARD_E1735) {
+ bool e1767 = pmu_board_info->sku == E1735_EMULATE_E1767_SKU;
v = e1735_fill_reg_map(v);
data = &e1735_cl_dvfs_data;
+
+ data->u.pmu_pwm.pwm_bus = e1767 ?
+ TEGRA_CL_DVFS_PWM_1WIRE_DIRECT :
+ TEGRA_CL_DVFS_PWM_1WIRE_BUFFER;
+
if (data->u.pmu_pwm.dfll_bypass_dev) {
/* this has to be exact to 1uV level from table */
e1735_dfll_bypass_init_data.constraints.init_uV = v;
- ardbeg_suspend_data.suspend_dfll_bypass =
+ ardbeg_suspend_data.suspend_dfll_bypass = e1767 ?
+ e1767_suspend_dfll_bypass :
e1735_suspend_dfll_bypass;
- ardbeg_suspend_data.resume_dfll_bypass =
+ ardbeg_suspend_data.resume_dfll_bypass = e1767 ?
+ e1767_resume_dfll_bypass :
e1735_resume_dfll_bypass;
+ tegra_init_cpu_reg_mode_limits(E1735_CPU_VDD_IDLE_MA,
+ REGULATOR_MODE_IDLE);
} else {
(void)e1735_dfll_bypass_dev;
}
data = &e1733_cl_dvfs_data;
}
+ if (pmu_board_id == BOARD_E1736 ||
+ pmu_board_id == BOARD_E1769) {
+ e1736_fill_reg_map();
+ data = &e1736_cl_dvfs_data;
+ }
+
if (data) {
data->flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
tegra_cl_dvfs_device.dev.platform_data = data;
return 0;
}
#else
-static inline int ardbeg_cl_dvfs_init(u16 pmu_board_id)
+static inline int ardbeg_cl_dvfs_init(struct board_info *pmu_board_info)
{ return 0; }
#endif
return 0;
}
+int __init ardbeg_regulator_init(void)
+{
+ struct board_info pmu_board_info;
+
+ tegra_get_pmu_board_info(&pmu_board_info);
+
+ if ((pmu_board_info.board_id == BOARD_E1733) ||
+ (pmu_board_info.board_id == BOARD_E1734)) {
+ i2c_register_board_info(0, tca6408_expander,
+ ARRAY_SIZE(tca6408_expander));
+ ardbeg_ams_regulator_init();
+ regulator_has_full_constraints();
+ } else if (pmu_board_info.board_id == BOARD_E1735) {
+ regulator_has_full_constraints();
+ ardbeg_tps65913_regulator_init();
+ } else if (pmu_board_info.board_id == BOARD_E1736 ||
+ pmu_board_info.board_id == BOARD_E1769) {
+ tn8_regulator_init();
+ ardbeg_cl_dvfs_init(&pmu_board_info);
+ return tn8_fixed_regulator_init();
+ } else {
+ pr_warn("PMU board id 0x%04x is not supported\n",
+ pmu_board_info.board_id);
+ }
+
+ if (get_power_supply_type() == POWER_SUPPLY_TYPE_BATTERY) {
+ i2c_register_board_info(1, bq2471x_boardinfo,
+ ARRAY_SIZE(bq2471x_boardinfo));
+ i2c_register_board_info(1, bq2477x_boardinfo,
+ ARRAY_SIZE(bq2477x_boardinfo));
+ }
+
+ platform_device_register(&power_supply_extcon_device);
+
+ ardbeg_cl_dvfs_init(&pmu_board_info);
+ return 0;
+}
+
static int __init ardbeg_fixed_regulator_init(void)
{
struct board_info pmu_board_info;
+ struct board_info display_board_info;
- if (!of_machine_is_compatible("nvidia,ardbeg"))
+ if ((!of_machine_is_compatible("nvidia,ardbeg")) &&
+ (!of_machine_is_compatible("nvidia,ardbeg_sata")))
return 0;
+ tegra_get_display_board_info(&display_board_info);
+
+ if (display_board_info.board_id == BOARD_E1824)
+ platform_add_devices(fixed_reg_devs_e1824,
+ ARRAY_SIZE(fixed_reg_devs_e1824));
+
tegra_get_pmu_board_info(&pmu_board_info);
- ardbeg_cl_dvfs_init(pmu_board_info.board_id);
if (pmu_board_info.board_id == BOARD_E1733)
return platform_add_devices(fixed_reg_devs_e1733,
else if (pmu_board_info.board_id == BOARD_E1735)
return platform_add_devices(fixed_reg_devs_e1735,
ARRAY_SIZE(fixed_reg_devs_e1735));
+ else if (pmu_board_info.board_id == BOARD_E1736)
+ return 0;
else
pr_warn("The PMU board id 0x%04x is not supported\n",
pmu_board_info.board_id);
regulator_mA = get_maximum_cpu_current_supported();
if (!regulator_mA)
- regulator_mA = 16000;
+ regulator_mA = 14000;
pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
tegra_init_cpu_edp_limits(regulator_mA);
+ /* gpu maximum current */
+ regulator_mA = 12000;
+ pr_info("%s: GPU regulator %d mA\n", __func__, regulator_mA);
+
+ tegra_init_gpu_edp_limits(regulator_mA);
return 0;
}
.governor_params = &soctherm_pid_params,
};
+static struct tegra_tsensor_pmu_data tpdata_palmas = {
+ .reset_tegra = 1,
+ .pmu_16bit_ops = 0,
+ .controller_type = 0,
+ .pmu_i2c_addr = 0x58,
+ .i2c_controller_id = 4,
+ .poweroff_reg_addr = 0xa0,
+ .poweroff_reg_data = 0x0,
+};
+
+static struct tegra_tsensor_pmu_data tpdata_as3722 = {
+ .reset_tegra = 1,
+ .pmu_16bit_ops = 0,
+ .controller_type = 0,
+ .pmu_i2c_addr = 0x40,
+ .i2c_controller_id = 4,
+ .poweroff_reg_addr = 0x36,
+ .poweroff_reg_data = 0x2,
+};
+
static struct soctherm_platform_data ardbeg_soctherm_data = {
.therm = {
[THERM_CPU] = {
.zone_enable = true,
.passive_delay = 1000,
.hotspot_offset = 6000,
- .num_trips = 0,
+ .num_trips = 3,
.trips = {
{
- .cdev_type = "tegra-balanced",
- .trip_temp = 84000,
- .trip_type = THERMAL_TRIP_PASSIVE,
+ .cdev_type = "tegra-shutdown",
+ .trip_temp = 101000,
+ .trip_type = THERMAL_TRIP_CRITICAL,
.upper = THERMAL_NO_LIMIT,
.lower = THERMAL_NO_LIMIT,
},
{
.cdev_type = "tegra-heavy",
- .trip_temp = 94000,
+ .trip_temp = 99000,
.trip_type = THERMAL_TRIP_HOT,
.upper = THERMAL_NO_LIMIT,
.lower = THERMAL_NO_LIMIT,
},
{
- .cdev_type = "tegra-shutdown",
- .trip_temp = 104000,
- .trip_type = THERMAL_TRIP_CRITICAL,
+ .cdev_type = "cpu-balanced",
+ .trip_temp = 89000,
+ .trip_type = THERMAL_TRIP_PASSIVE,
.upper = THERMAL_NO_LIMIT,
.lower = THERMAL_NO_LIMIT,
},
},
[THERM_GPU] = {
.zone_enable = true,
- .num_trips = 0,
+ .passive_delay = 1000,
+ .hotspot_offset = 6000,
+ .num_trips = 2,
.trips = {
+ {
+ .cdev_type = "tegra-shutdown",
+ .trip_temp = 103000,
+ .trip_type = THERMAL_TRIP_CRITICAL,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ },
+ {
+ .cdev_type = "gpu-balanced",
+ .trip_temp = 91000,
+ .trip_type = THERMAL_TRIP_PASSIVE,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ },
+/*
{
.cdev_type = "gk20a_cdev",
- .trip_temp = 80000,
+ .trip_temp = 101000,
.trip_type = THERMAL_TRIP_PASSIVE,
.upper = THERMAL_NO_LIMIT,
.lower = THERMAL_NO_LIMIT,
},
{
.cdev_type = "tegra-heavy",
- .trip_temp = 90000,
+ .trip_temp = 101000,
.trip_type = THERMAL_TRIP_HOT,
.upper = THERMAL_NO_LIMIT,
.lower = THERMAL_NO_LIMIT,
},
+*/
+ },
+ .tzp = &soctherm_tzp,
+ },
+ [THERM_MEM] = {
+ .zone_enable = true,
+ .num_trips = 1,
+ .trips = {
{
.cdev_type = "tegra-shutdown",
- .trip_temp = 102000,
+ .trip_temp = 103000, /* = GPU shut */
.trip_type = THERMAL_TRIP_CRITICAL,
.upper = THERMAL_NO_LIMIT,
.lower = THERMAL_NO_LIMIT,
},
},
- .tzp = &soctherm_tzp,
},
[THERM_PLL] = {
.zone_enable = true,
+ .tzp = &soctherm_tzp,
},
},
.throttle = {
- [THROTTLE_LIGHT] = {
- .priority = 0x0f,
- .devs = {
- [THROTTLE_DEV_CPU] = {
- .enable = false,
- },
- [THROTTLE_DEV_GPU] = {
- .enable = false,
- },
- },
- },
[THROTTLE_HEAVY] = {
- .priority = 0xf0,
+ .priority = 100,
.devs = {
[THROTTLE_DEV_CPU] = {
- .enable = false,
+ .enable = true,
.depth = 80,
},
[THROTTLE_DEV_GPU] = {
},
},
},
+ .tshut_pmu_trip_data = &tpdata_palmas,
};
int __init ardbeg_soctherm_init(void)
{
+ s32 base_cp, shft_cp;
+ u32 base_ft, shft_ft;
+ struct board_info pmu_board_info;
+
+ /* do this only for supported CP,FT fuses */
+ if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) &&
+ (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) {
+ tegra_platform_edp_init(
+ ardbeg_soctherm_data.therm[THERM_CPU].trips,
+ &ardbeg_soctherm_data.therm[THERM_CPU].num_trips,
+ 8000); /* edp temperature margin */
+ tegra_platform_gpu_edp_init(
+ ardbeg_soctherm_data.therm[THERM_GPU].trips,
+ &ardbeg_soctherm_data.therm[THERM_GPU].num_trips,
+ 8000);
+ tegra_add_tj_trips(
+ ardbeg_soctherm_data.therm[THERM_CPU].trips,
+ &ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
+ tegra_add_tgpu_trips(
+ ardbeg_soctherm_data.therm[THERM_GPU].trips,
+ &ardbeg_soctherm_data.therm[THERM_GPU].num_trips);
+ tegra_add_vc_trips(
+ ardbeg_soctherm_data.therm[THERM_CPU].trips,
+ &ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
+ tegra_add_tpll_trips(
+ ardbeg_soctherm_data.therm[THERM_PLL].trips,
+ &ardbeg_soctherm_data.therm[THERM_PLL].num_trips);
+ }
+
+ tegra_get_pmu_board_info(&pmu_board_info);
+
+ if ((pmu_board_info.board_id == BOARD_E1733) ||
+ (pmu_board_info.board_id == BOARD_E1734))
+ ardbeg_soctherm_data.tshut_pmu_trip_data = &tpdata_as3722;
+ else if (pmu_board_info.board_id == BOARD_E1735 ||
+ pmu_board_info.board_id == BOARD_E1736 ||
+ pmu_board_info.board_id == BOARD_E1769)
+ ;/* tpdata_palmas is default */
+ else
+ pr_warn("soctherm THERMTRIP is not supported on this PMIC\n");
+
return tegra11_soctherm_init(&ardbeg_soctherm_data);
}
Code Review / linux-3.10.git / blobdiff