#include <linux/io.h>
#include <mach/edp.h>
#include <mach/irqs.h>
+#include <linux/edp.h>
+#include <linux/platform_data/tegra_edp.h>
+#include <linux/pid_thermal_gov.h>
#include <mach/hardware.h>
#include <linux/regulator/fixed.h>
#include <linux/mfd/palmas.h>
#include <linux/regulator/tegra-dfll-bypass-regulator.h>
#include <asm/mach-types.h>
+#include <mach/tegra_fuse.h>
#include "pm.h"
#include "dvfs.h"
#include "iomap.h"
#include "tegra-board-id.h"
#include "tegra_cl_dvfs.h"
+#include "tegra11_soctherm.h"
+#include "tegra3_tsensor.h"
#define PMC_CTRL 0x0
#define PMC_CTRL_INTR_LOW (1 << 17)
-#define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep, \
- _tstep, _vsel) \
- static struct palmas_reg_init reg_init_data_##_name = { \
- .warm_reset = _warm_reset, \
- .roof_floor = _roof_floor, \
- .mode_sleep = _mode_sleep, \
- .tstep = _tstep, \
- .vsel = _vsel, \
- }
-
-
/************************ ARDBEG E1733 based regulators ***********/
static struct regulator_consumer_supply as3722_ldo0_supply[] = {
REGULATOR_SUPPLY("avdd_pll_m", NULL),
REGULATOR_SUPPLY("vif", "2-0010"),
REGULATOR_SUPPLY("vif", "2-0036"),
REGULATOR_SUPPLY("vdd_i2c", "2-000c"),
+ REGULATOR_SUPPLY("vi2c", "2-0030"),
};
REGULATOR_SUPPLY("avdd_af1_cam", NULL),
REGULATOR_SUPPLY("imx135_reg1", NULL),
REGULATOR_SUPPLY("vdd", "2-000c"),
+ REGULATOR_SUPPLY("vin", "2-0030"),
};
static struct regulator_consumer_supply as3722_ldo11_supply[] = {
REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
-#ifdef CONFIG_ARCH_TEGRA_12x_SOC
REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
-#endif
REGULATOR_SUPPLY("vddio_audio", NULL),
REGULATOR_SUPPLY("pwrdet_audio", NULL),
REGULATOR_SUPPLY("vddio_uart", NULL),
};
-AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1, 2);
-AMS_PDATA_INIT(sd1, NULL, 700000, 1400000, 1, 1, 1, 1);
+AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE2);
+AMS_PDATA_INIT(sd1, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 0, 1, 1, 0);
AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
AMS_PDATA_INIT(sd6, NULL, 700000, 1400000, 1, 1, 0, 0);
-AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, 1);
+AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
AMS_PDATA_INIT(ldo3, NULL, 800000, 800000, 1, 1, 1, 0);
REGULATOR_SUPPLY("vdd", "0-0048"),
REGULATOR_SUPPLY("vdd", "0-000c"),
REGULATOR_SUPPLY("vdd", "0-0077"),
-#ifdef CONFIG_ARCH_TEGRA_11x_SOC
- REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
- REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
- REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
- REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
- REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
-#endif
};
-PALMAS_PDATA_INIT(ti913_smps123, 900, 1400, NULL, 1, 1, 1, NORMAL);
-PALMAS_PDATA_INIT(ti913_smps45, 900, 1400, NULL, 1, 1, 1, NORMAL);
-PALMAS_PDATA_INIT(ti913_smps6, 1800, 1800, NULL, 1, 1, 1, NORMAL);
-PALMAS_PDATA_INIT(ti913_smps7, 900, 1350, NULL, 1, 1, 1, NORMAL);
-PALMAS_PDATA_INIT(ti913_smps9, 1050, 1050, NULL, 0, 0, 0, NORMAL);
-PALMAS_PDATA_INIT(ti913_ldo1, 1050, 1250, palmas_rails(ti913_smps7),
- 1, 1, 1, 0);
-PALMAS_PDATA_INIT(ti913_ldo2, 1200, 1200, palmas_rails(ti913_smps6),
- 0, 0, 1, 0);
-PALMAS_PDATA_INIT(ti913_ldo3, 3100, 3100, NULL,
- 0, 0, 1, 0);
-PALMAS_PDATA_INIT(ti913_ldo4, 1200, 1200, palmas_rails(ti913_smps6),
- 0, 0, 1, 0);
-PALMAS_PDATA_INIT(ti913_ldo5, 2700, 2700, NULL,
- 0, 0, 1, 0);
-PALMAS_PDATA_INIT(ti913_ldo6, 1800, 1800, NULL,
- 0, 0, 1, 0);
-PALMAS_PDATA_INIT(ti913_ldo7, 2700, 2700, NULL,
- 0, 0, 1, 0);
-PALMAS_PDATA_INIT(ti913_ldo8, 1000, 1000, NULL, 1, 1, 1, 0);
-PALMAS_PDATA_INIT(ti913_ldo9, 1800, 3300, NULL,
- 0, 0, 1, 0);
-PALMAS_PDATA_INIT(ti913_ldoln, 1050, 1050, palmas_rails(ti913_smps6),
- 0, 0, 1, 0);
-PALMAS_PDATA_INIT(ti913_ldousb, 1800, 1800, NULL, 0, 0, 1, 0);
-PALMAS_PDATA_INIT(ti913_regen1, 2800, 3300, NULL, 1, 1, 1, 0);
+PALMAS_REGS_PDATA(ti913_smps123, 700, 1400, NULL, 1, 1, 1, NORMAL,
+ 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_smps45, 900, 1400, NULL, 1, 1, 1, NORMAL,
+ 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_smps6, 1800, 1800, NULL, 1, 1, 1, NORMAL,
+ 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_smps7, 900, 1350, NULL, 1, 1, 1, NORMAL,
+ 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_smps9, 1050, 1050, NULL, 0, 0, 0, NORMAL,
+ 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldo1, 1050, 1250, palmas_rails(ti913_smps7),
+ 1, 1, 1, 0, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldo2, 1200, 1200, palmas_rails(ti913_smps6),
+ 0, 0, 1, 0, 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldo3, 3100, 3100, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldo4, 1200, 1200, palmas_rails(ti913_smps6),
+ 0, 0, 1, 0, 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldo5, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldo6, 1800, 1800, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldo7, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldo8, 1000, 1000, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldo9, 1800, 3300, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldoln, 1050, 1050, palmas_rails(ti913_smps6),
+ 0, 0, 1, 0, 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_ldousb, 1800, 1800, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
+PALMAS_REGS_PDATA(ti913_regen1, 2800, 3300, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
#define PALMAS_REG_PDATA(_sname) ®_idata_##_sname
static struct regulator_init_data *ardbeg_1735_reg_data[PALMAS_NUM_REGS] = {
NULL,
};
-PALMAS_REG_INIT(ti913_smps123, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
-PALMAS_REG_INIT(ti913_smps6, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_smps7, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_smps9, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_ldo1, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_ldo2, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_ldo3, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_ldo4, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_ldo5, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_ldo6, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_ldo7, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_ldo8, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_ldo9, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_ldoln, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_ldousb, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ti913_regen1, 0, 0, 0, 0, 0);
-
#define PALMAS_REG_INIT_DATA(_sname) ®_init_data_##_sname
static struct palmas_reg_init *ardbeg_1735_reg_init[PALMAS_NUM_REGS] = {
NULL,
};
static struct palmas_pinctrl_config palmas_ti913_pincfg[] = {
- PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
- PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO0, ID, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO5, CLK32KGAUDIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
+ PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
+ PALMAS_PINMUX("vac", "vac", NULL, NULL),
+ PALMAS_PINMUX("gpio0", "id", NULL, NULL),
+ PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
+ PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
+ PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
+ PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
+ PALMAS_PINMUX("gpio5", "clk32kgaudio", NULL, NULL),
+ PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
+ PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
};
static struct palmas_pinctrl_platform_data palmas_ti913_pinctrl_pdata = {
};
static struct palmas_pmic_platform_data pmic_ti913_platform = {
- .enable_ldo8_tracking = true,
- .disabe_ldo8_tracking_suspend = true,
+};
+
+static struct palmas_pm_platform_data palmas_pm_pdata = {
+ .use_power_off = true,
+ .use_power_reset = true,
};
static struct palmas_platform_data palmas_ti913_pdata = {
.gpio_base = PALMAS_TEGRA_GPIO_BASE,
.irq_base = PALMAS_TEGRA_IRQ_BASE,
.pmic_pdata = &pmic_ti913_platform,
- .use_power_off = true,
.pinctrl_pdata = &palmas_ti913_pinctrl_pdata,
.clk32k_init_data = palmas_ti913_clk32k_idata,
.clk32k_init_data_size = ARRAY_SIZE(palmas_ti913_clk32k_idata),
.extcon_pdata = &palmas_extcon_pdata,
+ .pm_pdata = &palmas_pm_pdata,
};
static struct i2c_board_info palma_ti913_device[] = {
*/
pmc_ctrl = readl(pmc + PMC_CTRL);
writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
+
+ /* Tracking configuration */
+ reg_init_data_ti913_ldo8.config_flags =
+ PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
+ PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
+
for (i = 0; i < PALMAS_NUM_REGS ; i++) {
pmic_ti913_platform.reg_data[i] = ardbeg_1735_reg_data[i];
pmic_ti913_platform.reg_init[i] = ardbeg_1735_reg_init[i];
/* Set vdd_gpu init uV to 1V */
reg_idata_ti913_smps123.constraints.init_uV = 900000;
+
i2c_register_board_info(4, palma_ti913_device,
ARRAY_SIZE(palma_ti913_device));
return 0;
}
-/************************ ARDBEG based regulator *****************/
-static struct regulator_consumer_supply palmas_smps12_supply[] = {
- REGULATOR_SUPPLY("vdd_core", NULL),
-};
-
-static struct regulator_consumer_supply palmas_smps3_supply[] = {
- REGULATOR_SUPPLY("vdd_modem", NULL),
-};
-
-static struct regulator_consumer_supply palmas_smps6_supply[] = {
- REGULATOR_SUPPLY("vddio_ddr", NULL),
- REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
- REGULATOR_SUPPLY("vddio_ddr3", NULL),
- REGULATOR_SUPPLY("vcore1_ddr3", NULL),
-};
-
-static struct regulator_consumer_supply palmas_smps8_supply[] = {
- REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
- REGULATOR_SUPPLY("avdd_pll_c4", NULL),
- REGULATOR_SUPPLY("avdd_pll_cg", NULL),
- REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
- REGULATOR_SUPPLY("avdd_pll_m", NULL),
- REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
- REGULATOR_SUPPLY("avdd_pll_utmip", NULL),
- REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
- REGULATOR_SUPPLY("avdd_pll_x", NULL),
- REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
- REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
-};
-
-#define palmas_smps9_supply as3722_sd5_supply
-
-static struct regulator_consumer_supply palmas_ldo1_supply[] = {
- REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
- REGULATOR_SUPPLY("imx135_reg2", NULL),
-};
-
-static struct regulator_consumer_supply palmas_ldo2_supply[] = {
- REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
- REGULATOR_SUPPLY("avdd_hdmi", NULL),
- REGULATOR_SUPPLY("avdd_pex_pll", NULL),
- REGULATOR_SUPPLY("avddio_pex_pll", NULL),
- REGULATOR_SUPPLY("dvddio_pex", NULL),
- REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
-};
-
-static struct regulator_consumer_supply palmas_ldo3_supply[] = {
- REGULATOR_SUPPLY("vddio_cam_mb", NULL),
- REGULATOR_SUPPLY("vdd_cam_1v8_cam", NULL),
- REGULATOR_SUPPLY("vif", "2-0010"),
- REGULATOR_SUPPLY("vif", "2-0036"),
- REGULATOR_SUPPLY("vdd_i2c", "2-000c"),
-};
-
-static struct regulator_consumer_supply palmas_ldo4_supply[] = {
- REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
- REGULATOR_SUPPLY("vdig", "2-0010"),
- REGULATOR_SUPPLY("vdig", "2-0036"),
- REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
- REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
- REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
-};
-
-static struct regulator_consumer_supply palmas_ldo5_supply[] = {
- REGULATOR_SUPPLY("vdd_rtc", NULL),
-};
-
-static struct regulator_consumer_supply palmas_ldo6_supply[] = {
- REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
- REGULATOR_SUPPLY("vana", "2-0010"),
- REGULATOR_SUPPLY("vdd", "1-004c"),
- REGULATOR_SUPPLY("vdd", "1-004d"),
-};
-
-static struct regulator_consumer_supply palmas_ldo7_supply[] = {
- REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
- REGULATOR_SUPPLY("vana", "2-0036"),
-};
-
-static struct regulator_consumer_supply palmas_ldo8_supply[] = {
- REGULATOR_SUPPLY("vdd_snsr_mb", NULL),
- REGULATOR_SUPPLY("vdd_snsr_temp", NULL),
- REGULATOR_SUPPLY("vdd", "0-0048"),
- REGULATOR_SUPPLY("vdd_snsr_pm", NULL),
- REGULATOR_SUPPLY("vdd_pca", "1-0071"),
- REGULATOR_SUPPLY("vdd", "0-0069"),
- REGULATOR_SUPPLY("vdd", "0-000c"),
- REGULATOR_SUPPLY("vdd", "0-0077"),
-};
-
-static struct regulator_consumer_supply palmas_ldo9_supply[] = {
- REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
- REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
- REGULATOR_SUPPLY("avdd_1v2_hsic_mdm", NULL),
- REGULATOR_SUPPLY("pwrdet_mipi", NULL),
- REGULATOR_SUPPLY("avdd_1v2_hsic_com", NULL),
- REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
-};
-
-static struct regulator_consumer_supply palmas_ldo10_supply[] = {
- REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
-};
-
-static struct regulator_consumer_supply palmas_ldo11_supply[] = {
- REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
- REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
- REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
- REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
- REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
- REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
- REGULATOR_SUPPLY("avdd_3v3_pex", NULL),
- REGULATOR_SUPPLY("avdd_3v3_pex_pll", NULL),
-};
-
-static struct regulator_consumer_supply palmas_ldo12_supply[] = {
- REGULATOR_SUPPLY("vdd_lcd_1v8b_dis", NULL),
- REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
- REGULATOR_SUPPLY("dvdd_lcd", NULL),
-};
-
-static struct regulator_consumer_supply palmas_ldo13_supply[] = {
- REGULATOR_SUPPLY("dvdd", "spi0.0"),
-};
-
-static struct regulator_consumer_supply palmas_ldo14_supply[] = {
- REGULATOR_SUPPLY("avdd_af1_cam", NULL),
- REGULATOR_SUPPLY("imx135_reg1", NULL),
- REGULATOR_SUPPLY("vdd", "2-000c"),
-};
-
-static struct regulator_consumer_supply palmas_ldoln_supply[] = {
- REGULATOR_SUPPLY("avdd", "spi0.0"),
-};
-
-static struct regulator_consumer_supply palmas_ldousb_supply[] = {
- REGULATOR_SUPPLY("vpp_fuse", NULL),
-};
-
-static struct regulator_consumer_supply palmas_regen1_supply[] = {
- REGULATOR_SUPPLY("vdd_com_3v3", NULL),
- REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
- REGULATOR_SUPPLY("vdd_nfc_3v3", NULL),
-};
-
-static struct regulator_consumer_supply palmas_regen2_supply[] = {
- REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5639.0"),
- REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
- REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
-};
-
-static struct regulator_consumer_supply palmas_regen4_supply[] = {
- REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
-};
-
-/* TPS51632 DC-DC converter */
-static struct regulator_consumer_supply tps51632_dcdc_cpu_supply[] = {
- REGULATOR_SUPPLY("vdd_cpu", NULL),
-};
-
-static struct regulator_init_data tps51632_cpu_init_data = {
- .constraints = {
- .min_uV = 500000,
- .max_uV = 1520000,
- .valid_modes_mask = (REGULATOR_MODE_NORMAL |
- REGULATOR_MODE_STANDBY),
- .valid_ops_mask = (REGULATOR_CHANGE_MODE |
- REGULATOR_CHANGE_STATUS |
- REGULATOR_CHANGE_CONTROL |
- REGULATOR_CHANGE_VOLTAGE),
- .always_on = 1,
- .boot_on = 1,
- .apply_uV = 0,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_cpu_supply),
- .consumer_supplies = tps51632_dcdc_cpu_supply,
- .supply_regulator = palmas_rails(regen2),
-};
-
-static struct tps51632_regulator_platform_data tps51632_pdata_cpu = {
- .reg_init_data = &tps51632_cpu_init_data,
- .enable_pwm = false,
- .max_voltage_uV = 1520000,
- .base_voltage_uV = 500000,
- .slew_rate_uv_per_us = 6000,
-};
-
-static struct i2c_board_info tps51632_cpu_boardinfo[] = {
- {
- I2C_BOARD_INFO("tps51632_cpu", 0x43),
- .platform_data = &tps51632_pdata_cpu,
- },
-};
-
-static struct regulator_consumer_supply tps51632_dcdc_gpu_supply[] = {
- REGULATOR_SUPPLY("vdd_gpu", NULL),
-};
-
-static struct regulator_init_data tps51632_init_gpu_data = {
- .constraints = {
- .min_uV = 500000,
- .max_uV = 1520000,
- .valid_modes_mask = (REGULATOR_MODE_NORMAL |
- REGULATOR_MODE_STANDBY),
- .valid_ops_mask = (REGULATOR_CHANGE_MODE |
- REGULATOR_CHANGE_STATUS |
- REGULATOR_CHANGE_CONTROL |
- REGULATOR_CHANGE_VOLTAGE),
- .always_on = 1,
- .boot_on = 1,
- .apply_uV = 0,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_gpu_supply),
- .consumer_supplies = tps51632_dcdc_gpu_supply,
- .supply_regulator = palmas_rails(regen2),
-};
-
-static struct tps51632_regulator_platform_data tps51632_pdata_gpu = {
- .reg_init_data = &tps51632_init_gpu_data,
- .enable_pwm = false,
- .max_voltage_uV = 1520000,
- .base_voltage_uV = 500000,
- .slew_rate_uv_per_us = 6000,
-};
-
-static struct i2c_board_info tps51632_gpu_boardinfo[] = {
- {
- I2C_BOARD_INFO("tps51632_gpu", 0x45),
- .platform_data = &tps51632_pdata_gpu,
- },
-};
-
-#define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
- _boot_on, _apply_uv) \
- static struct regulator_init_data reg_idata_##_name = { \
- .constraints = { \
- .name = palmas_rails(_name), \
- .min_uV = (_minmv)*1000, \
- .max_uV = (_maxmv)*1000, \
- .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
- REGULATOR_MODE_STANDBY), \
- .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
- REGULATOR_CHANGE_STATUS | \
- REGULATOR_CHANGE_VOLTAGE), \
- .always_on = _always_on, \
- .boot_on = _boot_on, \
- .apply_uV = _apply_uv, \
- }, \
- .num_consumer_supplies = \
- ARRAY_SIZE(palmas_##_name##_supply), \
- .consumer_supplies = palmas_##_name##_supply, \
- .supply_regulator = _supply_reg, \
- }
-
-PALMAS_PDATA_INIT(smps12, 900, 1300, NULL, 0, 0, 0);
-PALMAS_PDATA_INIT(smps3, 1000, 3300, NULL, 1, 1, 0);
-PALMAS_PDATA_INIT(smps6, 500, 1650, NULL, 0, 0, 0);
-PALMAS_PDATA_INIT(smps8, 1000, 3300, NULL, 0, 0, 0);
-PALMAS_PDATA_INIT(smps9, 1800, 1800, NULL, 1, 1, 0);
-PALMAS_PDATA_INIT(ldo1, 1050, 1050, palmas_rails(smps3), 0, 0, 1);
-PALMAS_PDATA_INIT(ldo2, 2800, 3000, palmas_rails(smps6), 0, 0, 0);
-PALMAS_PDATA_INIT(ldo3, 2800, 3000, NULL, 0, 0, 0);
-//PALMAS_PDATA_INIT(ldo4, 2800, 3000, palmas_rails(smps3), 0, 0, 0);
-PALMAS_PDATA_INIT(ldo4, 1500, 2100, palmas_rails(smps3), 0, 0, 0);
-PALMAS_PDATA_INIT(ldo5, 1100, 1100, palmas_rails(smps6), 1, 1, 1);
-PALMAS_PDATA_INIT(ldo6, 2700, 2700, NULL, 0, 0, 0);
-PALMAS_PDATA_INIT(ldo7, 2800, 2800, NULL, 0, 0, 0);
-PALMAS_PDATA_INIT(ldo8, 2800, 3000, NULL, 0, 0, 0);
-//PALMAS_PDATA_INIT(ldo9, 2800, 3000, palmas_rails(smps3), 1, 1, 0);
-PALMAS_PDATA_INIT(ldo9, 1500, 2100, palmas_rails(smps3), 0, 0, 0);
-PALMAS_PDATA_INIT(ldo10, 1800, 3300, NULL, 0, 0, 0);
-PALMAS_PDATA_INIT(ldo11, 3300, 3300, NULL, 0, 0, 0);
-PALMAS_PDATA_INIT(ldo12, 2800, 3000, palmas_rails(smps9), 1, 1, 0);
-PALMAS_PDATA_INIT(ldo13, 1800, 1800, palmas_rails(smps9), 1, 1, 1);
-PALMAS_PDATA_INIT(ldo14, 2800, 3000, NULL, 0, 0, 0);
-PALMAS_PDATA_INIT(ldoln, 3300, 3300, NULL, 1, 1, 1);
-PALMAS_PDATA_INIT(ldousb, 2800, 3000, NULL, 0, 0, 0);
-PALMAS_PDATA_INIT(regen1, 3300, 3300, NULL, 1, 0, 0);
-PALMAS_PDATA_INIT(regen2, 5000, 5000, NULL, 1, 0, 0);
-PALMAS_PDATA_INIT(regen4, 5000, 5000, NULL, 0, 0, 0);
-
-#define PALMAS_REG_PDATA(_sname) ®_idata_##_sname
-
-static struct regulator_init_data *ardbeg_reg_data[PALMAS_NUM_REGS] = {
- PALMAS_REG_PDATA(smps12),
- NULL,
- PALMAS_REG_PDATA(smps3),
- NULL,
- NULL,
- PALMAS_REG_PDATA(smps6),
- NULL,
- PALMAS_REG_PDATA(smps8),
- PALMAS_REG_PDATA(smps9),
- NULL,
- PALMAS_REG_PDATA(ldo1),
- PALMAS_REG_PDATA(ldo2),
- PALMAS_REG_PDATA(ldo3),
- PALMAS_REG_PDATA(ldo4),
- PALMAS_REG_PDATA(ldo5),
- PALMAS_REG_PDATA(ldo6),
- PALMAS_REG_PDATA(ldo7),
- PALMAS_REG_PDATA(ldo8),
- PALMAS_REG_PDATA(ldo9),
- PALMAS_REG_PDATA(ldo10),
- PALMAS_REG_PDATA(ldo11),
- PALMAS_REG_PDATA(ldo12),
- PALMAS_REG_PDATA(ldo13),
- PALMAS_REG_PDATA(ldo14),
- PALMAS_REG_PDATA(ldoln),
- PALMAS_REG_PDATA(ldousb),
- PALMAS_REG_PDATA(regen1),
- PALMAS_REG_PDATA(regen2),
- NULL,
- PALMAS_REG_PDATA(regen4),
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
-};
-
-PALMAS_REG_INIT(smps12, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
-PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(smps45, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 1, 0, 0);
-PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo10, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo11, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo12, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo13, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldo14, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
-PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
-
-static struct palmas_reg_init *ardbeg_reg_init[PALMAS_NUM_REGS] = {
- PALMAS_REG_INIT_DATA(smps12),
- PALMAS_REG_INIT_DATA(smps123),
- PALMAS_REG_INIT_DATA(smps3),
- PALMAS_REG_INIT_DATA(smps45),
- PALMAS_REG_INIT_DATA(smps457),
- PALMAS_REG_INIT_DATA(smps6),
- PALMAS_REG_INIT_DATA(smps7),
- PALMAS_REG_INIT_DATA(smps8),
- PALMAS_REG_INIT_DATA(smps9),
- PALMAS_REG_INIT_DATA(smps10),
- PALMAS_REG_INIT_DATA(ldo1),
- PALMAS_REG_INIT_DATA(ldo2),
- PALMAS_REG_INIT_DATA(ldo3),
- PALMAS_REG_INIT_DATA(ldo4),
- PALMAS_REG_INIT_DATA(ldo5),
- PALMAS_REG_INIT_DATA(ldo6),
- PALMAS_REG_INIT_DATA(ldo7),
- PALMAS_REG_INIT_DATA(ldo8),
- PALMAS_REG_INIT_DATA(ldo9),
- PALMAS_REG_INIT_DATA(ldo10),
- PALMAS_REG_INIT_DATA(ldo11),
- PALMAS_REG_INIT_DATA(ldo12),
- PALMAS_REG_INIT_DATA(ldo13),
- PALMAS_REG_INIT_DATA(ldo14),
- PALMAS_REG_INIT_DATA(ldoln),
- PALMAS_REG_INIT_DATA(ldousb),
-};
-
-static struct palmas_pmic_platform_data pmic_platform = {
- .enable_ldo8_tracking = false,
- .disabe_ldo8_tracking_suspend = false,
-};
-
-static struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
- {
- .clk32k_id = PALMAS_CLOCK32KG,
- .enable = true,
- }, {
- .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
- .enable = true,
- },
-};
-
-static struct palmas_pinctrl_config palmas_pincfg[] = {
- PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
- PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO0, ID, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO8, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO9, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO10, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO11, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO12, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO13, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO14, GPIO, DEFAULT, DEFAULT),
- PALMAS_PINMUX(GPIO15, GPIO, DEFAULT, DEFAULT),
-};
-
-static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
- .pincfg = palmas_pincfg,
- .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
- .dvfs1_enable = false,
- .dvfs2_enable = false,
-};
-
-static struct palmas_platform_data palmas_pdata = {
- .gpio_base = PALMAS_TEGRA_GPIO_BASE,
- .irq_base = PALMAS_TEGRA_IRQ_BASE,
- .pmic_pdata = &pmic_platform,
- .clk32k_init_data = palmas_clk32k_idata,
- .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
- .irq_flags = IRQ_TYPE_LEVEL_HIGH,
- .use_power_off = true,
- .pinctrl_pdata = &palmas_pinctrl_pdata,
-};
-
-static struct i2c_board_info palma_device[] = {
- {
- I2C_BOARD_INFO("tps80036", 0x58),
- .irq = INT_EXTERNAL_PMU,
- .platform_data = &palmas_pdata,
- },
-};
-
static struct pca953x_platform_data tca6408_pdata = {
.gpio_base = PMU_TCA6416_GPIO_BASE,
};
tegra_get_pmu_board_info(&pmu_board_info);
- if (pmu_board_info.board_id == BOARD_E1735)
- ardbeg_suspend_data.cpu_timer = 2500;
+ if (pmu_board_info.board_id == BOARD_E1735) {
+ ardbeg_suspend_data.cpu_timer = 2000;
+ ardbeg_suspend_data.crail_up_early = true;
+ }
tegra_init_suspend(&ardbeg_suspend_data);
return 0;
int __init ardbeg_regulator_init(void)
{
struct board_info pmu_board_info;
- int i;
- void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
- u32 pmc_ctrl;
tegra_get_pmu_board_info(&pmu_board_info);
ARRAY_SIZE(tca6408_expander));
ardbeg_ams_regulator_init();
regulator_has_full_constraints();
- } else if (pmu_board_info.board_id == BOARD_E1731) {
- /* configure the power management controller to trigger PMU
- * interrupts when high */
- pmc_ctrl = readl(pmc + PMC_CTRL);
- writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
-
- for (i = 0; i < PALMAS_NUM_REGS ; i++) {
- pmic_platform.reg_data[i] = ardbeg_reg_data[i];
- pmic_platform.reg_init[i] = ardbeg_reg_init[i];
- }
-
- i2c_register_board_info(4, palma_device,
- ARRAY_SIZE(palma_device));
- i2c_register_board_info(4, tps51632_cpu_boardinfo, 1);
- i2c_register_board_info(4, tps51632_gpu_boardinfo, 1);
- reg_init_data_ldo5.enable_tracking = true;
- reg_init_data_ldo5.tracking_regulator = PALMAS_REG_SMPS12;
} else if (pmu_board_info.board_id == BOARD_E1735) {
regulator_has_full_constraints();
ardbeg_tps65913_regulator_init();
} else if (pmu_board_info.board_id == BOARD_E1736) {
return tn8_regulator_init();
+ } else {
+ pr_warn("PMU board id 0x%04x is not supported\n",
+ pmu_board_info.board_id);
}
return 0;
FIXED_REG(1, usb0_vbus, usb0_vbus,
NULL, 0, 0, TEGRA_GPIO_PN4,
- false, true, 0, 5000, 0);
+ true, true, 0, 5000, 0);
-#ifdef CONFIG_ARCH_TEGRA_12x_SOC
FIXED_REG(2, usb1_vbus, usb1_vbus,
NULL, 0, 0, TEGRA_GPIO_PN5,
true, true, 0, 5000, 0);
FIXED_REG(3, usb2_vbus, usb2_vbus,
NULL, 0, 0, TEGRA_GPIO_PFF1,
- false, true, 0, 5000, 0);
-#else
-FIXED_REG(2, usb1_vbus, usb1_vbus,
- NULL, 0, 0, TEGRA_GPIO_PK6,
true, true, 0, 5000, 0);
-FIXED_REG(3, usb2_vbus, usb2_vbus,
- NULL, 0, 0, TEGRA_GPIO_PK5,
- false, true, 0, 5000, 0);
-#endif
-
FIXED_REG(4, vdd_sd, vdd_sd,
NULL, 0, 0, TEGRA_GPIO_PR0,
false, true, 0, 3300, 0);
AS3722_SUPPLY(sd5), 0, 0, PMU_TCA6416_GPIO(2),
false, true, 0, 1200, 0);
-#ifdef CONFIG_ARCH_TEGRA_11x_SOC
-FIXED_REG(12, vdd_hdmi_5v0, vdd_hdmi_5v0,
- NULL, 0, 0,
- TEGRA_GPIO_PH7, false, true, 0, 5000, 5000);
-#else
FIXED_REG(12, vdd_hdmi_5v0, vdd_hdmi_5v0,
NULL, 0, 0,
TEGRA_GPIO_PK6, false, true, 0, 5000, 5000);
-#endif
FIXED_REG(13, tca6408_p6, tca6408_p6,
AS3722_SUPPLY(sd5), 0, 0, PMU_TCA6416_GPIO(6),
NULL, 0, 1, -1,
false, true, 0, 1000, 0);
-/* Always ON /Battery regulator */
-static struct regulator_consumer_supply fixed_reg_en_battery_e1731_supply[] = {
- REGULATOR_SUPPLY("vdd_sys_bl", NULL),
- REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
- REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
- REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
-};
-
-static struct regulator_consumer_supply fixed_reg_en_vdd_cdc_1v2_supply[] = {
- REGULATOR_SUPPLY("vdd_cdc_1v2_aud", NULL),
-};
-
-static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v2_supply[] = {
- REGULATOR_SUPPLY("vdd_cdc_1v2_dis", NULL),
-};
-
-static struct regulator_consumer_supply fixed_reg_en_vdd_cdc_3v3a_supply[] = {
- REGULATOR_SUPPLY("vdd_cdc_3v3a_aud", NULL),
-};
-
-static struct regulator_consumer_supply fixed_reg_en_vdd_usb0_5v0_supply[] = {
- REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
- REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
- REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
- REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
-};
-
-static struct regulator_consumer_supply fixed_reg_en_vdd_dis_3v3a_supply[] = {
- REGULATOR_SUPPLY("vdd_dis_3v3_lcd", NULL),
- REGULATOR_SUPPLY("vdd_dis_3v3_lvds", NULL),
- REGULATOR_SUPPLY("avdd_lcd", NULL),
-};
-
-FIXED_REG(0, battery_e1731, battery_e1731,
- NULL, 0, 0,
- -1, false, true, 0, 3300, 0);
-
-FIXED_REG(1, vdd_cdc_1v2, vdd_cdc_1v2,
- palmas_rails(smps3), 0, 0,
- PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO14, false, true, 0, 1200,
- 0);
-
-FIXED_REG(2, vdd_lcd_1v2, vdd_lcd_1v2,
- palmas_rails(smps3), 1, 1,
- PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4, false, true, 0, 1200,
- 0);
-
-FIXED_REG(3, vdd_cdc_3v3a, vdd_cdc_3v3a,
- NULL, 0, 0,
- PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO10, false, true, 0, 3300,
- 0);
-
-FIXED_REG(4, vdd_usb0_5v0, vdd_usb0_5v0,
- NULL, 0, 0,
- TEGRA_GPIO_PN4, true, true, 0, 5000,
- 0);
-
-FIXED_REG(5, vdd_dis_3v3a, vdd_dis_3v3a,
- NULL, 1, 1,
- PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO3, true, true, 0, 3300,
- 0);
-
/*
* Creating fixed regulator device tables
*/
ADD_FIXED_REG(ti913_gpio7), \
ADD_FIXED_REG(vdd_cpu_fixed),
-#define ARBDEG_1731_COMMON_FIXED_REG \
- ADD_FIXED_REG(battery_e1731), \
- ADD_FIXED_REG(vdd_cdc_1v2), \
- ADD_FIXED_REG(vdd_lcd_1v2), \
- ADD_FIXED_REG(vdd_cdc_3v3a), \
- ADD_FIXED_REG(vdd_usb0_5v0), \
- ADD_FIXED_REG(vdd_dis_3v3a), \
- ADD_FIXED_REG(vdd_hdmi_5v0),
-
static struct platform_device *fixed_reg_devs_e1733[] = {
ARDBEG_COMMON_FIXED_REG
ARDBEG_E1733_FIXED_REG
ARDBEG_E1735_FIXED_REG
};
-static struct platform_device *pfixed_reg_devs[] = {
- ARBDEG_1731_COMMON_FIXED_REG
-};
-
/************************ ARDBEG CL-DVFS DATA *********************/
#define E1735_CPU_VDD_MAP_SIZE 33
#define E1735_CPU_VDD_MIN_UV 675000
#define E1735_CPU_VDD_STEP_UV 18750
+#define E1735_CPU_VDD_STEP_US 80
#define ARDBEG_DEFAULT_CVB_ALIGNMENT 10000
#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
/* Macro definition of dfll bypass device */
-#define DFLL_BYPASS(_board, _min, _step, _size) \
+#define DFLL_BYPASS(_board, _min, _step, _size, _us_sel) \
static struct regulator_init_data _board##_dfll_bypass_init_data = { \
.num_consumer_supplies = ARRAY_SIZE(_board##_dfll_bypass_consumers), \
.consumer_supplies = _board##_dfll_bypass_consumers, \
.uV_step = (_step), \
.linear_min_sel = 0, \
.n_voltages = (_size), \
+ .voltage_time_sel = _us_sel, \
}; \
static struct platform_device e1735_dfll_bypass_dev = { \
.name = "tegra_dfll_bypass", \
REGULATOR_SUPPLY("vdd_cpu", NULL),
};
DFLL_BYPASS(e1735, E1735_CPU_VDD_MIN_UV, E1735_CPU_VDD_STEP_UV,
- E1735_CPU_VDD_MAP_SIZE);
+ E1735_CPU_VDD_MAP_SIZE, E1735_CPU_VDD_STEP_US);
static struct tegra_cl_dvfs_platform_data e1735_cl_dvfs_data = {
.dfll_clk_name = "dfll_cpu",
__gpio_set_value(TEGRA_GPIO_PS5, 0); /* enable PWM buffer operations */
}
+static struct tegra_cl_dvfs_cfg_param e1733_ardbeg_cl_dvfs_param = {
+ .sample_rate = 12500,
+
+ .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
+ .cf = 10,
+ .ci = 0,
+ .cg = 2,
+
+ .droop_cut_value = 0xF,
+ .droop_restore_ramp = 0x0,
+ .scale_out_ramp = 0x0,
+};
+
+/* E1733 volatge map. Fixed 10mv steps from 700mv to 1400mv */
+#define E1733_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
+static struct voltage_reg_map e1733_cpu_vdd_map[E1733_CPU_VDD_MAP_SIZE];
+static inline void e1733_fill_reg_map(void)
+{
+ int i;
+ for (i = 0; i < E1733_CPU_VDD_MAP_SIZE; i++) {
+ e1733_cpu_vdd_map[i].reg_value = i + 0xa;
+ e1733_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
+ }
+}
+
+static struct tegra_cl_dvfs_platform_data e1733_cl_dvfs_data = {
+ .dfll_clk_name = "dfll_cpu",
+ .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
+ .u.pmu_i2c = {
+ .fs_rate = 400000,
+ .slave_addr = 0x80,
+ .reg = 0x00,
+ },
+ .vdd_map = e1733_cpu_vdd_map,
+ .vdd_map_size = E1733_CPU_VDD_MAP_SIZE,
+
+ .cfg_param = &e1733_ardbeg_cl_dvfs_param,
+};
+
static int __init ardbeg_cl_dvfs_init(u16 pmu_board_id)
{
struct tegra_cl_dvfs_platform_data *data = NULL;
}
}
+
+ if (pmu_board_id == BOARD_E1733) {
+ e1733_fill_reg_map();
+ data = &e1733_cl_dvfs_data;
+ }
+
if (data) {
data->flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
tegra_cl_dvfs_device.dev.platform_data = data;
tegra_get_pmu_board_info(&pmu_board_info);
ardbeg_cl_dvfs_init(pmu_board_info.board_id);
- if (pmu_board_info.board_id == BOARD_E1731)
- return platform_add_devices(pfixed_reg_devs,
- ARRAY_SIZE(pfixed_reg_devs));
- else if (pmu_board_info.board_id == BOARD_E1733)
+ if (pmu_board_info.board_id == BOARD_E1733)
return platform_add_devices(fixed_reg_devs_e1733,
ARRAY_SIZE(fixed_reg_devs_e1733));
else if (pmu_board_info.board_id == BOARD_E1735)
return platform_add_devices(fixed_reg_devs_e1735,
ARRAY_SIZE(fixed_reg_devs_e1735));
+ else
+ pr_warn("The PMU board id 0x%04x is not supported\n",
+ pmu_board_info.board_id);
return 0;
}
}
+static struct pid_thermal_gov_params soctherm_pid_params = {
+ .max_err_temp = 9000,
+ .max_err_gain = 1000,
-/* TO DO: set default governor for gpu throttling */
-/*
-static struct thermal_zone_params bonaire_soctherm_therm_gpu_tzp = {
- .governor_name = "pid_thermal_gov",
+ .gain_p = 1000,
+ .gain_d = 0,
+
+ .up_compensation = 20,
+ .down_compensation = 20,
};
-*/
+static struct thermal_zone_params soctherm_tzp = {
+ .governor_name = "pid_thermal_gov",
+ .governor_params = &soctherm_pid_params,
+};
-/* TO DO: This number will be changed post-silicon */
-/* sample table */
-/*
-static struct soctherm_platform_data bonaire_soctherm_data = {
+static struct soctherm_platform_data ardbeg_soctherm_data = {
.therm = {
[THERM_CPU] = {
.zone_enable = true,
.num_trips = 3,
.trips = {
{
- .cdev_type = "tegra-balanced",
- .trip_temp = 84000,
- .trip_type = THERMAL_TRIP_PASSIVE,
+ .cdev_type = "tegra-shutdown",
+ .trip_temp = 98000,
+ .trip_type = THERMAL_TRIP_CRITICAL,
.upper = THERMAL_NO_LIMIT,
.lower = THERMAL_NO_LIMIT,
},
{
.cdev_type = "tegra-heavy",
- .trip_temp = 94000,
+ .trip_temp = 96000,
.trip_type = THERMAL_TRIP_HOT,
.upper = THERMAL_NO_LIMIT,
.lower = THERMAL_NO_LIMIT,
},
{
- .cdev_type = "tegra-shutdown",
- .trip_temp = 104000,
- .trip_type = THERMAL_TRIP_CRITICAL,
+ .cdev_type = "tegra-balanced",
+ .trip_temp = 86000,
+ .trip_type = THERMAL_TRIP_PASSIVE,
.upper = THERMAL_NO_LIMIT,
.lower = THERMAL_NO_LIMIT,
},
},
[THERM_GPU] = {
.zone_enable = true,
- .num_trips = 3,
+ .passive_delay = 1000,
+ .hotspot_offset = 6000,
+ .num_trips = 2,
.trips = {
{
- .cdev_type = "gk20a_cdev",
- .trip_temp = 80000,
+ .cdev_type = "tegra-shutdown",
+ .trip_temp = 100000,
+ .trip_type = THERMAL_TRIP_CRITICAL,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ },
+ {
+ .cdev_type = "tegra-balanced",
+ .trip_temp = 88000,
.trip_type = THERMAL_TRIP_PASSIVE,
.upper = THERMAL_NO_LIMIT,
.lower = THERMAL_NO_LIMIT,
},
+/*
{
- .cdev_type = "tegra-heavy",
- .trip_temp = 90000,
- .trip_type = THERMAL_TRIP_HOT,
+ .cdev_type = "gk20a_cdev",
+ .trip_temp = 80000,
+ .trip_type = THERMAL_TRIP_PASSIVE,
.upper = THERMAL_NO_LIMIT,
.lower = THERMAL_NO_LIMIT,
},
{
- .cdev_type = "tegra-shutdown",
- .trip_temp = 102000,
- .trip_type = THERMAL_TRIP_CRITICAL,
+ .cdev_type = "tegra-heavy",
+ .trip_temp = 98000,
+ .trip_type = THERMAL_TRIP_HOT,
.upper = THERMAL_NO_LIMIT,
.lower = THERMAL_NO_LIMIT,
},
+*/
},
.tzp = &soctherm_tzp,
},
},
},
.throttle = {
- [THROTTLE_LIGHT] = {
- .priority = 0x0f,
- .devs = {
- [THROTTLE_DEV_CPU] = {
- .enable = false,
- },
- [THROTTLE_DEV_GPU] = {
- .enable = false,
- },
- },
- },
[THROTTLE_HEAVY] = {
- .priority = 0xf0,
+ .priority = 100,
.devs = {
[THROTTLE_DEV_CPU] = {
.enable = true,
.depth = 80,
},
[THROTTLE_DEV_GPU] = {
- .enable = true,
+ .enable = false,
.throttling_depth = "heavy_throttling",
},
},
},
- [THROTTLE_OC1] = {
- },
},
};
-int __init bonaire_soctherm_init(void)
+int __init ardbeg_soctherm_init(void)
{
- return tegra11_soctherm_init(&bonaire_soctherm_data);
+ /* do this only for supported CP,FT fuses */
+ if (!tegra_fuse_calib_base_get_cp(NULL, NULL) &&
+ !tegra_fuse_calib_base_get_ft(NULL, NULL)) {
+ tegra_platform_edp_init(
+ ardbeg_soctherm_data.therm[THERM_CPU].trips,
+ &ardbeg_soctherm_data.therm[THERM_CPU].num_trips,
+ 8000); /* edp temperature margin */
+ return tegra11_soctherm_init(&ardbeg_soctherm_data);
+ }
+
+ return -EINVAL;
}
-*/