bool "Enable support for Tegra20 family"
depends on !ARCH_TEGRA_3x_SOC
depends on !ARCH_TEGRA_11x_SOC
+ depends on !ARCH_TEGRA_12x_SOC
depends on !ARCH_TEGRA_14x_SOC
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
- select ARCH_SUPPORTS_MSI if TEGRA_PCI
+ select ARCH_SUPPORTS_MSI if PCI_TEGRA
select ARCH_TEGRA_HAS_ARM_SCU
select ARCH_TEGRA_HAS_PCIE
select ARM_CPU_SUSPEND if PM
select CPA
select CPU_FREQ_TABLE if CPU_FREQ
select CPU_V7
- select NVMAP_CACHE_MAINT_BY_SET_WAYS
- select NVMAP_DEFERRED_CACHE_MAINT
- select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS
- select PCI_MSI if TEGRA_PCI
+ select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
+ select NVMAP_DEFERRED_CACHE_MAINT if TEGRA_NVMAP
+ select NVMAP_HANDLE_MARSHAL if TEGRA_NVMAP
+ select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
+ select PCI_MSI if PCI_TEGRA
select PINCTRL
select PINCTRL_TEGRA20
+ select POWER_RESET
+ select SYSTEM_PMIC
select PL310_ERRATA_769419 if CACHE_L2X0
select PM_GENERIC_DOMAINS if PM
select SOC_BUS
config ARCH_TEGRA_3x_SOC
bool "Enable support for Tegra30 family"
depends on !ARCH_TEGRA_11x_SOC
+ depends on !ARCH_TEGRA_12x_SOC
depends on !ARCH_TEGRA_14x_SOC
- select ARCH_SUPPORTS_MSI if TEGRA_PCI
+ select ARCH_SUPPORTS_MSI if PCI_TEGRA
select ARCH_TEGRA_HAS_ARM_SCU
select ARCH_TEGRA_HAS_PCIE
select ARCH_TEGRA_HAS_SATA
select CPU_FREQ_TABLE if CPU_FREQ
select CPU_V7
select GIC_SET_MULTIPLE_CPUS if SMP
- select NVMAP_CACHE_MAINT_BY_SET_WAYS
- select NVMAP_DEFERRED_CACHE_MAINT
- select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS
- select PCI_MSI if TEGRA_PCI
+ select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
+ select NVMAP_DEFERRED_CACHE_MAINT if TEGRA_NVMAP
+ select NVMAP_HANDLE_MARSHAL if TEGRA_NVMAP
+ select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
+ select PCI_MSI if PCI_TEGRA
select PINCTRL
select PINCTRL_TEGRA30
+ select POWER_RESET
+ select SYSTEM_PMIC
select PL310_ERRATA_727915
select PL310_ERRATA_769419 if CACHE_L2X0
select PM_GENERIC_DOMAINS if PM
select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
select SOC_BUS
- select TEGRA_ERRATA_1053704
- select TEGRA_LATENCY_ALLOWANCE
- select TEGRA_LATENCY_ALLOWANCE_SCALING
+ select TEGRA_ERRATA_1053704 if TEGRA_IOMMU_SMMU
select TEGRA_LP2_CPU_TIMER if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB_PHY
config ARCH_TEGRA_11x_SOC
bool "Tegra 11x family SOC"
+ depends on !ARCH_TEGRA_12x_SOC
depends on !ARCH_TEGRA_14x_SOC
select ARCH_HAS_PASR
- select ARCH_REQUIRE_GPIOLIB
select ARCH_TEGRA_4GB_MEMORY
select ARCH_TEGRA_HAS_CL_DVFS
select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
- select ARM_ARCH_TIMER
select ARM_CPU_SUSPEND if PM
select ARM_ERRATA_798181
select ARM_ERRATA_799270
select ARM_L1_CACHE_SHIFT_6
select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
select CPU_V7
- select NVMAP_CACHE_MAINT_BY_SET_WAYS
- select NVMAP_DEFERRED_CACHE_MAINT
+ select HAVE_ARM_ARCH_TIMER
+ select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
+ select NVMAP_CACHE_MAINT_BY_SET_WAYS_ON_ONE_CPU if TEGRA_NVMAP
+ select NVMAP_DEFERRED_CACHE_MAINT if TEGRA_NVMAP
+ select NVMAP_HANDLE_MARSHAL if TEGRA_NVMAP
select PINCTRL
+ select PINCTRL_TEGRA114
+ select POWER_RESET
+ select SYSTEM_PMIC
select PM_GENERIC_DOMAINS if PM
select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
select SOC_BUS
select TEGRA_DUAL_CBUS
select TEGRA_CORE_EDP_LIMITS
select TEGRA_ERRATA_977223
- select TEGRA_ERRATA_1053704
+ select TEGRA_ERRATA_1053704 if TEGRA_IOMMU_SMMU
select TEGRA_ERRATA_1157520
select TEGRA_ISOMGR
select TEGRA_ISOMGR_SYSFS
- select TEGRA_LATENCY_ALLOWANCE
select TEGRA_LP2_CPU_TIMER if !TEGRA_RAIL_OFF_MULTIPLE_CPUS
select TEGRA_MC_PTSA if !TEGRA_FPGA_PLATFORM
- select TEGRA_THERMAL_THROTTLE_EXACT_FREQ
select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_EHCI_TEGRA if USB_SUPPORT
select USB_ULPI if USB_SUPPORT
select USB_ULPI_VIEWPORT if USB_SUPPORT
+ select PROC_DEVICETREE
help
Support for NVIDIA Tegra 11x family of SoCs, based upon the
ARM Cortex-A15MP CPU
-config ARCH_TEGRA_HAS_ARM_SCU
- bool
+config ARCH_TEGRA_12x_SOC
+ bool "Tegra 12x family SOC"
+ depends on !ARCH_TEGRA_14x_SOC
+ select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
+ select ARCH_TEGRA_HAS_PCIE
+ select CPU_V7
+ select ARM_L1_CACHE_SHIFT_6
+ select ARM_ARCH_TIMER
+ select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
+ select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
+ select ARM_CPU_SUSPEND if PM
+ select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
+ select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
+ select ARM_GIC
+ select ARCH_REQUIRE_GPIOLIB
+ select USB_ARCH_HAS_EHCI if USB_SUPPORT
+ select USB_EHCI_TEGRA if USB_SUPPORT
+ select USB_ULPI if USB_SUPPORT
+ select USB_ULPI_VIEWPORT if USB_SUPPORT
+ select USE_OF
+ select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
+ select TEGRA_LP2_CPU_TIMER if !TEGRA_RAIL_OFF_MULTIPLE_CPUS
+ select ARCH_SUPPORTS_MSI if PCI_TEGRA
+ select PCI_MSI if PCI_TEGRA
+ select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
+ select NVMAP_CACHE_MAINT_BY_SET_WAYS_ON_ONE_CPU if TEGRA_NVMAP
+ select NVMAP_DEFERRED_CACHE_MAINT if TEGRA_NVMAP
+ select NVMAP_HANDLE_MARSHAL if TEGRA_NVMAP
+ select ARCH_TEGRA_HAS_CL_DVFS
+ select TEGRA_DUAL_CBUS
+ select SOC_BUS
+ select THERMAL
+ select PM_GENERIC_DOMAINS if PM
+ select PINCTRL
+ select PINCTRL_TEGRA124
+ select POWER_RESET
+ select SYSTEM_PMIC
+ select TEGRA_DC_TEMPORAL_DITHER
+ select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE
+ select REGULATOR_TEGRA_DFLL_BYPASS
+ select HAVE_ARM_ARCH_TIMER
+ select ARCH_HAS_PASR
+ select POWER_SUPPLY
+ select TEGRA_ISOMGR
+ select TEGRA_ISOMGR_SYSFS
+ select PROC_DEVICETREE
+ select TEGRA_USE_SIMON
+ help
+ Support for NVIDIA Tegra 12x family of SoCs, based upon the
+ ARM Cortex-A15MP CPU
config ARCH_TEGRA_14x_SOC
bool "Tegra 14x family SOC"
select ARM_GIC
select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
select PINCTRL
+ select POWER_RESET
+ select SYSTEM_PMIC
select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
select CPA
select CPU_V7
- select EDP_FRAMEWORK
select GIC_SET_MULTIPLE_CPUS if SMP
- select NVMAP_CACHE_MAINT_BY_SET_WAYS
- select NVMAP_DEFERRED_CACHE_MAINT
- select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS
+ select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
+ select NVMAP_DEFERRED_CACHE_MAINT if TEGRA_NVMAP
+ select NVMAP_HANDLE_MARSHAL if TEGRA_NVMAP
+ select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
select PM_GENERIC_DOMAINS if PM
select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
select SOC_BUS
select TEGRA_DISABLE_BBC_LATENCY_ALLOWANCE
select TEGRA_DUAL_CBUS
select TEGRA_ERRATA_977223
- select TEGRA_ERRATA_1053704
+ select TEGRA_ERRATA_1053704 if TEGRA_IOMMU_SMMU
select TEGRA_ERRATA_1213083
select TEGRA_ERRATA_1252872
select TEGRA_ISOMGR
select TEGRA_ISOMGR_SYSFS
select TEGRA_LP2_CPU_TIMER if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS
+ select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_EHCI_TEGRA if USB_SUPPORT
select USB_ULPI if USB_SUPPORT
Support for NVIDIA Tegra 14x family of SoCs, based upon the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
+config TEGRA_NO_CARVEOUT
+ bool "Disable Tegra carveout"
+ default n
+
+config ARCH_TEGRA_HAS_ARM_SCU
+ bool
+
config ARCH_TEGRA_HAS_DUAL_3D
bool
config ARCH_TEGRA_HAS_CL_DVFS
bool
-config TEGRA_PCI
- bool "PCIe host controller driver"
- select PCI
- depends on ARCH_TEGRA_HAS_PCIE
- help
- Adds PCIe Host controller driver for tegra based systems
-
-config TEGRA_PCIE_SKIP_POWERGATING
- bool "Skip PCIE powergating"
- depends on TEGRA_PCI
- help
- Do not powergate PCIE partition on boot up.
-
config TEGRA_AHB
bool "Enable AHB driver for NVIDIA Tegra SoCs"
default y
comment "Tegra board type"
-config MACH_CURACAO
- bool "Curacao board"
- depends on ARCH_TEGRA_11x_SOC
- select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
+config MACH_BONAIRE
+ bool "Bonaire board"
+ depends on ARCH_TEGRA_12x_SOC
select TEGRA_FPGA_PLATFORM
help
- Support for NVIDIA Curacao FPGA development platform
+ Support for NVIDIA Bonaire FPGA development platform
+
+config MACH_ARDBEG
+ bool "ARDBEG board"
+ depends on ARCH_TEGRA_12x_SOC || ARCH_TEGRA_11x_SOC
+ select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
+ select MACH_HAS_SND_SOC_TEGRA_RT5645 if SND_SOC
+ select SYSEDP_FRAMEWORK
+ help
+ Support for NVIDIA ARDBEG Development platform
+
+config MACH_LOKI
+ bool "Loki board"
+ depends on ARCH_TEGRA_12x_SOC
+ select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
+ select MACH_HAS_SND_SOC_TEGRA_RT5645 if SND_SOC
+ help
+ Support for NVIDIA LOKI Development platform
+
+config MACH_VCM30_T124
+ bool "VCM30_T124(Automotive) board"
+ depends on ARCH_TEGRA_12x_SOC
+ help
+ Support for NVIDIA VCM30_T124 Automotive Development platform
+config MACH_LAGUNA
+ bool "LAGUNA board"
+ depends on ARCH_TEGRA_12x_SOC || ARCH_TEGRA_11x_SOC
+ select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
+ select MACH_HAS_SND_SOC_TEGRA_RT5645 if SND_SOC
+ help
+ Support for NVIDIA LAGUNA Development platform
config MACH_DALMORE
bool "Dalmore board"
depends on ARCH_TEGRA_11x_SOC
select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
- select EDP_FRAMEWORK
help
Support for NVIDIA MACALLAN development platform
depends on ARCH_TEGRA_11x_SOC
select MACH_HAS_SND_SOC_TEGRA_CS42L73 if SND_SOC
select MACH_HAS_SND_SOC_TEGRA_TLV320AIC326X if SND_SOC
- select EDP_FRAMEWORK
help
Support for NVIDIA PLUTO development platform
bool "Simulation"
select TEGRA_PRE_SILICON_SUPPORT
select LESS_GCC_OPT if DEBUG_KERNEL
+ select READABLE_ASM if DEBUG_KERNEL
+ select TEGRA_SIMULATION_SPLIT_MEM
help
This enables support for a Tegra simulation platform.
Select this only if you are an NVIDIA developer working
config TEGRA_FPGA_PLATFORM
bool "FPGA"
select TEGRA_PRE_SILICON_SUPPORT
+ select LESS_GCC_OPT if DEBUG_KERNEL
+ select READABLE_ASM if DEBUG_KERNEL
help
This enables support for a Tegra FPGA platform.
Select this only if you are an NVIDIA developer working
Select this only if you are an NVIDIA developer working on
FPGA, Emulation or Simulation.
+config TEGRA_SIMULATION_SPLIT_MEM
+ bool "Tegra Simulation Split Memory Configuration"
+ default n
+ help
+ This enables support for a Tegra split memory
+ simulation. It can be used as part of ASIM/QT test
+ setup. Select this only if you are an NVIDIA developer
+ working on a simulation platform.
+
config TEGRA_FIQ_DEBUGGER
bool "Enable the FIQ serial debugger on Tegra"
default n
help
Enables the FIQ serial debugger on Tegra
+config TEGRA_PTM
+ bool "Enable PTM debugger on Tegra"
+ default n
+ help
+ This option enables PTM debugger on Tegra. This driver is used
+ for tracking each branch instructions executed by processor. It
+ can save such tracking information to the ETB buffer, which can
+ be further parsed by a user space program to re-construct the
+ complete program flows.
+
config TEGRA_EMC_SCALING_ENABLE
bool "Enable scaling the memory frequency"
- depends on TEGRA_SILICON_PLATFORM
default n
config TEGRA_CPU_DVFS
bool "Enable voltage scaling on Tegra CPU"
- depends on TEGRA_SILICON_PLATFORM
default y
config TEGRA_CORE_DVFS
bool "Enable voltage scaling on Tegra core"
- depends on TEGRA_SILICON_PLATFORM
depends on TEGRA_CPU_DVFS
default y
+config TEGRA_GPU_DVFS
+ bool "Enable voltage scaling on Tegra GPU"
+ depends on TEGRA_SILICON_PLATFORM
+ depends on ARCH_TEGRA_12x_SOC
+ default y
+
+config TEGRA_GK20A
+ bool "Enable the GK20A GPU on Tegra"
+ depends on ARCH_TEGRA_12x_SOC
+ depends on TEGRA_GRHOST
+ select GK20A
+ default y
+ help
+ Enable support for the GK20A graphics engine on Tegra
+ by adding a Tegra platfrom interface to the GK20A driver.
+ The Tegra platform interface requires TEGRA_GRHOST (host1x).
+
config TEGRA_AVP_KERNEL_ON_MMU
bool "Use AVP MMU to relocate AVP kernel"
depends on ARCH_TEGRA_2x_SOC
config TEGRA_THERMAL_THROTTLE
bool "Enable throttling of CPU speed on overtemp"
- depends on TEGRA_SILICON_PLATFORM
depends on CPU_FREQ
depends on THERMAL
default y
config TEGRA_THERMAL_THROTTLE_EXACT_FREQ
bool "Use exact cpu frequency capping when thermal throttling"
depends on TEGRA_THERMAL_THROTTLE
+ default y if TEGRA_THERMAL_THROTTLE
default n
help
When this option is enabled, the cpu will run at the exact
depends on DEBUG_FS
default n
+config TEGRA_CLOCK_DEBUG_FUNC
+ bool "Enable extra debug functions to access to clock tree"
+ depends on TEGRA_CLOCK_DEBUG_WRITE
+ default n
+
config TEGRA_CLUSTER_CONTROL
bool
depends on ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
config TEGRA_EDP_LIMITS
bool "Enforce electrical design limits on CPU rail"
- depends on TEGRA_SILICON_PLATFORM
depends on CPU_FREQ
depends on THERMAL
default y if ARCH_TEGRA_3x_SOC
of on-line CPUs to keep CPU rail current within power supply
capabilities.
+config TEGRA_CPU_EDP_FIXED_LIMITS
+ bool "Enforce fixed EDP limits on CPU rail per chip SKU"
+ depends on ARCH_TEGRA_11x_SOC
+ depends on TEGRA_EDP_LIMITS
+ default n
+ help
+ Enforce CPU EDP frequency limits which are fixed for a given
+ chip SKU. By default, the max frequency is determined optimally
+ for each individual chip.
+
+config TEGRA_GPU_EDP
+ bool "enable GPU EDP "
+ depends on THERMAL
+ depends on TEGRA_EDP_LIMITS
+ depends on ARCH_TEGRA_12x_SOC
+ default n
+ help
+ Limit maximum GPU frequency based on temperature
+ to keep GPU rail current within power supply
+ capabilities.
+
+config TEGRA_CPU_VOLT_CAP
+ bool "Allow cpu voltage to be capped based on usage metrics."
+ depends on TEGRA_EDP_LIMITS
+ default n
+ help
+ Provide userspace with an interface to dynamically adjust
+ CPU <voltage, temperature> cap. Userspace must respect
+ datasheet-imposed limits.
+
+config CONFIG_TEGRA_CORE_CAP
+ bool "Control core capping limits"
+ default y
+ help
+ Provide userspace control of floor and caps via sysfs and QoS
+ interface.
+
+
config TEGRA_EMC_TO_DDR_CLOCK
int "EMC to DDR clocks ratio"
default "2" if ARCH_TEGRA_2x_SOC
range 0 1300 if ARCH_TEGRA_3x_SOC
range 0 1800 if ARCH_TEGRA_11x_SOC
range 0 2000 if ARCH_TEGRA_14x_SOC
+ range 0 2000 if ARCH_TEGRA_12x_SOC
default 0
help
Devices need to boost frequency of CPU when they are connected
range 0 1300 if ARCH_TEGRA_3x_SOC
range 0 1800 if ARCH_TEGRA_11x_SOC
range 0 2000 if ARCH_TEGRA_14x_SOC
+ range 0 2000 if ARCH_TEGRA_12x_SOC
default 0
help
This value is the amount of the cpu frequency (in Mhz)
config TEGRA_DYNAMIC_PWRDET
bool "Enable dynamic activation of IO level auto-detection"
- depends on TEGRA_SILICON_PLATFORM
default n
help
This option allows turning off tegra IO level auto-detection
send out wakeup source and uevents which indicate suspend_prepare and
post_suspend.
+config TEGRA_INTERNAL_USB_CABLE_WAKE_SUPPORT
+ bool "Enable Tegra internal USB cable wake support"
+ depends on PM_SLEEP
+ default n
+ help
+ Enables Tegra suspend wakeup with USB cable through Tegra
+ integrated hardware. Enabled for selected Tegra chipsets.
+ This feature allows wakeup from suspend using either
+ device or host type USB cable.
+
config TEGRA_BB_XMM_POWER
bool "Enable power driver for XMM modem"
default n
and Latency Allowance settings. Additional setting adjustments
can be done from user space through sysfs.
+config TEGRA_BBC_THERMAL
+ bool "Enable BBC Thermal reporting support"
+ depends on NVSHM
+ depends on TEGRA_BBC_PROXY
+ default y
+ help
+ Enables the reporting of BBC-managed temperature sensors values as
+ thermal zones. This uses the statistics framework where the data
+ reside, and thus depends on the NVSHM driver to provides the API to
+ browse the BBC statistics and be notified of modem [re-]boot.
+
config TEGRA_PLLM_RESTRICTED
bool "Restrict PLLM usage as module clock source"
depends on !ARCH_TEGRA_2x_SOC
help
Enable support for LP1 Core voltage to set to lowest
-config TEGRA_LATENCY_ALLOWANCE
- bool "Allow memory clients to configure latency allowance"
- help
- Latency allowance is a per-memory-client setting that tells the
- memory controller how long it can ignore a request in favor of
- others. In other words, It indicates how long a request from specific
- memory client can wait before it is served.
- Enabling this option allows memory clients configure the
- latency allowance as per their bandwidth requirement.
-
-config TEGRA_LATENCY_ALLOWANCE_SCALING
- bool "Enable latency allowance scaling"
- depends on TEGRA_LATENCY_ALLOWANCE
- help
- Enables latency allowance scaling, which enables scaling
- programmed latency allowance values based on fifo threshold levels
- set for for display and vi hardware.
-
config TEGRA_DISABLE_BBC_LATENCY_ALLOWANCE
bool "Disable BBCRW latency allowance"
- depends on TEGRA_LATENCY_ALLOWANCE
help
Disables BBCRW latency allowance configuration by
clients. The BBCRW latency allowance would remain
config TEGRA_MC_PTSA
bool "Enable MC PTSA programming"
- depends on TEGRA_LATENCY_ALLOWANCE
help
Enables Priority Tier Snap Arbiter programming in
Memory Controller. PTSA is a Memory Controller feature that
int "Default CPU DFLL operating range"
depends on ARCH_TEGRA_HAS_CL_DVFS
range 0 2
- default "1" if TEGRA_SILICON_PLATFORM
- default "0"
+ default "2" if TEGRA_SILICON_PLATFORM && ARCH_TEGRA_11x_SOC
+ default "1"
help
Defines default range for dynamic frequency lock loop (DFLL)
to be used as CPU clock source:
"2" - DFLL is used only for high rates above crossover with
PLL dvfs curve
+config REGULATOR_TEGRA_DFLL_BYPASS
+ bool "Use dfll bypass regulator"
+ depends on ARCH_TEGRA_HAS_CL_DVFS
+ default n
+ help
+ Enables use of dfll bypass interfaces for voltage control
+ by s/w driver.
+
config TEGRA_TIMER_HZ
int "Kernel HZ (jiffies per second)"
- default "100" if TEGRA_FPGA_PLATFORM
+ default "100" if TEGRA_PRE_SILICON_SUPPORT
default "1000"
config TEGRA_SOCTHERM
bool "Enable soctherm"
- depends on ARCH_TEGRA_11x_SOC || ARCH_TEGRA_14x_SOC
+ depends on ARCH_TEGRA_11x_SOC || ARCH_TEGRA_14x_SOC || ARCH_TEGRA_12x_SOC
default y
help
Enables use of soctherm for thermal management.
provides a backup memory clock while PLLM is re-locking to the
new rate.
+config ARCH_TEGRA_VIC
+ bool "Tegra Video Image Compositor present"
+ default y
+ help
+ Say Y here if the SOC supports the Tegra Video Image Compositor.
+ Note that this not the same as the ARM Vectored Interrupt Controller.
+
config TEGRA_MC_DOMAINS
bool "Enable MC domains"
depends on PM_GENERIC_DOMAINS
bool "Enable core rail override support"
depends on TEGRA_SILICON_PLATFORM
default n
+ select CONFIG_TEGRA_CORE_CAP
help
When enabled, core rail can be fixed and locked at specified voltage
within override range, and core modules clocks are capped at rates
safe at override level.
+
+config TEGRA_GMI
+ bool
+
+config TEGRA_SOC_TIMERS
+ bool "Enable support for SOC timers"
+ default n
+ help
+ When enabled, cpu clock events will be using SOC timers instead
+ of arm private timers.
+
+config TEGRA_LP0_IN_IDLE
+ bool "Enable support LP0-in-idle state"
+ default n
+
+config TEGRA_HDMI_PRIMARY
+ bool "Use HDMI as primary display"
+ depends on TEGRA_DC
+ depends on !FRAMEBUFFER_CONSOLE
+ help
+ Configure system to support HDMI as the primary display.
+ When enabled, dispA/fb0 will be configured to use HDMI.
+
+config TEGRA_USE_SIMON
+ bool "Use Tegra Silicon Monitor"
+ default n
+ help
+ Enable Tegra silicon state monitoring, grading, and notification.
endif