bool "Enable support for Tegra20 family"
depends on !ARCH_TEGRA_3x_SOC
depends on !ARCH_TEGRA_11x_SOC
+ depends on !ARCH_TEGRA_12x_SOC
depends on !ARCH_TEGRA_14x_SOC
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
select ARCH_SUPPORTS_MSI if TEGRA_PCI
config ARCH_TEGRA_3x_SOC
bool "Enable support for Tegra30 family"
depends on !ARCH_TEGRA_11x_SOC
+ depends on !ARCH_TEGRA_12x_SOC
depends on !ARCH_TEGRA_14x_SOC
select ARCH_SUPPORTS_MSI if TEGRA_PCI
select ARCH_TEGRA_HAS_ARM_SCU
select PM_GENERIC_DOMAINS if PM
select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
select SOC_BUS
- select TEGRA_LATENCY_ALLOWANCE
- select TEGRA_LATENCY_ALLOWANCE_SCALING
+ select TEGRA_ERRATA_1053704
select TEGRA_LP2_CPU_TIMER if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB_PHY
config ARCH_TEGRA_11x_SOC
bool "Tegra 11x family SOC"
+ depends on !ARCH_TEGRA_12x_SOC
depends on !ARCH_TEGRA_14x_SOC
- select ARCH_REQUIRE_GPIOLIB
+ select ARCH_HAS_PASR
select ARCH_TEGRA_4GB_MEMORY
select ARCH_TEGRA_HAS_CL_DVFS
select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
- select ARM_ARCH_TIMER
select ARM_CPU_SUSPEND if PM
+ select ARM_ERRATA_798181
+ select ARM_ERRATA_799270
select ARM_GIC
select ARM_L1_CACHE_SHIFT_6
select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
- select CPA
select CPU_V7
+ select HAVE_ARM_ARCH_TIMER
select NVMAP_CACHE_MAINT_BY_SET_WAYS
select NVMAP_DEFERRED_CACHE_MAINT
select PINCTRL
select TEGRA_DUAL_CBUS
select TEGRA_CORE_EDP_LIMITS
select TEGRA_ERRATA_977223
+ select TEGRA_ERRATA_1053704
select TEGRA_ERRATA_1157520
select TEGRA_ISOMGR
select TEGRA_ISOMGR_SYSFS
- select TEGRA_ISOMGR_DEBUG
- select TEGRA_LATENCY_ALLOWANCE
select TEGRA_LP2_CPU_TIMER if !TEGRA_RAIL_OFF_MULTIPLE_CPUS
select TEGRA_MC_PTSA if !TEGRA_FPGA_PLATFORM
select TEGRA_THERMAL_THROTTLE_EXACT_FREQ
+ select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_EHCI_TEGRA if USB_SUPPORT
select USB_ULPI if USB_SUPPORT
Support for NVIDIA Tegra 11x family of SoCs, based upon the
ARM Cortex-A15MP CPU
-config ARCH_TEGRA_HAS_ARM_SCU
- bool
+config ARCH_TEGRA_12x_SOC
+ bool "Tegra 12x family SOC"
+ depends on !ARCH_TEGRA_14x_SOC
+ select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
+ select ARCH_TEGRA_HAS_PCIE
+ select CPU_V7
+ select ARM_L1_CACHE_SHIFT_6
+ select ARM_ARCH_TIMER
+ select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
+ select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
+ select ARM_CPU_SUSPEND if PM
+ select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
+ select ARM_GIC
+ select ARCH_REQUIRE_GPIOLIB
+ select USB_ARCH_HAS_EHCI if USB_SUPPORT
+ select USB_EHCI_TEGRA if USB_SUPPORT
+ select USB_ULPI if USB_SUPPORT
+ select USB_ULPI_VIEWPORT if USB_SUPPORT
+ select USE_OF
+ select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
+ select ARCH_SUPPORTS_MSI if TEGRA_PCI
+ select PCI_MSI if TEGRA_PCI
+ select ARCH_TEGRA_HAS_CL_DVFS
+ select TEGRA_DYNAMIC_CBUS
+ select TEGRA_DUAL_CBUS
+ select ARCH_TEGRA_VIC
+ select SOC_BUS
+ select THERMAL
+ select PM_GENERIC_DOMAINS if PM
+ help
+ Support for NVIDIA Tegra 12x family of SoCs, based upon the
+ ARM Cortex-A15MP CPU
config ARCH_TEGRA_14x_SOC
bool "Tegra 14x family SOC"
+ select ARCH_HAS_PASR
select ARCH_TEGRA_HAS_ARM_SCU
select ARCH_TEGRA_HAS_CL_DVFS
select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
select ARM_CPU_SUSPEND if PM
+ select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_GIC
select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
- select ARM_SMP_TWD
select PINCTRL
select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
+ select CPA
select CPU_V7
select EDP_FRAMEWORK
select GIC_SET_MULTIPLE_CPUS if SMP
select PM_GENERIC_DOMAINS if PM
select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
select SOC_BUS
+ select TEGRA_DISABLE_BBC_LATENCY_ALLOWANCE
select TEGRA_DUAL_CBUS
- select TEGRA_EDP_LIMITS
+ select TEGRA_ERRATA_977223
+ select TEGRA_ERRATA_1053704
+ select TEGRA_ERRATA_1213083
+ select TEGRA_ERRATA_1252872
select TEGRA_ISOMGR
+ select TEGRA_ISOMGR_SYSFS
select TEGRA_LP2_CPU_TIMER if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_EHCI_TEGRA if USB_SUPPORT
Support for NVIDIA Tegra 14x family of SoCs, based upon the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
+config ARCH_TEGRA_HAS_ARM_SCU
+ bool
+
config ARCH_TEGRA_HAS_DUAL_3D
bool
help
Adds PCIe Host controller driver for tegra based systems
+config TEGRA_PCIE_SKIP_POWERGATING
+ bool "Skip PCIE powergating"
+ depends on TEGRA_PCI
+ help
+ Do not powergate PCIE partition on boot up.
+
config TEGRA_AHB
bool "Enable AHB driver for NVIDIA Tegra SoCs"
default y
help
Support for NVIDIA Curacao FPGA development platform
+config MACH_BONAIRE
+ bool "Bonaire board"
+ depends on ARCH_TEGRA_12x_SOC
+ select TEGRA_FPGA_PLATFORM
+ help
+ Support for NVIDIA Bonaire FPGA development platform
config MACH_DALMORE
bool "Dalmore board"
help
Support for NVIDIA PISMO development platform
+config MACH_MACALLAN
+ bool "Macallan board"
+ depends on ARCH_TEGRA_11x_SOC
+ select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
+ select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
+ select EDP_FRAMEWORK
+ help
+ Support for NVIDIA MACALLAN development platform
+
config MACH_TEGRA_PLUTO
bool "Pluto board"
depends on ARCH_TEGRA_11x_SOC
bool "Simulation"
select TEGRA_PRE_SILICON_SUPPORT
select LESS_GCC_OPT if DEBUG_KERNEL
+ select READABLE_ASM if DEBUG_KERNEL
+ select TEGRA_SIMULATION_SPLIT_MEM
help
This enables support for a Tegra simulation platform.
Select this only if you are an NVIDIA developer working
config TEGRA_FPGA_PLATFORM
bool "FPGA"
select TEGRA_PRE_SILICON_SUPPORT
+ select LESS_GCC_OPT if DEBUG_KERNEL
+ select READABLE_ASM if DEBUG_KERNEL
help
This enables support for a Tegra FPGA platform.
Select this only if you are an NVIDIA developer working
Select this only if you are an NVIDIA developer working on
FPGA, Emulation or Simulation.
+config TEGRA_SIMULATION_SPLIT_MEM
+ bool "Tegra Simulation Split Memory Configuration"
+ default n
+ help
+ This enables support for a Tegra split memory
+ simulation. It can be used as part of ASIM/QT test
+ setup. Select this only if you are an NVIDIA developer
+ working on a simulation platform.
+
config TEGRA_FIQ_DEBUGGER
bool "Enable the FIQ serial debugger on Tegra"
default n
config TEGRA_CPU_DVFS
bool "Enable voltage scaling on Tegra CPU"
depends on TEGRA_SILICON_PLATFORM
- depends on !ARCH_TEGRA_14x_SOC
default y
config TEGRA_CORE_DVFS
depends on TEGRA_CPU_DVFS
default y
+config TEGRA_GK20A
+ bool "Enable the GK20A graphics engine"
+ depends on ARCH_TEGRA_12x_SOC
+ default y
+ help
+ Enable support for the GK20A graphics engine
+
config TEGRA_AVP_KERNEL_ON_MMU
bool "Use AVP MMU to relocate AVP kernel"
depends on ARCH_TEGRA_2x_SOC
config TEGRA_AVP_KERNEL_ON_SMMU
bool "Use SMMU to relocate AVP kernel"
- depends on TEGRA_IOVMM_SMMU
+ depends on TEGRA_IOVMM_SMMU || TEGRA_IOMMU_SMMU
default y
help
Use SMMU to relocate AVP kernel (nvrm_avp.bin).
controller. This feature is used to improve CPU memory
write performance.
+config TEGRA_ERRATA_1252872
+ bool "DLL experiences internal sychronization issue"
+ depends on ARCH_TEGRA_14x_SOC
+ help
+ The digital DLL in the T148 A01 chip has an internal synchronization
+ issue that can lead to reading invalid results. These invalid results
+ are returned when multiple bits change in one calibration value to
+ the next. To work around this a two step process is used: (1) the DLL
+ is enabled and locked (but not sampled); and (2) the DLL clock is
+ disabled and the internal state machine is reinvoked (and then
+ sampled). This requires that the DLL is never placed in a continuous
+ running mode.
+
+config TEGRA_ERRATA_1213083
+ bool "HOTRESET_STAT can return invalid status"
+ depends on ARCH_TEGRA_14x_SOC
+ help
+ On T14x it is possible to read the HOTRESET_STAT register before
+ the HW has had a chance to transition into the flush state. Thus
+ the flush status appears to be done. This errata adds a small delay
+ (at least 25 mcclk cycles) before polling the HOTRESET_STAT register.
+
config TEGRA_ERRATA_1157520
bool "Memory writes are not consistent/ordered from CPU"
depends on ARCH_TEGRA_11x_SOC
config TEGRA_ERRATA_977223
bool "PTSA ring 1 to ring 0 does not account for forced coalescing"
- depends on ARCH_TEGRA_11x_SOC
+ depends on ARCH_TEGRA_11x_SOC || ARCH_TEGRA_14x_SOC
help
The forced coalescing logic will "drop" the first request of the
coalesced pair after the ring 1 snap arbiter. This means that for
default "1"
config TEGRA_GADGET_BOOST_CPU_FREQ
- int "Boost cpu frequency for tegra usb gadget (0-1300 mhz)"
- range 0 1300
+ int "Boost cpu frequency for tegra usb gadget"
+ range 0 1300 if ARCH_TEGRA_3x_SOC
+ range 0 1800 if ARCH_TEGRA_11x_SOC
+ range 0 2000 if ARCH_TEGRA_14x_SOC
default 0
help
Devices need to boost frequency of CPU when they are connected
to host pc through usb cable for better performance. This value
- is the amount of the frequency (in mhz) to be boosted. If it is
+ is the amount of the frequency (in Mhz) to be boosted. If it is
zero boosting frequency will not be enabled. This value will be
used only by usb gadget driver.
+config TEGRA_EHCI_BOOST_CPU_FREQ
+ int "Boost cpu frequency(in Mhz) for tegra usb host"
+ range 0 1300 if ARCH_TEGRA_3x_SOC
+ range 0 1800 if ARCH_TEGRA_11x_SOC
+ range 0 2000 if ARCH_TEGRA_14x_SOC
+ default 0
+ help
+ This value is the amount of the cpu frequency (in Mhz)
+ to be boosted. If it is zero boosting frequency will not
+ be enabled. This value will be used only by usb ehci driver.
+
config TEGRA_DYNAMIC_PWRDET
bool "Enable dynamic activation of IO level auto-detection"
depends on TEGRA_SILICON_PLATFORM
send out wakeup source and uevents which indicate suspend_prepare and
post_suspend.
-config TEGRA_USB_MODEM_POWER
- bool "Enable tegra usb modem power management"
- default n
- help
- This option enables support for out-of_band remote wakeup, selective
- suspend and system suspend/resume.
-
config TEGRA_BB_XMM_POWER
bool "Enable power driver for XMM modem"
default n
Harmless to select this even if hardware does not support full
4GB physical memory.
-config TEGRA_LP1_950
+config TEGRA_LP1_LOW_COREVOLTAGE
bool "LP1 low core voltage"
default n
- depends on ARCH_TEGRA_3x_SOC
+ depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_11x_SOC
help
Enable support for LP1 Core voltage to set to lowest
-config TEGRA_LATENCY_ALLOWANCE
- bool "Allow memory clients to configure latency allowance"
- help
- Latency allowance is a per-memory-client setting that tells the
- memory controller how long it can ignore a request in favor of
- others. In other words, It indicates how long a request from specific
- memory client can wait before it is served.
- Enabling this option allows memory clients configure the
- latency allowance as per their bandwidth requirement.
-
-config TEGRA_LATENCY_ALLOWANCE_SCALING
- bool "Enable latency allowance scaling"
- depends on TEGRA_LATENCY_ALLOWANCE
+config TEGRA_DISABLE_BBC_LATENCY_ALLOWANCE
+ bool "Disable BBCRW latency allowance"
help
- Enables latency allowance scaling, which enables scaling
- programmed latency allowance values based on fifo threshold levels
- set for for display and vi hardware.
+ Disables BBCRW latency allowance configuration by
+ clients. The BBCRW latency allowance would remain
+ same as boot time configured value.
config TEGRA_BASEBAND
bool "Enable integrated tegra baseband support"
config TEGRA_MC_PTSA
bool "Enable MC PTSA programming"
- depends on TEGRA_LATENCY_ALLOWANCE
help
Enables Priority Tier Snap Arbiter programming in
Memory Controller. PTSA is a Memory Controller feature that
be useful in debug or in understanding performance on a
running system.
-config TEGRA_ISOMGR_DEBUG
- bool "Inject stimulus into Isochronous Bandwidth Manager "
- depends on TEGRA_ISOMGR && TEGRA_ISOMGR_SYSFS
+config TEGRA_ISOMGR_MAX_ISO_BW_QUIRK
+ bool "Relax Max ISO Bw limit"
+ depends on TEGRA_ISOMGR
+ default y
help
- When enabled, sysfs can be used to inject stimulus into isomgr.
- This is used to generate stimulus to isomgr for debug. It's
- especially useful for contriving isomgr tests. You can write
- user space tests that exercise isomgr in ways that drivers
- couldn't easily accommodate.
+ When enabled, allows system with less ISO bw continue to
+ work. This is necessary for systems running at lower
+ EMC clock freq or on FPGA.
config TEGRA_IO_DPD
bool "Allow IO DPD"
config TEGRA_SOCTHERM
bool "Enable soctherm"
- depends on ARCH_TEGRA_11x_SOC
+ depends on ARCH_TEGRA_11x_SOC || ARCH_TEGRA_14x_SOC
default y
help
Enables use of soctherm for thermal management.
+config TEGRA_USE_SECURE_KERNEL
+ bool "Boot the linux kernel in non-secure mode"
+ help
+ When enabled, the CPU will boot in the non-secure mode and issue
+ SMCs in order to access secure registers. SMC requests would be
+ serviced by a third party software component running in the secure
+ mode.
+
config TEGRA_VIRTUAL_CPUID
bool "virtualized CPUID"
- depends on !TRUSTED_FOUNDATIONS
+ depends on !TEGRA_USE_SECURE_KERNEL
depends on ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
default n
help
granularity of possible memory rate steps. In this case PLLC
provides a backup memory clock while PLLM is re-locking to the
new rate.
+config ARCH_TEGRA_VIC
+ bool "Tegra Video Image Compositor present"
+ default y
+ help
+ Say Y here if the SOC supports the Tegra Video Image Compositor.
+ Note that this not the same as the ARM Vectored Interrupt Controller.
+
+config TEGRA_MC_DOMAINS
+ bool "Enable MC domains"
+ depends on PM_GENERIC_DOMAINS
+ default n
+ help
+ When enabled, clock gates MC when it's not needed.
+
+config TEGRA_USE_NCT
+ bool "Enable NCT partition access"
+ help
+ When enabled, we can read non-volatile items from NCT partition.
+
+config TEGRA_VDD_CORE_OVERRIDE
+ bool "Enable core rail override support"
+ depends on TEGRA_SILICON_PLATFORM
+ default n
+ help
+ When enabled, core rail can be fixed and locked at specified voltage
+ within override range, and core modules clocks are capped at rates
+ safe at override level.
+
+config TEGRA_GMI
+ bool
endif