ARM: tegra12: power: Re-direct GPU rail gating control
[linux-3.10.git] / arch / arm / mach-s5p64x0 / common.c
index 28d0b91..8ae5800 100644 (file)
@@ -27,6 +27,7 @@
 
 #include <asm/irq.h>
 #include <asm/proc-fns.h>
+#include <asm/system_misc.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
+#include <plat/sdhci.h>
 #include <plat/adc-core.h>
 #include <plat/fb-core.h>
+#include <plat/spi-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-irqtype.h>
 #include <plat/regs-serial.h>
@@ -145,15 +148,12 @@ static void s5p64x0_idle(void)
 {
        unsigned long val;
 
-       if (!need_resched()) {
-               val = __raw_readl(S5P64X0_PWR_CFG);
-               val &= ~(0x3 << 5);
-               val |= (0x1 << 5);
-               __raw_writel(val, S5P64X0_PWR_CFG);
+       val = __raw_readl(S5P64X0_PWR_CFG);
+       val &= ~(0x3 << 5);
+       val |= (0x1 << 5);
+       __raw_writel(val, S5P64X0_PWR_CFG);
 
-               cpu_do_idle();
-       }
-       local_irq_enable();
+       cpu_do_idle();
 }
 
 /*
@@ -180,9 +180,13 @@ void __init s5p6440_map_io(void)
        /* initialize any device information early */
        s3c_adc_setname("s3c64xx-adc");
        s3c_fb_setname("s5p64x0-fb");
+       s3c64xx_spi_setname("s5p64x0-spi");
+
+       s5p64x0_default_sdhci0();
+       s5p64x0_default_sdhci1();
+       s5p6440_default_sdhci2();
 
        iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
-       init_consistent_dma_size(SZ_8M);
 }
 
 void __init s5p6450_map_io(void)
@@ -190,9 +194,13 @@ void __init s5p6450_map_io(void)
        /* initialize any device information early */
        s3c_adc_setname("s3c64xx-adc");
        s3c_fb_setname("s5p64x0-fb");
+       s3c64xx_spi_setname("s5p64x0-spi");
+
+       s5p64x0_default_sdhci0();
+       s5p64x0_default_sdhci1();
+       s5p6450_default_sdhci2();
 
        iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
-       init_consistent_dma_size(SZ_8M);
 }
 
 /*
@@ -277,41 +285,12 @@ int __init s5p64x0_init(void)
        printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
 
        /* set idle function */
-       pm_idle = s5p64x0_idle;
+       arm_pm_idle = s5p64x0_idle;
 
        return device_register(&s5p64x0_dev);
 }
 
-static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
-       [0] = {
-               .name           = "pclk_low",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       },
-       [1] = {
-               .name           = "uclk1",
-               .divisor        = 1,
-               .min_baud       = 0,
-               .max_baud       = 0,
-       },
-};
-
 /* uart registration process */
-
-void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-       struct s3c2410_uartcfg *tcfg = cfg;
-       u32 ucnt;
-
-       for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-               if (!tcfg->clocks) {
-                       tcfg->clocks = s5p64x0_serial_clocks;
-                       tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
-               }
-       }
-}
-
 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
        int uart;
@@ -321,13 +300,11 @@ void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
                s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
        }
 
-       s5p64x0_common_init_uarts(cfg, no);
        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
 
 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
-       s5p64x0_common_init_uarts(cfg, no);
        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }