select GENERIC_IRQ_SHOW
select GENERIC_PCI_IOMAP
select GENERIC_SMP_IDLE_THREAD
+ select GENERIC_IDLE_POLL_SETUP
select GENERIC_STRNCPY_FROM_USER
select GENERIC_STRNLEN_USER
select HARDIRQS_SW_RESEND
- select HAVE_AOUT
select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
select HAVE_ARCH_KGDB
select HAVE_ARCH_SECCOMP_FILTER
select HAVE_GENERIC_HARDIRQS
select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
select HAVE_IDE if PCI || ISA || PCMCIA
+ select HAVE_IRQ_TIME_ACCOUNTING
select HAVE_KERNEL_GZIP
select HAVE_KERNEL_LZMA
select HAVE_KERNEL_LZO
select CLONE_BACKWARDS
select OLD_SIGSUSPEND3
select OLD_SIGACTION
+ select HAVE_CONTEXT_TRACKING
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
config SYS_SUPPORTS_APM_EMULATION
bool
-config GENERIC_GPIO
- bool
-
config HAVE_TCM
bool
select GENERIC_ALLOCATOR
default DRAM_BASE if REMAP_VECTORS_TO_RAM
default 0x00000000
help
- The base address of exception vectors.
+ The base address of exception vectors. This must be two pages
+ in size.
config ARM_PATCH_PHYS_VIRT
bool "Patch physical to virtual translations at runtime" if EMBEDDED
This enables support for systems based on Atmel
AT91RM9200 and AT91SAM9* processors.
-config ARCH_BCM2835
- bool "Broadcom BCM2835 family"
- select ARCH_REQUIRE_GPIOLIB
- select ARM_AMBA
- select ARM_ERRATA_411920
- select ARM_TIMER_SP804
- select CLKDEV_LOOKUP
- select CLKSRC_OF
- select COMMON_CLK
- select CPU_V6
- select GENERIC_CLOCKEVENTS
- select MULTI_IRQ_HANDLER
- select PINCTRL
- select PINCTRL_BCM2835
- select SPARSE_IRQ
- select USE_OF
- help
- This enables support for the Broadcom BCM2835 SoC. This SoC is
- use in the Raspberry Pi, and Roku 2 devices.
-
-config ARCH_CNS3XXX
- bool "Cavium Networks CNS3XXX family"
- select ARM_GIC
- select CPU_V6K
- select GENERIC_CLOCKEVENTS
- select MIGHT_HAVE_CACHE_L2X0
- select MIGHT_HAVE_PCI
- select PCI_DOMAINS if PCI
- help
- Support for Cavium Networks CNS3XXX platform.
-
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select ARCH_REQUIRE_GPIOLIB
bool "Cortina Systems Gemini"
select ARCH_REQUIRE_GPIOLIB
select ARCH_USES_GETTIMEOFFSET
+ select NEED_MACH_GPIO_H
select CPU_FA526
help
Support for the Cortina Systems Gemini family SoCs
-config ARCH_SIRF
- bool "CSR SiRF"
- select ARCH_REQUIRE_GPIOLIB
- select AUTO_ZRELADDR
- select COMMON_CLK
- select GENERIC_CLOCKEVENTS
- select GENERIC_IRQ_CHIP
- select MIGHT_HAVE_CACHE_L2X0
- select NO_IOPORT
- select PINCTRL
- select PINCTRL_SIRF
- select USE_OF
- help
- Support for CSR SiRFprimaII/Marco/Polo platforms
-
config ARCH_EBSA110
bool "EBSA-110"
select ARCH_USES_GETTIMEOFFSET
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
-config ARCH_MXS
- bool "Freescale MXS-based"
- select ARCH_REQUIRE_GPIOLIB
- select CLKDEV_LOOKUP
- select CLKSRC_MMIO
- select COMMON_CLK
- select GENERIC_CLOCKEVENTS
- select HAVE_CLK_PREPARE
- select MULTI_IRQ_HANDLER
- select PINCTRL
- select SPARSE_IRQ
- select USE_OF
- help
- Support for Freescale MXS-based family of processors
-
config ARCH_NETX
bool "Hilscher NetX based"
select ARM_VIC
help
This enables support for systems based on the Hilscher NetX Soc
-config ARCH_H720X
- bool "Hynix HMS720x-based"
- select ARCH_USES_GETTIMEOFFSET
- select CPU_ARM720T
- select ISA_DMA_API
- help
- This enables support for systems based on the Hynix HMS720x
-
config ARCH_IOP13XX
bool "IOP13xx-based"
depends on MMU
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_PCI
select NEED_MACH_IO_H
+ select USB_EHCI_BIG_ENDIAN_MMIO
+ select USB_EHCI_BIG_ENDIAN_DESC
help
Support for Intel's IXP4XX (XScale) family of processors.
config ARCH_DOVE
bool "Marvell Dove"
select ARCH_REQUIRE_GPIOLIB
- select CPU_V7
+ select CPU_PJ4
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_PCI
select PINCTRL
select PINCTRL_DOVE
select PLAT_ORION_LEGACY
select USB_ARCH_HAS_EHCI
+ select MVEBU_MBUS
help
Support for the Marvell Dove SoC 88AP510
select PINCTRL
select PINCTRL_KIRKWOOD
select PLAT_ORION_LEGACY
+ select MVEBU_MBUS
help
Support for the following Marvell Kirkwood series SoCs:
88F6180, 88F6192 and 88F6281.
select GENERIC_CLOCKEVENTS
select PCI
select PLAT_ORION_LEGACY
+ select MVEBU_MBUS
help
Support for the following Marvell MV78xx0 series SoCs:
MV781x0, MV782x0.
select GENERIC_CLOCKEVENTS
select PCI
select PLAT_ORION_LEGACY
+ select MVEBU_MBUS
help
Support for the following Marvell Orion 5x series SoCs:
Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
- select CLKSRC_OF
- select COMMON_CLK
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
- select SPARSE_IRQ
+ select NEED_MACH_MEMORY_H
select USE_OF
+ select FIQ
+ select PCI
+ select CPU_IDLE_MULTIPLE_DRIVERS
help
This enables support for NVIDIA Tegra based systems (Tegra APX,
Tegra 6xx and Tegra 2 series).
select MULTI_IRQ_HANDLER
select NEED_MACH_MEMORY_H
select NO_IOPORT
- select PINCTRL
+ select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
select PM_GENERIC_DOMAINS if PM
select SPARSE_IRQ
help
config ARCH_S3C24XX
bool "Samsung S3C24XX SoCs"
select ARCH_HAS_CPUFREQ
- select ARCH_USES_GETTIMEOFFSET
+ select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
+ select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
+ select MULTI_IRQ_HANDLER
select NEED_MACH_GPIO_H
select NEED_MACH_IO_H
help
bool "Samsung S3C64XX"
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
- select ARCH_USES_GETTIMEOFFSET
select ARM_VIC
select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
select CPU_V6
+ select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
config ARCH_S5PC100
bool "Samsung S5PC100"
- select ARCH_USES_GETTIMEOFFSET
+ select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
select CPU_V7
+ select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SPARSEMEM_ENABLE
select CLKDEV_LOOKUP
+ select COMMON_CLK
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_CLK
help
Support for ST-Ericsson U300 series mobile platforms.
-config ARCH_U8500
- bool "ST-Ericsson U8500 Series"
- depends on MMU
- select ARCH_HAS_CPUFREQ
- select ARCH_REQUIRE_GPIOLIB
- select ARM_AMBA
- select CLKDEV_LOOKUP
- select CPU_V7
- select GENERIC_CLOCKEVENTS
- select HAVE_SMP
- select MIGHT_HAVE_CACHE_L2X0
- select SPARSE_IRQ
- help
- Support for ST-Ericsson's Ux500 architecture
-
-config ARCH_NOMADIK
- bool "STMicroelectronics Nomadik"
- select ARCH_REQUIRE_GPIOLIB
- select ARM_AMBA
- select ARM_VIC
- select CLKSRC_NOMADIK_MTU
- select COMMON_CLK
- select CPU_ARM926T
- select GENERIC_CLOCKEVENTS
- select MIGHT_HAVE_CACHE_L2X0
- select USE_OF
- select PINCTRL
- select PINCTRL_STN8815
- select SPARSE_IRQ
- help
- Support for the Nomadik platform by ST-Ericsson
-
-config PLAT_SPEAR
- bool "ST SPEAr"
- select ARCH_HAS_CPUFREQ
- select ARCH_REQUIRE_GPIOLIB
- select ARM_AMBA
- select CLKDEV_LOOKUP
- select CLKSRC_MMIO
- select COMMON_CLK
- select GENERIC_CLOCKEVENTS
- select HAVE_CLK
- help
- Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
-
config ARCH_DAVINCI
bool "TI DaVinci"
select ARCH_HAS_HOLES_MEMORYMODEL
bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
default y
select ARCH_MULTI_V6_V7
- select ARCH_VEXPRESS
select CPU_V7
config ARCH_MULTI_V6_V7
source "arch/arm/mach-bcm/Kconfig"
+source "arch/arm/mach-bcm2835/Kconfig"
+
source "arch/arm/mach-clps711x/Kconfig"
source "arch/arm/mach-cns3xxx/Kconfig"
source "arch/arm/mach-gemini/Kconfig"
-source "arch/arm/mach-h720x/Kconfig"
-
source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
-source "arch/arm/plat-spear/Kconfig"
+source "arch/arm/mach-spear/Kconfig"
source "arch/arm/mach-s3c24xx/Kconfig"
config ARM_TIMER_SP804
bool
select CLKSRC_MMIO
- select HAVE_SCHED_CLOCK
+ select CLKSRC_OF if OF
source arch/arm/mm/Kconfig
config ARM_NR_BANKS
int
default 16 if ARCH_EP93XX
+ default 16 if ARCH_TEGRA_4GB_MEMORY
default 8
config IWMMXT
- bool "Enable iWMMXt support"
+ bool "Enable iWMMXt support" if !CPU_PJ4
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
- default y if PXA27x || PXA3xx || ARCH_MMP
+ default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
help
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
source "arch/arm/Kconfig-nommu"
endif
+config PJ4B_ERRATA_4742
+ bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
+ depends on CPU_PJ4B && MACH_ARMADA_370
+ default y
+ help
+ When coming out of either a Wait for Interrupt (WFI) or a Wait for
+ Event (WFE) IDLE states, a specific timing sensitivity exists between
+ the retiring WFI/WFE instructions and the newly issued subsequent
+ instructions. This sensitivity can result in a CPU hang scenario.
+ Workaround:
+ The software must insert either a Data Synchronization Barrier (DSB)
+ or Data Memory Barrier (DMB) command immediately after the WFI/WFE
+ instruction
+
config ARM_ERRATA_326103
bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
depends on CPU_V6
ACTLR register. Note that setting specific bits in the ACTLR register
may not be available in non-secure mode.
+config ARM_ERRATA_716044
+ bool "ARM errata: an uncacheable load multiple instruction can cause a deadlock"
+ depends on CPU_V7
+ help
+ Under some rare circumstances, an uncacheable load multiple
+ instruction (LDRD, LDM, VLDM, VLD1, VLD2, VLD3, VLD4) can cause
+ a processor deadlock.
+
config ARM_ERRATA_742230
bool "ARM errata: DMB operation may be faulty"
depends on CPU_V7 && SMP
is not correctly implemented in PL310 as clean lines are not
invalidated as a result of these operations.
+config ARM_ERRATA_643719
+ bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
+ depends on CPU_V7 && SMP
+ help
+ This option enables the workaround for the 643719 Cortex-A9 (prior to
+ r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
+ register returns zero when it should return one. The workaround
+ corrects this value, ensuring cache maintenance operations which use
+ it behave as intended and avoiding data corruption.
+
config ARM_ERRATA_720789
bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
depends on CPU_V7
relevant cache maintenance functions and sets a specific bit
in the diagnostic control register of the SCU.
+config ARM_ERRATA_720791
+ bool "ARM errata: Dynamic high-level clock gating corrupts the Jazelle instruction stream"
+ depends on CPU_V7
+ help
+ This option enables the workaround for the 720791 Cortex-A9
+ (r1p0..r1p2) erratum. The Jazelle instruction stream may be
+ corrupted when dynamic high-level clock gating is enabled.
+ This workaround disables gating the Core clock when the Instruction
+ side is waiting for a Page Table Walk answer or linefill completion.
+
+config ARM_ERRATA_752520
+ bool "ARM errata: Faulty arbitration between PLD and Cacheable TLB requests may create a system deadlock"
+ depends on CPU_V7
+ help
+ Under rare circumstances, PLDs may interfere with a Cacheable page table walk,
+ creating a processor deadlock. The erratum can only happen when the Data Cache
+ and MMU are enabled, with the TLB descriptors marked as L1 cacheable,
+ so that Page Table Walks are performed as cache linefills.
+
+config ARM_ERRATA_761320
+ bool "Full cache line writes to the same memory region from at least two processors might deadlock processor"
+ depends on CPU_V7 && SMP
+ help
+ Under very rare circumstances, full cache line writes
+ from (at least) 2 processors on cache lines in hazard with
+ other requests may cause arbitration issues in the SCU,
+ leading to processor deadlock. This erratum can be
+ worked around by setting bit[21] of the undocumented
+ Diagnostic Control Register to 1.
+
config PL310_ERRATA_769419
bool "PL310 errata: no automatic Store Buffer drain"
depends on CACHE_L2X0
to deadlock. This workaround puts DSB before executing ISB if
an abort may occur on cache maintenance.
+config ARM_ERRATA_798181
+ bool "ARM errata: TLBI/DSB failure on Cortex-A15"
+ depends on CPU_V7 && SMP
+ help
+ On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
+ adequately shooting down all use of the old entries. This
+ option enables the Linux kernel workaround for this erratum
+ which sends an IPI to the CPUs that are running the same ASID
+ as the one being invalidated.
+
+config ARM_ERRATA_799270
+ bool "ARM errata: Writing ACTLR.SMP when the L2 cache has been idle for an extended period may not work correctly"
+ depends on CPU_V7 && SMP
+ help
+ This option enables the workaround for the 799270 Cortex-A15 (r2p0,
+ r2p1, r2p2, r2p3, r2p4) erratum. If the L2 cache logic clock is
+ stopped because of L2 inactivity, setting or clearing the ACTLR.SMP
+ bit might not be effective. The bit is modified in the ACTLR, meaning
+ a read of the register returns the updated value. However the logic
+ that uses that bit retains the previous value. The workaround is to
+ do a memory read to a memory location with Non-cacheable, Strongly-
+ ordered, or Device memory attributes. A dependency must be created
+ between the returning load data and the MCR instruction that sets the
+ ACTLR.SMP bit.
+
+config ARM_ERRATA_798870
+ bool "ARM errata: A memory read can stall indefinitely in the L2 cache"
+ depends on CPU_V7
+ help
+ If back-to-back speculative cache line fills (fill A and fill B)
+ are issued from the L1 data cache of a CPU to the L2 cache, the
+ second request (fill B) is then cancelled, and the second request
+ would have detected a hazard against a recent write or eviction
+ (write B) to the same cache line as fill B, then the L2 logic might
+ deadlock. The workaround is to let a secondary CPU go through reset
+ cycle periodically which can restart L2 clock.
+
endmenu
source "arch/arm/common/Kconfig"
source "drivers/pci/Kconfig"
+source "drivers/pci/pcie/Kconfig"
+
source "drivers/pcmcia/Kconfig"
endmenu
depends on GENERIC_CLOCKEVENTS
depends on HAVE_SMP
depends on MMU
- select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
+ select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP && \
+ (!ARCH_TEGRA || ARCH_TEGRA_HAS_ARM_SCU)
select USE_GENERIC_SMP_HELPERS
help
This enables support for systems with more than one CPU. If you have
help
This options enables support for the ARM timer and watchdog unit
+config MCPM
+ bool "Multi-Cluster Power Management"
+ depends on CPU_V7 && SMP
+ help
+ This option provides the common power management infrastructure
+ for (multi-)cluster based systems, such as big.LITTLE based
+ systems.
+
choice
prompt "Memory split"
default VMSPLIT_3G
default 0x80000000 if VMSPLIT_2G
default 0xC0000000
+choice
+ prompt "Task size"
+ depends on MMU
+ default TASK_SIZE_1G_LESS_16M if VMSPLIT_1G
+ default TASK_SIZE_2G_LESS_16M if VMSPLIT_2G
+ default TASK_SIZE_3G_LESS_16M
+
+config TASK_SIZE_1G_LESS_16M
+ bool "Task size is 1GiB less 16MiB"
+ depends on VMSPLIT_1G
+
+config TASK_SIZE_1G_LESS_24M
+ bool "Task size is 1GiB less 24MiB"
+ depends on VMSPLIT_1G
+
+config TASK_SIZE_2G_LESS_16M
+ bool "Task size is 2GiB less 16MiB"
+ depends on VMSPLIT_2G
+
+config TASK_SIZE_2G_LESS_24M
+ bool "Task size is 2GiB less 24MiB"
+ depends on VMSPLIT_2G
+
+config TASK_SIZE_3G_LESS_16M
+ bool "Task size is 3GiB less 16MiB"
+ depends on VMSPLIT_3G
+
+config TASK_SIZE_3G_LESS_24M
+ bool "Task size is 3GiB less 24MiB"
+ depends on VMSPLIT_3G
+
+endchoice
+
+config TASK_SIZE
+ hex
+ depends on MMU
+ default 0x3E800000 if TASK_SIZE_1G_LESS_24M
+ default 0x3F000000 if TASK_SIZE_1G_LESS_16M
+ default 0x7E800000 if TASK_SIZE_2G_LESS_24M
+ default 0x7F000000 if TASK_SIZE_2G_LESS_16M
+ default 0xBE800000 if TASK_SIZE_3G_LESS_24M
+ default 0xBF000000
+
config NR_CPUS
int "Maximum number of CPUs (2-32)"
range 2 32
bool "Use local timer interrupts"
depends on SMP
default y
- select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
+ select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT && !ARM_ARCH_TIMER \
+ && !TEGRA_SOC_TIMERS)
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system
int
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 512 if SOC_OMAP5
- default 355 if ARCH_U8500
- default 288 if ARCH_VT8500 || ARCH_SUNXI
+ default 392 if ARCH_U8500
+ default 352 if ARCH_VT8500
+ default 288 if ARCH_SUNXI
default 264 if MACH_H4700
default 0
help
ARCH_S5PV210 || ARCH_EXYNOS4
default AT91_TIMER_HZ if ARCH_AT91
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
+ default TEGRA_TIMER_HZ if ARCH_TEGRA
default 100
config SCHED_HRTICK
def_bool HIGH_RES_TIMERS
config THUMB2_KERNEL
- bool "Compile the kernel in Thumb-2 mode"
+ bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
depends on CPU_V7 && !CPU_V6 && !CPU_V6K
+ default y if CPU_THUMBONLY
select AEABI
select ARM_ASM_UNIFIED
select ARM_UNWIND
However, if the CPU data cache is using a write-allocate mode,
this option is unlikely to provide any performance gain.
+config ARM_PLD_64BYTE
+ bool "Use 64-bit preload size for kernel memory copy"
+ depends on CPU_V7
+ help
+ Config preload size for memcpy, selecting this for Cortex-A15
+
+config USE_LDRDSTRD_OVER_LDMSTM
+ bool "Use 64-bit access instructions to optimize memory copy"
+ depends on CPU_V7
+ help
+ Cortex-A15 perform better when use LDRD/STRD to access memory.
+ Selecting this to optimize memory copy routines.
+
config SECCOMP
bool
prompt "Enable seccomp to safely compute untrusted bytecode"
depends on ARM && AEABI && OF
depends on CPU_V7 && !CPU_V6
depends on !GENERIC_ATOMIC64
+ select ARM_PSCI
help
Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
+config ARM_FLUSH_CONSOLE_ON_RESTART
+ bool "Force flush the console on restart"
+ help
+ If the console is locked while the system is rebooted, the messages
+ in the temporary logbuffer would not have propogated to all the
+ console drivers. This option forces the console lock to be
+ released if it failed to be acquired, which will cause all the
+ pending messages to be flushed.
+
endmenu
menu "Boot options"
This was deprecated in 2001 and announced to live on for 5 years.
Some old boot loaders still use this way.
+config BUILD_ARM_APPENDED_DTB_IMAGE
+ bool "Build a concatenated zImage/dtb by default"
+ depends on OF
+ help
+ Enabling this option will cause a concatenated zImage and DTB to
+ be built by default (instead of a standalone zImage.) The image
+ will built in arch/arm/boot/zImage-dtb.<dtb name>
+
+config BUILD_ARM_APPENDED_DTB_IMAGE_NAME
+ string "Default dtb name"
+ depends on BUILD_ARM_APPENDED_DTB_IMAGE
+ help
+ name of the dtb to append when building a concatenated
+ zImage/dtb.
+
# Compressed boot loader in ROM. Yes, we really want to ask about
# TEXT and BSS so we preserve their values in the config files.
config ZBOOT_ROM_TEXT
config KEXEC
bool "Kexec system call (EXPERIMENTAL)"
- depends on (!SMP || HOTPLUG_CPU)
+ depends on (!SMP || PM_SLEEP_SMP)
help
kexec is a system call that implements the ability to shutdown your
current kernel, and to start another kernel. It is like a reboot
if ARCH_HAS_CPUFREQ
source "drivers/cpufreq/Kconfig"
-config CPU_FREQ_IMX
- tristate "CPUfreq driver for i.MX CPUs"
- depends on ARCH_MXC && CPU_FREQ
- select CPU_FREQ_TABLE
- help
- This enables the CPUfreq driver for i.MX CPUs.
-
config CPU_FREQ_S3C
bool
help
source "drivers/cpuidle/Kconfig"
+source "drivers/cpuquiet/Kconfig"
+
+source "drivers/edp/Kconfig"
+
endmenu
menu "Floating point emulation"