select HAVE_CLK
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
+ select NEED_MACH_MEMORY_H
select USE_OF
select FIQ
select PCI
and MMU are enabled, with the TLB descriptors marked as L1 cacheable,
so that Page Table Walks are performed as cache linefills.
+config ARM_ERRATA_761320
+ bool "Full cache line writes to the same memory region from at least two processors might deadlock processor"
+ depends on CPU_V7 && SMP
+ help
+ Under very rare circumstances, full cache line writes
+ from (at least) 2 processors on cache lines in hazard with
+ other requests may cause arbitration issues in the SCU,
+ leading to processor deadlock. This erratum can be
+ worked around by setting bit[21] of the undocumented
+ Diagnostic Control Register to 1.
+
config PL310_ERRATA_769419
bool "PL310 errata: no automatic Store Buffer drain"
depends on CACHE_L2X0
ARCH_S5PV210 || ARCH_EXYNOS4
default AT91_TIMER_HZ if ARCH_AT91
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
+ default TEGRA_TIMER_HZ if ARCH_TEGRA
default 100
config SCHED_HRTICK
source "drivers/cpuquiet/Kconfig"
+source "drivers/edp/Kconfig"
+
endmenu
menu "Floating point emulation"