asoc: tegra: Add support for K3.10 audio
[linux-3.10.git] / sound / soc / tegra / tegra30_i2s.h
1 /*
2  * tegra30_i2s.h - Definitions for Tegra30 I2S driver
3  *
4  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #ifndef __TEGRA30_I2S_H__
20 #define __TEGRA30_I2S_H__
21
22 #include "tegra_pcm.h"
23
24 /* Register offsets from TEGRA30_I2S*_BASE */
25
26 #define TEGRA30_I2S_CTRL                                0x0
27 #define TEGRA30_I2S_TIMING                              0x4
28 #define TEGRA30_I2S_OFFSET                              0x08
29 #define TEGRA30_I2S_CH_CTRL                             0x0c
30 #define TEGRA30_I2S_SLOT_CTRL                           0x10
31 #define TEGRA30_I2S_CIF_RX_CTRL                         0x14
32 #define TEGRA30_I2S_CIF_TX_CTRL                         0x18
33 #define TEGRA30_I2S_FLOWCTL                             0x1c
34 #define TEGRA30_I2S_TX_STEP                             0x20
35 #define TEGRA30_I2S_FLOW_STATUS                         0x24
36 #define TEGRA30_I2S_FLOW_TOTAL                          0x28
37 #define TEGRA30_I2S_FLOW_OVER                           0x2c
38 #define TEGRA30_I2S_FLOW_UNDER                          0x30
39 #define TEGRA30_I2S_LCOEF_1_4_0                         0x34
40 #define TEGRA30_I2S_LCOEF_1_4_1                         0x38
41 #define TEGRA30_I2S_LCOEF_1_4_2                         0x3c
42 #define TEGRA30_I2S_LCOEF_1_4_3                         0x40
43 #define TEGRA30_I2S_LCOEF_1_4_4                         0x44
44 #define TEGRA30_I2S_LCOEF_1_4_5                         0x48
45 #define TEGRA30_I2S_LCOEF_2_4_0                         0x4c
46 #define TEGRA30_I2S_LCOEF_2_4_1                         0x50
47 #define TEGRA30_I2S_LCOEF_2_4_2                         0x54
48 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
49 #define TEGRA30_I2S_SLOT_CTRL2                          0x64
50 #endif
51
52 /* Fields in TEGRA30_I2S_CTRL */
53
54 #define TEGRA30_I2S_CTRL_XFER_EN_TX                     (1 << 31)
55 #define TEGRA30_I2S_CTRL_XFER_EN_RX                     (1 << 30)
56 #define TEGRA30_I2S_CTRL_CG_EN                          (1 << 29)
57 #define TEGRA30_I2S_CTRL_SOFT_RESET                     (1 << 28)
58 #define TEGRA30_I2S_CTRL_TX_FLOWCTL_EN                  (1 << 27)
59
60 #define TEGRA30_I2S_CTRL_OBS_SEL_SHIFT                  24
61 #define TEGRA30_I2S_CTRL_OBS_SEL_MASK                   (7 << TEGRA30_I2S_CTRL_OBS_SEL_SHIFT)
62
63 #define TEGRA30_I2S_FRAME_FORMAT_LRCK                   0
64 #define TEGRA30_I2S_FRAME_FORMAT_FSYNC                  1
65
66 #define TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT             12
67 #define TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK              (7                              << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT)
68 #define TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK              (TEGRA30_I2S_FRAME_FORMAT_LRCK  << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT)
69 #define TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC             (TEGRA30_I2S_FRAME_FORMAT_FSYNC << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT)
70
71 #define TEGRA30_I2S_CTRL_MASTER_ENABLE                  (1 << 10)
72
73 #define TEGRA30_I2S_LRCK_LEFT_LOW                       0
74 #define TEGRA30_I2S_LRCK_RIGHT_LOW                      1
75
76 #define TEGRA30_I2S_CTRL_LRCK_SHIFT                     9
77 #define TEGRA30_I2S_CTRL_LRCK_MASK                      (1                          << TEGRA30_I2S_CTRL_LRCK_SHIFT)
78 #define TEGRA30_I2S_CTRL_LRCK_L_LOW                     (TEGRA30_I2S_LRCK_LEFT_LOW  << TEGRA30_I2S_CTRL_LRCK_SHIFT)
79 #define TEGRA30_I2S_CTRL_LRCK_R_LOW                     (TEGRA30_I2S_LRCK_RIGHT_LOW << TEGRA30_I2S_CTRL_LRCK_SHIFT)
80
81 #define TEGRA30_I2S_CTRL_LPBK_ENABLE                    (1 << 8)
82
83 #define TEGRA30_I2S_BIT_CODE_LINEAR                     0
84 #define TEGRA30_I2S_BIT_CODE_ULAW                       1
85 #define TEGRA30_I2S_BIT_CODE_ALAW                       2
86
87 #define TEGRA30_I2S_CTRL_BIT_CODE_SHIFT                 4
88 #define TEGRA30_I2S_CTRL_BIT_CODE_MASK                  (3                           << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
89 #define TEGRA30_I2S_CTRL_BIT_CODE_LINEAR                (TEGRA30_I2S_BIT_CODE_LINEAR << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
90 #define TEGRA30_I2S_CTRL_BIT_CODE_ULAW                  (TEGRA30_I2S_BIT_CODE_ULAW   << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
91 #define TEGRA30_I2S_CTRL_BIT_CODE_ALAW                  (TEGRA30_I2S_BIT_CODE_ALAW   << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
92
93 #define TEGRA30_I2S_BITS_8                              1
94 #define TEGRA30_I2S_BITS_12                             2
95 #define TEGRA30_I2S_BITS_16                             3
96 #define TEGRA30_I2S_BITS_20                             4
97 #define TEGRA30_I2S_BITS_24                             5
98 #define TEGRA30_I2S_BITS_28                             6
99 #define TEGRA30_I2S_BITS_32                             7
100
101 /* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */
102 #define TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT                 0
103 #define TEGRA30_I2S_CTRL_BIT_SIZE_MASK                  (7                   << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
104 #define TEGRA30_I2S_CTRL_BIT_SIZE_8                     (TEGRA30_I2S_BITS_8  << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
105 #define TEGRA30_I2S_CTRL_BIT_SIZE_12                    (TEGRA30_I2S_BITS_12 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
106 #define TEGRA30_I2S_CTRL_BIT_SIZE_16                    (TEGRA30_I2S_BITS_16 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
107 #define TEGRA30_I2S_CTRL_BIT_SIZE_20                    (TEGRA30_I2S_BITS_20 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
108 #define TEGRA30_I2S_CTRL_BIT_SIZE_24                    (TEGRA30_I2S_BITS_24 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
109 #define TEGRA30_I2S_CTRL_BIT_SIZE_28                    (TEGRA30_I2S_BITS_28 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
110 #define TEGRA30_I2S_CTRL_BIT_SIZE_32                    (TEGRA30_I2S_BITS_32 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
111
112 /* Fields in TEGRA30_I2S_TIMING */
113
114 #define TEGRA30_I2S_TIMING_NON_SYM_ENABLE               (1 << 12)
115 #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT      0
116 #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US    0x7fff
117 #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK       (TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)
118
119 /* Fields in TEGRA30_I2S_OFFSET */
120
121 #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT         16
122 #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US       0x7ff
123 #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK          (TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT)
124 #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT         0
125 #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US       0x7ff
126 #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK          (TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT)
127
128 /* Fields in TEGRA30_I2S_CH_CTRL */
129
130 /* (FSYNC width - 1) in bit clocks */
131 #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT           24
132 #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US         0xff
133 #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK            (TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US << TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT)
134
135 #define TEGRA30_I2S_HIGHZ_NO                            0
136 #define TEGRA30_I2S_HIGHZ_YES                           1
137 #define TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK               2
138
139 #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT            12
140 #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_MASK             (3                                 << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
141 #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_NO               (TEGRA30_I2S_HIGHZ_NO              << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
142 #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_YES              (TEGRA30_I2S_HIGHZ_YES             << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
143 #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK  (TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
144
145 #define TEGRA30_I2S_MSB_FIRST                           0
146 #define TEGRA30_I2S_LSB_FIRST                           1
147
148 #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT          10
149 #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MASK           (1                     << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT)
150 #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST      (TEGRA30_I2S_MSB_FIRST << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT)
151 #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST      (TEGRA30_I2S_LSB_FIRST << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT)
152 #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT          9
153 #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MASK           (1                     << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT)
154 #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST      (TEGRA30_I2S_MSB_FIRST << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT)
155 #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST      (TEGRA30_I2S_LSB_FIRST << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT)
156
157 #define TEGRA30_I2S_POS_EDGE                            0
158 #define TEGRA30_I2S_NEG_EDGE                            1
159
160 #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT             8
161 #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK              (1                    << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT)
162 #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE          (TEGRA30_I2S_POS_EDGE << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT)
163 #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE          (TEGRA30_I2S_NEG_EDGE << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT)
164
165 /* Sample size is # bits from BIT_SIZE minus this field */
166 #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT          4
167 #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US        7
168 #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK           (TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US << TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT)
169
170 #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT          0
171 #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US        7
172 #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK           (TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US << TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT)
173
174 /* Fields in TEGRA30_I2S_SLOT_CTRL */
175
176 /* Number of slots in frame, minus 1 */
177 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
178 #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT         0
179 #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US       0xf
180 #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK          (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT)
181 #else
182 #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT         16
183 #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US       7
184 #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK          (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT)
185 #endif
186
187 /* TDM mode slot enable bitmask */
188 #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT     8
189 #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK      (0xff << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT)
190
191 #define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT     0
192 #define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK      (0xff << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT)
193
194 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
195 #define TEGRA30_I2S_SLOT_CTRL2_TX_SLOT_ENABLES_SHIFT    0
196 #define TEGRA30_I2S_SLOT_CTRL2_TX_SLOT_ENABLES_MASK     (0xffff << TEGRA30_I2S_SLOT_CTRL2_TX_SLOT_ENABLES_SHIFT)
197
198 #define TEGRA30_I2S_SLOT_CTRL2_RX_SLOT_ENABLES_SHIFT    16
199 #define TEGRA30_I2S_SLOT_CTRL2_RX_SLOT_ENABLES_MASK     (0xffff << TEGRA30_I2S_SLOT_CTRL2_RX_SLOT_ENABLES_SHIFT)
200 #endif
201
202 /* Fields in TEGRA30_I2S_CIF_RX_CTRL */
203 /* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */
204
205 /* Fields in TEGRA30_I2S_CIF_TX_CTRL */
206 /* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */
207
208 /* Fields in TEGRA30_I2S_FLOWCTL */
209
210 #define TEGRA30_I2S_FILTER_LINEAR                       0
211 #define TEGRA30_I2S_FILTER_QUAD                         1
212
213 #define TEGRA30_I2S_FLOWCTL_FILTER_SHIFT                31
214 #define TEGRA30_I2S_FLOWCTL_FILTER_MASK                 (1                         << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT)
215 #define TEGRA30_I2S_FLOWCTL_FILTER_LINEAR               (TEGRA30_I2S_FILTER_LINEAR << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT)
216 #define TEGRA30_I2S_FLOWCTL_FILTER_QUAD                 (TEGRA30_I2S_FILTER_QUAD   << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT)
217
218 /* Fields in TEGRA30_I2S_TX_STEP */
219
220 #define TEGRA30_I2S_TX_STEP_SHIFT                       0
221 #define TEGRA30_I2S_TX_STEP_MASK_US                     0xffff
222 #define TEGRA30_I2S_TX_STEP_MASK                        (TEGRA30_I2S_TX_STEP_MASK_US << TEGRA30_I2S_TX_STEP_SHIFT)
223
224 /* Fields in TEGRA30_I2S_FLOW_STATUS */
225
226 #define TEGRA30_I2S_FLOW_STATUS_UNDERFLOW               (1 << 31)
227 #define TEGRA30_I2S_FLOW_STATUS_OVERFLOW                (1 << 30)
228 #define TEGRA30_I2S_FLOW_STATUS_MONITOR_INT_EN          (1 << 4)
229 #define TEGRA30_I2S_FLOW_STATUS_COUNTER_CLR             (1 << 3)
230 #define TEGRA30_I2S_FLOW_STATUS_MONITOR_CLR             (1 << 2)
231 #define TEGRA30_I2S_FLOW_STATUS_COUNTER_EN              (1 << 1)
232 #define TEGRA30_I2S_FLOW_STATUS_MONITOR_EN              (1 << 0)
233
234 /*
235  * There are no fields in TEGRA30_I2S_FLOW_TOTAL, TEGRA30_I2S_FLOW_OVER,
236  * TEGRA30_I2S_FLOW_UNDER; they are counters taking the whole register.
237  */
238
239 /* Fields in TEGRA30_I2S_LCOEF_* */
240
241 #define TEGRA30_I2S_LCOEF_COEF_SHIFT                    0
242 #define TEGRA30_I2S_LCOEF_COEF_MASK_US                  0xffff
243 #define TEGRA30_I2S_LCOEF_COEF_MASK                     (TEGRA30_I2S_LCOEF_COEF_MASK_US << TEGRA30_I2S_LCOEF_COEF_SHIFT)
244
245 /* Number of i2s controllers*/
246 #define TEGRA30_NR_I2S_IFC                              5
247
248 struct dsp_config_t {
249         int num_slots;
250         int rx_mask;
251         int tx_mask;
252         int slot_width;
253         int rx_data_offset;
254         int tx_data_offset;
255 };
256
257 struct codec_config {
258         int i2s_id;
259         int rate;
260         int channels;
261         int bitsize;
262         int is_i2smaster;
263         int i2s_mode;
264         int bit_clk;
265 };
266
267 struct tegra30_i2s {
268         struct snd_soc_dai_driver dai;
269         struct device *dev;
270         int cif_id;
271         struct clk *clk_i2s;
272         struct clk *clk_i2s_sync;
273         struct clk *clk_audio_2x;
274         struct clk *clk_pll_a_out0;
275         int id;
276         enum tegra30_ahub_txcif capture_i2s_cif;
277         enum tegra30_ahub_rxcif capture_fifo_cif;
278         struct tegra_pcm_dma_params capture_dma_data;
279         enum tegra30_ahub_rxcif playback_i2s_cif;
280         enum tegra30_ahub_txcif playback_fifo_cif;
281         struct tegra_pcm_dma_params playback_dma_data;
282         struct regmap *regmap;
283         int daifmt;
284         int dam_ifc;
285         int dam_ch_refcount;
286         int  playback_ref_count;
287         int  capture_ref_count;
288         bool is_dam_used;
289 #ifdef CONFIG_PM
290         #ifdef CONFIG_ARCH_TEGRA_3x_SOC
291                 u32  reg_cache[(TEGRA30_I2S_LCOEF_2_4_2 >> 2) + 1];
292         #else
293                 u32  reg_cache[(TEGRA30_I2S_SLOT_CTRL2 >> 2) + 1];
294         #endif
295 #endif
296         int call_record_dam_ifc;
297         int call_record_dam_ifc2;
298         int is_call_mode_rec;
299         struct dsp_config_t dsp_config;
300         int i2s_bit_clk;
301 };
302
303 int tegra30_make_voice_call_connections(struct codec_config *codec_info,
304                         struct codec_config *bb_info,
305                         int uses_voice_codec);
306
307 int tegra30_break_voice_call_connections(struct codec_config *codec_info,
308                         struct codec_config *bb_info,
309                         int uses_voice_codec);
310
311 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
312 int t14x_make_bt_voice_call_connections(struct codec_config *codec_info,
313                                 struct ahub_bbc1_config *bb_info,
314                                 int uses_voice_codec);
315
316 int t14x_break_bt_voice_call_connections(struct codec_config *codec_info,
317                                 struct ahub_bbc1_config *bb_info,
318                                 int uses_voice_codec);
319
320 int t14x_make_voice_call_connections(struct codec_config *codec_info,
321                                 struct ahub_bbc1_config *bb_info,
322                                 int uses_voice_codec);
323
324 int t14x_break_voice_call_connections(struct codec_config *codec_info,
325                                 struct ahub_bbc1_config *bb_info,
326                                 int uses_voice_codec);
327 #endif
328
329 #endif