ccd3dd45da48b7c36ae3c1f60b03025b7a02990f
[linux-3.10.git] / sound / soc / tegra / tegra30_i2s.c
1 /*
2  * tegra30_i2s.c - Tegra30 I2S driver
3  *
4  * Author: Stephen Warren <swarren@nvidia.com>
5  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Based on code copyright/by:
8  *
9  * Copyright (c) 2009-2013, NVIDIA Corporation.
10  * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
11  * Scott Peterson <speterson@nvidia.com>
12  *
13  * Copyright (C) 2010 Google, Inc.
14  * Iliyan Malchev <malchev@google.com>
15  *
16  * This program is free software; you can redistribute it and/or modify it
17  * under the terms and conditions of the GNU General Public License,
18  * version 2, as published by the Free Software Foundation.
19  *
20  * This program is distributed in the hope it will be useful, but WITHOUT
21  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
22  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
23  * more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
27  */
28
29 #include <linux/clk.h>
30 #include <linux/device.h>
31 #include <linux/io.h>
32 #include <linux/module.h>
33 #include <linux/of.h>
34 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/regmap.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
39 #include <mach/tegra_asoc_pdata.h>
40 #include <sound/core.h>
41 #include <sound/pcm.h>
42 #include <sound/pcm_params.h>
43 #include <sound/soc.h>
44
45 #include "tegra30_ahub.h"
46 #include "tegra30_dam.h"
47 #include "tegra30_i2s.h"
48
49 #define DRV_NAME "tegra30-i2s"
50
51 static struct tegra30_i2s  i2scont[TEGRA30_NR_I2S_IFC];
52
53 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
54 static struct tegra30_i2s bbc1cont;
55 #endif
56
57 static int tegra30_i2s_runtime_suspend(struct device *dev)
58 {
59         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
60
61         regcache_cache_only(i2s->regmap, true);
62
63         clk_disable_unprepare(i2s->clk_i2s);
64
65         return 0;
66 }
67
68 static int tegra30_i2s_runtime_resume(struct device *dev)
69 {
70         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
71         int ret;
72
73         ret = clk_prepare_enable(i2s->clk_i2s);
74         if (ret) {
75                 dev_err(dev, "clk_enable failed: %d\n", ret);
76                 return ret;
77         }
78
79         regcache_cache_only(i2s->regmap, false);
80
81         return 0;
82 }
83
84 int tegra30_i2s_startup(struct snd_pcm_substream *substream,
85                         struct snd_soc_dai *dai)
86 {
87         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
88         int ret;
89
90         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
91                 /* increment the playback ref count */
92                 i2s->playback_ref_count++;
93
94                 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
95                                         &i2s->playback_dma_data.addr,
96                                         &i2s->playback_dma_data.req_sel);
97                 i2s->playback_dma_data.wrap = 4;
98                 i2s->playback_dma_data.width = 32;
99
100                 if (!i2s->is_dam_used)
101                         tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
102                                                        i2s->playback_fifo_cif);
103         } else {
104                 i2s->capture_ref_count++;
105                 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
106                                         &i2s->capture_dma_data.addr,
107                                         &i2s->capture_dma_data.req_sel);
108                 i2s->capture_dma_data.wrap = 4;
109                 i2s->capture_dma_data.width = 32;
110                 tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
111                                                i2s->capture_i2s_cif);
112         }
113
114         return ret;
115 }
116
117 void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
118                         struct snd_soc_dai *dai)
119 {
120         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
121
122         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
123                 if (i2s->playback_ref_count == 1)
124                         tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
125
126                 /* free the apbif dma channel*/
127                 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
128
129                 /* decrement the playback ref count */
130                 i2s->playback_ref_count--;
131         } else {
132                 if (i2s->capture_ref_count == 1)
133                         tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
134                 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
135                 i2s->capture_ref_count--;
136         }
137 }
138
139 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
140                                 unsigned int fmt)
141 {
142         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
143         unsigned int mask, val;
144
145         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
146         case SND_SOC_DAIFMT_NB_NF:
147                 break;
148         default:
149                 return -EINVAL;
150         }
151
152         mask = TEGRA30_I2S_CTRL_MASTER_ENABLE;
153         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
154         case SND_SOC_DAIFMT_CBS_CFS:
155                 val = TEGRA30_I2S_CTRL_MASTER_ENABLE;
156                 break;
157         case SND_SOC_DAIFMT_CBM_CFM:
158                 break;
159         default:
160                 return -EINVAL;
161         }
162
163         mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
164                 TEGRA30_I2S_CTRL_LRCK_MASK;
165         i2s->reg_ch_ctrl &= ~TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK;
166         i2s->daifmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
167         switch (i2s->daifmt) {
168         case SND_SOC_DAIFMT_DSP_A:
169                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
170                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
171                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE;
172                 break;
173         case SND_SOC_DAIFMT_DSP_B:
174                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
175                 val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
176                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
177                 break;
178         case SND_SOC_DAIFMT_I2S:
179                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
180                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
181                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
182                 break;
183         case SND_SOC_DAIFMT_RIGHT_J:
184                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
185                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
186                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
187                 break;
188         case SND_SOC_DAIFMT_LEFT_J:
189                 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
190                 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
191                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
192                 break;
193         default:
194                 return -EINVAL;
195         }
196
197         pm_runtime_get_sync(dai->dev);
198         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
199         pm_runtime_put(dai->dev);
200
201         return 0;
202 }
203
204 static void tegra30_i2s_set_channel_bit_count(struct tegra30_i2s *i2s,
205                                 int i2sclock, int srate)
206 {
207         int sym_bitclk, bitcnt;
208         u32 val;
209
210         bitcnt = (i2sclock / (2 * srate)) - 1;
211         sym_bitclk = !(i2sclock % (2 * srate));
212
213         val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
214
215         if (!sym_bitclk)
216                 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
217
218         regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
219 }
220
221 static void tegra30_i2s_set_data_offset(struct tegra30_i2s *i2s)
222 {
223         u32 val;
224         int rx_data_offset = i2s->dsp_config.rx_data_offset;
225         int tx_data_offset = i2s->dsp_config.tx_data_offset;
226
227         val = (rx_data_offset <<
228                                 TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
229                         (tx_data_offset <<
230                                 TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
231
232         regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
233 }
234
235 static void tegra30_i2s_set_slot_control(struct tegra30_i2s *i2s, int stream)
236 {
237         u32 mask, val = 0;
238         int tx_mask = i2s->dsp_config.tx_mask;
239         int rx_mask = i2s->dsp_config.rx_mask;
240
241         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
242                 mask = TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK;
243                 val |= (tx_mask << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT);
244         } else {
245                 mask = TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK;
246                 val |= (rx_mask << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT);
247         }
248
249         mask |= TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK;
250         val |= (i2s->dsp_config.num_slots - 1)
251                         << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT;
252
253         regmap_update_bits(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, mask, val);
254 }
255
256 static int tegra30_i2s_tdm_setup_clocks(struct device *dev,
257                                 struct tegra30_i2s *i2s, int *i2sclock)
258 {
259         int ret;
260
261         if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_MASTER_ENABLE) {
262
263                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_pll_a_out0);
264                 if (ret) {
265                         dev_err(dev, "Can't set parent of I2S clock\n");
266                         return ret;
267                 }
268
269                 ret = clk_set_rate(i2s->clk_i2s, *i2sclock);
270                 if (ret) {
271                         dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
272                         return ret;
273                 }
274         } else {
275
276                 ret = clk_set_rate(i2s->clk_i2s_sync, *i2sclock);
277                 if (ret) {
278                         dev_err(dev, "Can't set I2S sync clock rate\n");
279                         return ret;
280                 }
281
282                 ret = clk_set_parent(clk_get_parent(i2s->clk_audio_2x),
283                                                 i2s->clk_i2s_sync);
284                 if (ret) {
285                         dev_err(dev, "Can't set parent of audio2x clock\n");
286                         return ret;
287                 }
288
289                 ret = clk_set_rate(i2s->clk_audio_2x, *i2sclock);
290                 if (ret) {
291                         dev_err(dev, "Can't set audio2x clock rate\n");
292                         return ret;
293                 }
294
295                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_audio_2x);
296                 if (ret) {
297                         dev_err(dev, "Can't set parent of i2s clock\n");
298                         return ret;
299                 }
300         }
301         return ret;
302 }
303
304
305 static int tegra30_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
306                                 struct snd_pcm_hw_params *params,
307                                 struct snd_soc_dai *dai)
308 {
309         struct device *dev = substream->pcm->card->dev;
310         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
311         u32 val;
312         int i2s_client_ch, i2s_audio_ch;
313         int i2s_audio_bits = 0, i2s_client_bits = 0;
314         int i2sclock, srate;
315         int ret;
316
317         srate = params_rate(params);
318
319         i2sclock = srate *
320                                 i2s->dsp_config.num_slots *
321                                 i2s->dsp_config.slot_width;
322
323         ret = tegra30_i2s_tdm_setup_clocks(dev, i2s, &i2sclock);
324         if (ret)
325                 return -EINVAL;
326
327         /* Run ahub clock greater than i2sclock */
328         tegra30_ahub_clock_set_rate(i2sclock*2);
329
330         tegra30_i2s_set_channel_bit_count(i2s, i2sclock*2, srate);
331
332         i2s_client_ch = i2s->dsp_config.num_slots;
333         i2s_audio_ch = i2s->dsp_config.num_slots;
334
335         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
336         switch (i2s->dsp_config.slot_width) {
337         case 16:
338                 i2s_audio_bits = TEGRA30_AUDIOCIF_BITS_16;
339                 i2s_client_bits = TEGRA30_AUDIOCIF_BITS_16;
340                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
341                 break;
342         case 32:
343                 i2s_audio_bits = TEGRA30_AUDIOCIF_BITS_32;
344                 i2s_client_bits = TEGRA30_AUDIOCIF_BITS_32;
345                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_32;
346                 break;
347         default:
348                 dev_err(dev, "unknown slot_width %d\n",
349                                 i2s->dsp_config.slot_width);
350                 return -EINVAL;
351         }
352
353         val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
354                         ((i2s_audio_ch - 1) <<
355                          TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
356                         ((i2s_client_ch - 1) <<
357                          TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
358                         (i2s_audio_bits <<
359                          TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
360                         (i2s_client_bits <<
361                          TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT);
362
363         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
364                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
365                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
366
367                 tegra30_ahub_set_tx_cif_channels(i2s->playback_fifo_cif,
368                                                 i2s_audio_ch,
369                                                 i2s_client_ch);
370                 tegra30_ahub_set_tx_cif_bits(i2s->playback_fifo_cif,
371                                                 i2s_audio_bits,
372                                                 i2s_client_bits);
373                 tegra30_ahub_set_tx_fifo_pack_mode(i2s->playback_fifo_cif, 0);
374
375         } else {
376                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
377                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
378
379                 tegra30_ahub_set_rx_cif_channels(i2s->capture_fifo_cif,
380                                                 i2s_audio_ch,
381                                                 i2s_client_ch);
382                 tegra30_ahub_set_rx_cif_bits(i2s->capture_fifo_cif,
383                                                 i2s_audio_bits,
384                                                 i2s_client_bits);
385                 tegra30_ahub_set_rx_fifo_pack_mode(i2s->capture_fifo_cif, 0);
386         }
387
388         tegra30_i2s_set_slot_control(i2s, substream->stream);
389
390         tegra30_i2s_set_data_offset(i2s);
391
392         i2s->reg_ch_ctrl &= ~TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK;
393         i2s->reg_ch_ctrl |= (i2s->dsp_config.slot_width - 1) <<
394                         TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT;
395         tegra30_i2s_write(i2s, TEGRA30_I2S_CH_CTRL, i2s->reg_ch_ctrl);
396
397         return 0;
398 }
399
400 static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
401                                  struct snd_pcm_hw_params *params,
402                                  struct snd_soc_dai *dai)
403 {
404         struct device *dev = dai->dev;
405         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
406         unsigned int mask, val, reg, i;
407         int ret, sample_size, srate, i2sclock, bitcnt, sym_bitclk;
408         int i2s_client_ch;
409
410         mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
411         switch (params_format(params)) {
412         case SNDRV_PCM_FORMAT_S8:
413                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_8;
414                 sample_size = 8;
415                 break;
416         case SNDRV_PCM_FORMAT_S16_LE:
417                 val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
418                 sample_size = 16;
419                 break;
420         case SNDRV_PCM_FORMAT_S24_LE:
421                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_24;
422                 sample_size = 24;
423                 break;
424         case SNDRV_PCM_FORMAT_S32_LE:
425                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_32;
426                 sample_size = 32;
427                 break;
428         default:
429                 return -EINVAL;
430         }
431
432         regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
433
434         bitcnt = sample_size;
435         i = 0;
436
437         /* TDM mode */
438         if ((i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC) &&
439                 (i2s->dsp_config.slot_width > 2))
440                 return tegra30_i2s_tdm_hw_params(substream, params, dai);
441
442         srate = params_rate(params);
443
444         if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_MASTER_ENABLE) {
445                 i2sclock = srate * params_channels(params) * sample_size;
446
447                 /* Additional "* 4" is needed for FSYNC mode */
448                 if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC)
449                         i2sclock *= 4;
450
451                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_pll_a_out0);
452                 if (ret) {
453                         dev_err(dev, "Can't set parent of I2S clock\n");
454                         return ret;
455                 }
456
457                 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
458                 if (ret) {
459                         dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
460                         return ret;
461                 }
462
463                 if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC) {
464                         bitcnt = (i2sclock / srate) - 1;
465                         sym_bitclk = !(i2sclock % srate);
466 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
467                         val = tegra30_i2s_read(i2s, TEGRA30_I2S_SLOT_CTRL2);
468
469                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
470                                 val &=
471                                   ~TEGRA30_I2S_SLOT_CTRL2_TX_SLOT_ENABLES_MASK;
472                                 val |= ((1 << params_channels(params)) - 1) <<
473                                   TEGRA30_I2S_SLOT_CTRL2_TX_SLOT_ENABLES_SHIFT;
474                         } else {
475                                 val &=
476                                   ~TEGRA30_I2S_SLOT_CTRL2_RX_SLOT_ENABLES_MASK;
477                                 val |= ((1 << params_channels(params)) - 1) <<
478                                   TEGRA30_I2S_SLOT_CTRL2_RX_SLOT_ENABLES_SHIFT;
479                         }
480                         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL2, val);
481 #endif
482                 } else {
483                         bitcnt = (i2sclock / (2 * srate)) - 1;
484                         sym_bitclk = !(i2sclock % (2 * srate));
485                         i2s_client_ch = 2;
486                 }
487                 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
488
489                 if (!sym_bitclk)
490                         val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
491
492                 regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
493         } else {
494                 i2sclock = srate * params_channels(params) * sample_size;
495
496                 /* Additional "* 2" is needed for FSYNC mode */
497                 if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC)
498                         i2sclock *= 2;
499
500                 ret = clk_set_rate(i2s->clk_i2s_sync, i2sclock);
501                 if (ret) {
502                         dev_err(dev, "Can't set I2S sync clock rate\n");
503                         return ret;
504                 }
505
506                 ret = clk_set_parent(clk_get_parent(i2s->clk_audio_2x),
507                                                 i2s->clk_i2s_sync);
508                 if (ret) {
509                         dev_err(dev, "Can't set parent of audio2x clock\n");
510                         return ret;
511                 }
512
513                 ret = clk_set_rate(i2s->clk_audio_2x, i2sclock);
514                 if (ret) {
515                         dev_err(dev, "Can't set I2S sync clock rate\n");
516                         return ret;
517                 }
518
519                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_audio_2x);
520                 if (ret) {
521                         dev_err(dev, "Can't set parent of audio2x clock\n");
522                         return ret;
523                 }
524         }
525
526         i2s_client_ch = (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC) ?
527                         params_channels(params) : 2;
528
529         switch (sample_size) {
530         case 8:
531                 val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
532               ((params_channels(params) - 1) <<
533                         TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
534               ((i2s_client_ch - 1) <<
535                         TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
536               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8 |
537               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8;
538                 break;
539
540         case 16:
541                 val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
542               ((params_channels(params) - 1) <<
543                         TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
544               ((i2s_client_ch - 1) <<
545                         TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
546               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
547               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
548                 break;
549
550         case 24:
551                 val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
552               ((params_channels(params) - 1) <<
553                         TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
554               ((i2s_client_ch - 1) <<
555                         TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
556               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24 |
557               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24;
558                 break;
559
560         case 32:
561                 val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
562               ((params_channels(params) - 1) <<
563                         TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
564               ((i2s_client_ch - 1) <<
565                         TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
566               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32 |
567               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32;
568                 break;
569
570         default:
571                 pr_err("Error in sample size\n");
572                 val = 0;
573                 break;
574         }
575
576         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
577                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
578                 reg = TEGRA30_I2S_CIF_RX_CTRL;
579
580                 tegra30_ahub_set_tx_cif_channels(i2s->playback_fifo_cif,
581                                                  params_channels(params),
582                                                  params_channels(params));
583
584                 switch (sample_size) {
585                 case 8:
586                         tegra30_ahub_set_tx_cif_bits(i2s->playback_fifo_cif,
587                           TEGRA30_AUDIOCIF_BITS_8, TEGRA30_AUDIOCIF_BITS_8);
588                         tegra30_ahub_set_tx_fifo_pack_mode(i2s->playback_fifo_cif,
589                           TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4);
590                         break;
591
592                 case 16:
593                         tegra30_ahub_set_tx_cif_bits(i2s->playback_fifo_cif,
594                           TEGRA30_AUDIOCIF_BITS_16, TEGRA30_AUDIOCIF_BITS_16);
595                         tegra30_ahub_set_tx_fifo_pack_mode(i2s->playback_fifo_cif,
596                           TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16);
597                         break;
598
599                 case 24:
600                         tegra30_ahub_set_tx_cif_bits(i2s->playback_fifo_cif,
601                           TEGRA30_AUDIOCIF_BITS_24, TEGRA30_AUDIOCIF_BITS_24);
602                         tegra30_ahub_set_tx_fifo_pack_mode(i2s->playback_fifo_cif, 0);
603                         break;
604
605                 case 32:
606                         tegra30_ahub_set_tx_cif_bits(i2s->playback_fifo_cif,
607                           TEGRA30_AUDIOCIF_BITS_32, TEGRA30_AUDIOCIF_BITS_32);
608                         tegra30_ahub_set_tx_fifo_pack_mode(i2s->playback_fifo_cif, 0);
609                         break;
610
611                 default:
612                         pr_err("Error in sample_size\n");
613                         break;
614                 }
615         } else {
616                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
617                 reg = TEGRA30_I2S_CIF_TX_CTRL;
618
619                 tegra30_ahub_set_rx_cif_channels(i2s->capture_fifo_cif,
620                                                  params_channels(params),
621                                                  params_channels(params));
622
623                 switch (sample_size) {
624                 case 8:
625                         tegra30_ahub_set_rx_cif_bits(i2s->capture_fifo_cif,
626                           TEGRA30_AUDIOCIF_BITS_8, TEGRA30_AUDIOCIF_BITS_8);
627                         tegra30_ahub_set_rx_fifo_pack_mode(i2s->capture_fifo_cif,
628                           TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4);
629                         break;
630
631                 case 16:
632                         tegra30_ahub_set_rx_cif_bits(i2s->capture_fifo_cif,
633                           TEGRA30_AUDIOCIF_BITS_16, TEGRA30_AUDIOCIF_BITS_16);
634                         tegra30_ahub_set_rx_fifo_pack_mode(i2s->capture_fifo_cif,
635                           TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16);
636                         break;
637
638                 case 24:
639                         tegra30_ahub_set_rx_cif_bits(i2s->capture_fifo_cif,
640                           TEGRA30_AUDIOCIF_BITS_24, TEGRA30_AUDIOCIF_BITS_24);
641                         tegra30_ahub_set_rx_fifo_pack_mode(i2s->capture_fifo_cif, 0);
642                         break;
643
644                 case 32:
645                         tegra30_ahub_set_rx_cif_bits(i2s->capture_fifo_cif,
646                           TEGRA30_AUDIOCIF_BITS_32, TEGRA30_AUDIOCIF_BITS_32);
647                         tegra30_ahub_set_rx_fifo_pack_mode(i2s->capture_fifo_cif, 0);
648                         break;
649
650                 default:
651                         pr_err("Error in sample_size\n");
652                         break;
653                 }
654         }
655
656         regmap_write(i2s->regmap, reg, val);
657
658         switch (i2s->daifmt) {
659         case SND_SOC_DAIFMT_RIGHT_J:
660                 val = 0;
661                 if ((bitcnt - sample_size) > 0)
662                         val = bitcnt - sample_size;
663                 break;
664         case SND_SOC_DAIFMT_DSP_B:
665         case SND_SOC_DAIFMT_LEFT_J:
666                 val = 0;
667                 break;
668         case SND_SOC_DAIFMT_I2S:
669         case SND_SOC_DAIFMT_DSP_A: /* fall through */
670                 val = 1;
671                 break;
672         default:
673                 return -EINVAL;
674         }
675         val = (val << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
676                   (val << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
677         regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
678
679         tegra30_i2s_write(i2s, TEGRA30_I2S_CH_CTRL, i2s->reg_ch_ctrl);
680
681         val = 0;
682 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
683         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
684                 mask = TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK;
685                 val |= (1 << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT);
686         } else {
687                 mask = TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK;
688                 val |= (1 << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT);
689         }
690         regmap_update_bits(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, mask, val);
691 #else
692         if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC)
693                 val = params_channels(params) - 1;
694         regmap_write(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, val);
695 #endif
696
697         return 0;
698 }
699
700 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
701 {
702         tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
703         /* if this is the only user of i2s tx then enable it*/
704         if (i2s->playback_ref_count == 1)
705                 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
706                                    TEGRA30_I2S_CTRL_XFER_EN_TX,
707                                    TEGRA30_I2S_CTRL_XFER_EN_TX);
708 }
709
710 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
711 {
712         int dcnt = 10;
713         /* if this is the only user of i2s tx then disable it*/
714         tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
715         if (i2s->playback_ref_count == 1)
716                 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
717                                    TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
718         while (!tegra30_ahub_tx_fifo_is_empty(i2s->id) && dcnt--)
719                 udelay(100);
720 }
721
722 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
723 {
724         tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
725         if (!i2s->is_call_mode_rec && (i2s->capture_ref_count == 1))
726                 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
727                                    TEGRA30_I2S_CTRL_XFER_EN_RX,
728                                    TEGRA30_I2S_CTRL_XFER_EN_RX);
729 }
730
731 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
732 {
733         int dcnt = 10;
734         if (!i2s->is_call_mode_rec && (i2s->capture_ref_count == 1)) {
735                 tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
736                 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
737                                    TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
738                 while (tegra30_ahub_rx_fifo_is_enabled(i2s->id) && dcnt--)
739                         udelay(100);
740         }
741
742         while (!tegra30_ahub_rx_fifo_is_empty(i2s->id) && dcnt--)
743                 udelay(100);
744 }
745
746 static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
747                                 struct snd_soc_dai *dai)
748 {
749         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
750
751         switch (cmd) {
752         case SNDRV_PCM_TRIGGER_START:
753         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
754         case SNDRV_PCM_TRIGGER_RESUME:
755                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
756                         tegra30_i2s_start_playback(i2s);
757                 else
758                         tegra30_i2s_start_capture(i2s);
759                 break;
760         case SNDRV_PCM_TRIGGER_STOP:
761         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
762         case SNDRV_PCM_TRIGGER_SUSPEND:
763                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
764                         tegra30_i2s_stop_playback(i2s);
765                 else
766                         tegra30_i2s_stop_capture(i2s);
767                 break;
768         default:
769                 return -EINVAL;
770         }
771
772         return 0;
773 }
774
775 static int tegra30_i2s_probe(struct snd_soc_dai *dai)
776 {
777         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
778
779         dai->capture_dma_data = &i2s->capture_dma_data;
780         dai->playback_dma_data = &i2s->playback_dma_data;
781
782         /* Default values for DSP mode */
783         i2s->dsp_config.num_slots = 1;
784         i2s->dsp_config.slot_width = 2;
785         i2s->dsp_config.tx_mask = 1;
786         i2s->dsp_config.rx_mask = 1;
787         i2s->dsp_config.rx_data_offset = 1;
788         i2s->dsp_config.tx_data_offset = 1;
789
790
791         return 0;
792 }
793
794 int tegra30_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai,
795                                                         unsigned int tx_mask,
796                                                         unsigned int rx_mask,
797                                                         int slots,
798                                                         int slot_width)
799 {
800         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
801
802         i2s->dsp_config.num_slots = slots;
803         i2s->dsp_config.slot_width = slot_width;
804         i2s->dsp_config.tx_mask = tx_mask;
805         i2s->dsp_config.rx_mask = rx_mask;
806         i2s->dsp_config.rx_data_offset = 0;
807         i2s->dsp_config.tx_data_offset = 0;
808
809         return 0;
810 }
811
812 #ifdef CONFIG_PM
813 int tegra30_i2s_resume(struct snd_soc_dai *cpu_dai)
814 {
815         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
816         int ret = 0;
817
818         //tegra30_ahub_apbif_resume();
819
820         if (i2s->dam_ch_refcount)
821                 ret = tegra30_dam_resume(i2s->dam_ifc);
822
823         return ret;
824 }
825 #else
826 #define tegra30_i2s_resume NULL
827 #endif
828
829 static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
830         .startup        = tegra30_i2s_startup,
831         .shutdown       = tegra30_i2s_shutdown,
832         .set_fmt        = tegra30_i2s_set_fmt,
833         .hw_params      = tegra30_i2s_hw_params,
834         .trigger        = tegra30_i2s_trigger,
835         .set_tdm_slot = tegra30_i2s_set_tdm_slot,
836 };
837
838 static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
839         .probe = tegra30_i2s_probe,
840         .resume = tegra30_i2s_resume,
841         .playback = {
842                 .stream_name = "Playback",
843                 .channels_min = 1,
844                 .channels_max = 16,
845                 .rates = SNDRV_PCM_RATE_8000_96000,
846                 .formats = SNDRV_PCM_FMTBIT_S8 |
847                            SNDRV_PCM_FMTBIT_S16_LE |
848                            SNDRV_PCM_FMTBIT_S24_LE |
849                            SNDRV_PCM_FMTBIT_S32_LE,
850         },
851         .capture = {
852                 .stream_name = "Capture",
853                 .channels_min = 1,
854                 .channels_max = 16,
855                 .rates = SNDRV_PCM_RATE_8000_96000,
856                 .formats = SNDRV_PCM_FMTBIT_S8 |
857                            SNDRV_PCM_FMTBIT_S16_LE |
858                            SNDRV_PCM_FMTBIT_S24_LE |
859                            SNDRV_PCM_FMTBIT_S32_LE,
860         },
861         .ops = &tegra30_i2s_dai_ops,
862         .symmetric_rates = 1,
863 };
864
865 static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
866 {
867         switch (reg) {
868         case TEGRA30_I2S_CTRL:
869         case TEGRA30_I2S_TIMING:
870         case TEGRA30_I2S_OFFSET:
871         case TEGRA30_I2S_CH_CTRL:
872         case TEGRA30_I2S_SLOT_CTRL:
873         case TEGRA30_I2S_CIF_RX_CTRL:
874         case TEGRA30_I2S_CIF_TX_CTRL:
875         case TEGRA30_I2S_FLOWCTL:
876         case TEGRA30_I2S_TX_STEP:
877         case TEGRA30_I2S_FLOW_STATUS:
878         case TEGRA30_I2S_FLOW_TOTAL:
879         case TEGRA30_I2S_FLOW_OVER:
880         case TEGRA30_I2S_FLOW_UNDER:
881         case TEGRA30_I2S_LCOEF_1_4_0:
882         case TEGRA30_I2S_LCOEF_1_4_1:
883         case TEGRA30_I2S_LCOEF_1_4_2:
884         case TEGRA30_I2S_LCOEF_1_4_3:
885         case TEGRA30_I2S_LCOEF_1_4_4:
886         case TEGRA30_I2S_LCOEF_1_4_5:
887         case TEGRA30_I2S_LCOEF_2_4_0:
888         case TEGRA30_I2S_LCOEF_2_4_1:
889         case TEGRA30_I2S_LCOEF_2_4_2:
890                 return true;
891         default:
892                 return false;
893         };
894 }
895
896 static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
897 {
898         switch (reg) {
899         case TEGRA30_I2S_FLOW_STATUS:
900         case TEGRA30_I2S_FLOW_TOTAL:
901         case TEGRA30_I2S_FLOW_OVER:
902         case TEGRA30_I2S_FLOW_UNDER:
903                 return true;
904         default:
905                 return false;
906         };
907 }
908
909 static const struct regmap_config tegra30_i2s_regmap_config = {
910         .reg_bits = 32,
911         .reg_stride = 4,
912         .val_bits = 32,
913         .max_register = TEGRA30_I2S_LCOEF_2_4_2,
914         .writeable_reg = tegra30_i2s_wr_rd_reg,
915         .readable_reg = tegra30_i2s_wr_rd_reg,
916         .volatile_reg = tegra30_i2s_volatile_reg,
917         .cache_type = REGCACHE_RBTREE,
918 };
919
920 static int configure_baseband_i2s(struct tegra30_i2s  *i2s, int is_i2smaster,
921                 int i2s_mode, int channels, int rate, int bitsize, int bit_clk)
922 {
923         u32 val;
924         int i2sclock, bitcnt, ret, is_formatdsp;
925 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
926         u32  i;
927 #endif
928
929         is_formatdsp = (i2s_mode == TEGRA_DAIFMT_DSP_A) ||
930                                         (i2s_mode == TEGRA_DAIFMT_DSP_B);
931
932         if (bit_clk) {
933                 i2sclock = bit_clk;
934         } else {
935             i2sclock = rate * channels * bitsize * 2;
936             /* additional 8 for baseband */
937                 if (is_formatdsp)
938                         i2sclock *= 8;
939         }
940
941         if (is_i2smaster) {
942                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_pll_a_out0);
943                 if (ret) {
944                         pr_err("Can't set parent of I2S clock\n");
945                         return ret;
946                 }
947
948                 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
949                 if (ret) {
950                         pr_err("Can't set I2S clock rate: %d\n", ret);
951                         return ret;
952                 }
953         } else {
954                 ret = clk_set_rate(i2s->clk_i2s_sync, i2sclock);
955                 if (ret) {
956                         pr_err("Can't set I2S sync clock rate\n");
957                         return ret;
958                 }
959
960                 ret = clk_set_rate(i2s->clk_audio_2x, i2sclock);
961                 if (ret) {
962                         pr_err("Can't set I2S sync clock rate\n");
963                         return ret;
964                 }
965
966                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_audio_2x);
967                 if (ret) {
968                         pr_err("Can't set parent of audio2x clock\n");
969                         return ret;
970                 }
971         }
972
973         i2s->reg_ctrl &= ~(TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
974                                         TEGRA30_I2S_CTRL_LRCK_MASK |
975                                         TEGRA30_I2S_CTRL_MASTER_ENABLE);
976         i2s->reg_ch_ctrl &= ~TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK;
977
978         i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
979
980         if (is_i2smaster)
981                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
982
983         if (i2s_mode == TEGRA_DAIFMT_DSP_A) {
984                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
985                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
986                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE;
987         } else if (i2s_mode == TEGRA_DAIFMT_DSP_B) {
988                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
989                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
990                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
991         } else {
992                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
993                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
994                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
995         }
996
997         tegra30_i2s_write(i2s, TEGRA30_I2S_CH_CTRL, i2s->reg_ch_ctrl);
998
999 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
1000         val = 0;
1001         for (i = 0; i < channels; i++)
1002                 val |= (1 << i);
1003
1004         val |= val <<
1005           TEGRA30_I2S_SLOT_CTRL2_TX_SLOT_ENABLES_SHIFT;
1006         val |= val <<
1007           TEGRA30_I2S_SLOT_CTRL2_RX_SLOT_ENABLES_SHIFT;
1008         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL2, val);
1009
1010         val = 0;
1011         if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC)
1012                 val = channels  - 1;
1013
1014         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
1015 #else
1016         val = tegra30_i2s_read(i2s, TEGRA30_I2S_SLOT_CTRL);
1017         val &= ~(TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK |
1018                 TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK);
1019         val |= (1 << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT |
1020                 1 << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT);
1021         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
1022 #endif
1023
1024         val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
1025               (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
1026         tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
1027
1028         if (is_formatdsp) {
1029                 bitcnt = (i2sclock/rate) - 1;
1030                 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
1031                 if (i2sclock % (rate))
1032                         val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
1033         } else {
1034                 bitcnt = (i2sclock/(2*rate)) - 1;
1035                 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
1036                 if (i2sclock % (2*rate))
1037                         val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
1038         }
1039
1040         tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
1041
1042         /* configure the i2s cif*/
1043         val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
1044               ((channels - 1) << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
1045               ((channels - 1) << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
1046               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
1047               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
1048         val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
1049         tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
1050
1051         val &= ~TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK;
1052         val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
1053         tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
1054
1055         return 0;
1056 }
1057
1058 static int configure_dam(struct tegra30_i2s  *i2s, int out_channel,
1059                 int out_rate, int out_bitsize, int in_channels,
1060                 int in_rate, int in_bitsize)
1061 {
1062
1063         if (!i2s->dam_ch_refcount)
1064                 i2s->dam_ifc = tegra30_dam_allocate_controller();
1065
1066         if (i2s->dam_ifc < 0)
1067                 return -ENOENT;
1068
1069         tegra30_dam_allocate_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC);
1070         i2s->dam_ch_refcount++;
1071         tegra30_dam_enable_clock(i2s->dam_ifc);
1072         tegra30_dam_set_samplerate(i2s->dam_ifc, TEGRA30_DAM_CHOUT, out_rate);
1073         tegra30_dam_set_samplerate(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC,
1074                                 in_rate);
1075         tegra30_dam_set_gain(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC, 0x1000);
1076 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
1077         tegra30_dam_set_acif(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC,
1078                         in_channels, in_bitsize, 1, 32);
1079         tegra30_dam_set_acif(i2s->dam_ifc, TEGRA30_DAM_CHOUT,
1080                         out_channel, out_bitsize, out_channel, 32);
1081 #else
1082         tegra30_dam_set_acif(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC,
1083                         in_channels, in_bitsize, 1, 16);
1084         tegra30_dam_set_acif(i2s->dam_ifc, TEGRA30_DAM_CHOUT,
1085                         out_channel, out_bitsize, out_channel, out_bitsize);
1086 #endif
1087
1088 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
1089         if (in_rate != out_rate) {
1090                 tegra30_dam_write_coeff_ram(i2s->dam_ifc, in_rate, out_rate);
1091                 tegra30_dam_set_farrow_param(i2s->dam_ifc, in_rate, out_rate);
1092                 tegra30_dam_set_biquad_fixed_coef(i2s->dam_ifc);
1093                 tegra30_dam_enable_coeff_ram(i2s->dam_ifc);
1094                 tegra30_dam_set_filter_stages(i2s->dam_ifc, in_rate, out_rate);
1095         } else {
1096                 tegra30_dam_enable_stereo_mixing(i2s->dam_ifc);
1097         }
1098 #endif
1099
1100         return 0;
1101 }
1102
1103
1104 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1105 int t14x_make_voice_call_connections(struct codec_config *codec_info,
1106                                 struct ahub_bbc1_config *bb_info,
1107                                 int uses_voice_codec)
1108 {
1109         struct tegra30_i2s *codec_i2s = &i2scont[codec_info->i2s_id];
1110         struct tegra30_i2s *bb_i2s = &bbc1cont;
1111
1112         /* increment the codec i2s playback ref count */
1113         codec_i2s->playback_ref_count++;
1114         bb_i2s->playback_ref_count++;
1115         codec_i2s->capture_ref_count++;
1116         bb_i2s->capture_ref_count++;
1117
1118         /*Configure codec i2s*/
1119         configure_baseband_i2s(codec_i2s, codec_info->is_i2smaster,
1120                 codec_info->i2s_mode, codec_info->channels,
1121                 codec_info->rate, codec_info->bitsize, codec_info->bit_clk);
1122
1123         if (uses_voice_codec) {
1124                 /* The following two lines are a hack */
1125                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_APBIF_RX0);
1126                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0+1);
1127
1128                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1129                             bb_info->port_id, TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1130                             codec_info->i2s_id);
1131                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1132                             codec_info->i2s_id, TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1133                             bb_info->port_id);
1134         } else {
1135
1136                 /*configure codec dam*/
1137                 configure_dam(codec_i2s, codec_info->channels,
1138                    codec_info->rate, codec_info->bitsize, bb_info->channels,
1139                    bb_info->rate, bb_info->sample_size);
1140
1141                 /*configure bb dam*/
1142                 configure_dam(bb_i2s, bb_info->channels,
1143                         bb_info->rate, bb_info->sample_size, codec_info->channels,
1144                         codec_info->rate, codec_info->bitsize);
1145
1146                 /*make ahub connections*/
1147
1148                 /*if this is the only user of i2s tx, make i2s rx connection*/
1149                 if (codec_i2s->playback_ref_count == 1) {
1150                         tegra30_ahub_set_rx_cif_source(
1151                           TEGRA30_AHUB_RXCIF_I2S0_RX0 + codec_info->i2s_id,
1152                           TEGRA30_AHUB_TXCIF_DAM0_TX0 + codec_i2s->dam_ifc);
1153                 }
1154
1155                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_BBC1_RX0,
1156                                 TEGRA30_AHUB_TXCIF_DAM0_TX0 + bb_i2s->dam_ifc);
1157                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
1158                         (codec_i2s->dam_ifc*2), TEGRA30_AHUB_TXCIF_BBC1_TX0);
1159                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
1160                         (bb_i2s->dam_ifc*2), TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1161                         codec_info->i2s_id);
1162
1163                 /*enable dam and i2s*/
1164                 tegra30_dam_enable(codec_i2s->dam_ifc, TEGRA30_DAM_ENABLE,
1165                         TEGRA30_DAM_CHIN0_SRC);
1166                 tegra30_dam_enable(bb_i2s->dam_ifc, TEGRA30_DAM_ENABLE,
1167                         TEGRA30_DAM_CHIN0_SRC);
1168         }
1169
1170         codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
1171         codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
1172         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
1173                 codec_i2s->reg_ctrl);
1174
1175         return 0;
1176 }
1177
1178 int t14x_break_voice_call_connections(struct codec_config *codec_info,
1179                                 struct ahub_bbc1_config *bb_info,
1180                                 int uses_voice_codec)
1181 {
1182         struct tegra30_i2s *codec_i2s = &i2scont[codec_info->i2s_id];
1183         struct tegra30_i2s *bb_i2s = &bbc1cont;
1184         int dcnt = 10;
1185
1186         /*Disable Codec I2S RX (TX to ahub)*/
1187         if (codec_i2s->capture_ref_count == 1)
1188                 codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1189
1190         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL, codec_i2s->reg_ctrl);
1191
1192         while (!tegra30_ahub_rx_fifo_is_empty(codec_i2s->id) && dcnt--)
1193                 udelay(100);
1194
1195         dcnt = 10;
1196
1197         /*Disable Codec I2S TX (RX from ahub)*/
1198         if (codec_i2s->playback_ref_count == 1)
1199                         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1200
1201         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL, codec_i2s->reg_ctrl);
1202
1203         while (!tegra30_ahub_tx_fifo_is_empty(codec_i2s->id) && dcnt--)
1204                 udelay(100);
1205
1206         dcnt = 10;
1207
1208         if (uses_voice_codec) {
1209                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1210                             bb_info->port_id);
1211                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1212                             codec_info->i2s_id);
1213         } else {
1214
1215                 /*Disable baseband DAM*/
1216                 tegra30_dam_enable(bb_i2s->dam_ifc, TEGRA30_DAM_DISABLE,
1217                                 TEGRA30_DAM_CHIN0_SRC);
1218                 tegra30_dam_free_channel(bb_i2s->dam_ifc,
1219                                 TEGRA30_DAM_CHIN0_SRC);
1220                 bb_i2s->dam_ch_refcount--;
1221                 if (!bb_i2s->dam_ch_refcount)
1222                         tegra30_dam_free_controller(bb_i2s->dam_ifc);
1223
1224                 /*Disable Codec DAM*/
1225                 tegra30_dam_enable(codec_i2s->dam_ifc,
1226                         TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN0_SRC);
1227                 tegra30_dam_free_channel(codec_i2s->dam_ifc,
1228                         TEGRA30_DAM_CHIN0_SRC);
1229                 codec_i2s->dam_ch_refcount--;
1230                 if (!codec_i2s->dam_ch_refcount)
1231                         tegra30_dam_free_controller(codec_i2s->dam_ifc);
1232
1233                 /* Disconnect the ahub connections */
1234                 /* If this is the only user of i2s tx then break ahub
1235                 i2s rx connection */
1236                 if (codec_i2s->playback_ref_count == 1)
1237                         tegra30_ahub_unset_rx_cif_source(
1238                            TEGRA30_AHUB_RXCIF_I2S0_RX0 + codec_info->i2s_id);
1239
1240                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_BBC1_RX0);
1241                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0
1242                                         + (codec_i2s->dam_ifc*2));
1243                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0
1244                                         + (bb_i2s->dam_ifc*2));
1245
1246                 tegra30_dam_disable_clock(codec_i2s->dam_ifc);
1247                 tegra30_dam_disable_clock(bb_i2s->dam_ifc);
1248         }
1249
1250         /* Decrement the codec and bb i2s playback ref count */
1251         codec_i2s->playback_ref_count--;
1252         bb_i2s->playback_ref_count--;
1253         codec_i2s->capture_ref_count--;
1254         bb_i2s->capture_ref_count--;
1255
1256         /* Soft reset */
1257         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
1258                 codec_i2s->reg_ctrl | TEGRA30_I2S_CTRL_SOFT_RESET);
1259
1260         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1261         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_SOFT_RESET;
1262
1263         while ((tegra30_i2s_read(codec_i2s, TEGRA30_I2S_CTRL) &
1264                         TEGRA30_I2S_CTRL_SOFT_RESET)  && dcnt--)
1265                 udelay(100);
1266         dcnt = 10;
1267
1268         /* Disable the clocks */
1269         tegra30_i2s_disable_clocks(codec_i2s);
1270
1271         return 0;
1272 }
1273 #endif
1274
1275 int tegra30_make_voice_call_connections(struct codec_config *codec_info,
1276                                 struct codec_config *bb_info,
1277                                 int uses_voice_codec)
1278 {
1279         struct tegra30_i2s  *codec_i2s;
1280         struct tegra30_i2s  *bb_i2s;
1281         int reg;
1282
1283         codec_i2s = &i2scont[codec_info->i2s_id];
1284         bb_i2s = &i2scont[bb_info->i2s_id];
1285
1286         /* increment the codec i2s playback ref count */
1287         codec_i2s->playback_ref_count++;
1288         bb_i2s->playback_ref_count++;
1289         codec_i2s->capture_ref_count++;
1290         bb_i2s->capture_ref_count++;
1291
1292         /* Make sure i2s is disabled during the configiration */
1293         tegra30_i2s_enable_clocks(codec_i2s);
1294         reg = codec_i2s->reg_ctrl;
1295         reg &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1296         reg &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1297         reg &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1298         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
1299                 codec_i2s->reg_ctrl);
1300         tegra30_i2s_disable_clocks(codec_i2s);
1301
1302         tegra30_i2s_enable_clocks(bb_i2s);
1303         reg = bb_i2s->reg_ctrl;
1304         reg &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1305         reg &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1306         reg &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1307         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL,
1308                 bb_i2s->reg_ctrl);
1309         tegra30_i2s_disable_clocks(bb_i2s);
1310
1311         msleep(20);
1312
1313         /*Configure codec i2s*/
1314         configure_baseband_i2s(codec_i2s, codec_info->is_i2smaster,
1315                 codec_info->i2s_mode, codec_info->channels,
1316                 codec_info->rate, codec_info->bitsize, codec_info->bit_clk);
1317
1318         /*Configure bb i2s*/
1319         configure_baseband_i2s(bb_i2s, bb_info->is_i2smaster,
1320                 bb_info->i2s_mode, bb_info->channels,
1321                 bb_info->rate, bb_info->bitsize, bb_info->bit_clk);
1322
1323         if (uses_voice_codec) {
1324                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_APBIF_RX0 +
1325                         codec_info->i2s_id);
1326                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_APBIF_RX0 +
1327                         bb_info->i2s_id);
1328
1329                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1330                             bb_info->i2s_id, TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1331                             codec_info->i2s_id);
1332                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1333                             codec_info->i2s_id, TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1334                             bb_info->i2s_id);
1335                 if (!(codec_info->is_i2smaster && bb_info->is_i2smaster)) {
1336                         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_FLOWCTL,
1337                                 TEGRA30_I2S_FILTER_QUAD);
1338                         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_FLOWCTL,
1339                                 TEGRA30_I2S_FILTER_QUAD);
1340                         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_TX_STEP, 4);
1341                         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_TX_STEP, 4);
1342                         codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1343                         bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1344                 }
1345         } else {
1346
1347                 /*configure codec dam*/
1348                 configure_dam(codec_i2s, codec_info->channels,
1349                    codec_info->rate, codec_info->bitsize, bb_info->channels,
1350                    bb_info->rate, bb_info->bitsize);
1351
1352                 /*configure bb dam*/
1353                 configure_dam(bb_i2s, bb_info->channels,
1354                         bb_info->rate, bb_info->bitsize, codec_info->channels,
1355                         codec_info->rate, codec_info->bitsize);
1356
1357                 /*make ahub connections*/
1358
1359                 /*if this is the only user of i2s tx, make i2s rx connection*/
1360                 if (codec_i2s->playback_ref_count == 1) {
1361                         tegra30_ahub_set_rx_cif_source(
1362                           TEGRA30_AHUB_RXCIF_I2S0_RX0 + codec_info->i2s_id,
1363                           TEGRA30_AHUB_TXCIF_DAM0_TX0 + codec_i2s->dam_ifc);
1364                 }
1365
1366                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1367                                 bb_info->i2s_id, TEGRA30_AHUB_TXCIF_DAM0_TX0 +
1368                                 bb_i2s->dam_ifc);
1369                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
1370                         (codec_i2s->dam_ifc*2), TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1371                         bb_info->i2s_id);
1372                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
1373                         (bb_i2s->dam_ifc*2), TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1374                         codec_info->i2s_id);
1375
1376                 /*enable dam and i2s*/
1377                 tegra30_dam_enable(codec_i2s->dam_ifc, TEGRA30_DAM_ENABLE,
1378                         TEGRA30_DAM_CHIN0_SRC);
1379                 tegra30_dam_enable(bb_i2s->dam_ifc, TEGRA30_DAM_ENABLE,
1380                         TEGRA30_DAM_CHIN0_SRC);
1381         }
1382
1383         msleep(20);
1384
1385         codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
1386         codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
1387         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
1388                 codec_i2s->reg_ctrl);
1389
1390         msleep(20);
1391
1392         bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
1393         bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
1394         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL,
1395                 bb_i2s->reg_ctrl);
1396
1397         return 0;
1398 }
1399
1400 int tegra30_break_voice_call_connections(struct codec_config *codec_info,
1401                                 struct codec_config *bb_info,
1402                                 int uses_voice_codec)
1403 {
1404         struct tegra30_i2s  *codec_i2s;
1405         struct tegra30_i2s  *bb_i2s;
1406         int dcnt = 10;
1407
1408         codec_i2s = &i2scont[codec_info->i2s_id];
1409         bb_i2s = &i2scont[bb_info->i2s_id];
1410
1411         /*Disable Codec I2S RX (TX to ahub)*/
1412         if (codec_i2s->capture_ref_count == 1)
1413                 codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1414
1415         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL, codec_i2s->reg_ctrl);
1416
1417         while (!tegra30_ahub_rx_fifo_is_empty(codec_i2s->id) && dcnt--)
1418                 udelay(100);
1419
1420         dcnt = 10;
1421
1422         /*Disable baseband I2S TX (RX from ahub)*/
1423         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1424         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL, bb_i2s->reg_ctrl);
1425
1426         while (!tegra30_ahub_tx_fifo_is_empty(bb_i2s->id) && dcnt--)
1427                 udelay(100);
1428
1429         dcnt = 10;
1430
1431         /*Disable baseband I2S RX (TX to ahub)*/
1432         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1433         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL, bb_i2s->reg_ctrl);
1434
1435         while (!tegra30_ahub_rx_fifo_is_empty(bb_i2s->id) && dcnt--)
1436                 udelay(100);
1437
1438         dcnt = 10;
1439
1440         /*Disable Codec I2S TX (RX from ahub)*/
1441         if (codec_i2s->playback_ref_count == 1)
1442                         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1443
1444         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL, codec_i2s->reg_ctrl);
1445
1446         while (!tegra30_ahub_tx_fifo_is_empty(codec_i2s->id) && dcnt--)
1447                 udelay(100);
1448
1449         dcnt = 10;
1450
1451         if (uses_voice_codec) {
1452                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1453                             bb_info->i2s_id);
1454                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1455                             codec_info->i2s_id);
1456         } else {
1457
1458                 /*Disable baseband DAM*/
1459                 tegra30_dam_enable(bb_i2s->dam_ifc, TEGRA30_DAM_DISABLE,
1460                                 TEGRA30_DAM_CHIN0_SRC);
1461                 tegra30_dam_free_channel(bb_i2s->dam_ifc,
1462                                 TEGRA30_DAM_CHIN0_SRC);
1463                 bb_i2s->dam_ch_refcount--;
1464                 if (!bb_i2s->dam_ch_refcount)
1465                         tegra30_dam_free_controller(bb_i2s->dam_ifc);
1466
1467                 /*Disable Codec DAM*/
1468                 tegra30_dam_enable(codec_i2s->dam_ifc,
1469                         TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN0_SRC);
1470                 tegra30_dam_free_channel(codec_i2s->dam_ifc,
1471                         TEGRA30_DAM_CHIN0_SRC);
1472                 codec_i2s->dam_ch_refcount--;
1473                 if (!codec_i2s->dam_ch_refcount)
1474                         tegra30_dam_free_controller(codec_i2s->dam_ifc);
1475
1476                 /* Disconnect the ahub connections */
1477                 /* If this is the only user of i2s tx then break ahub
1478                 i2s rx connection */
1479                 if (codec_i2s->playback_ref_count == 1)
1480                         tegra30_ahub_unset_rx_cif_source(
1481                            TEGRA30_AHUB_RXCIF_I2S0_RX0 + codec_info->i2s_id);
1482
1483                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0
1484                                         + bb_info->i2s_id);
1485                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0
1486                                         + (codec_i2s->dam_ifc*2));
1487                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0
1488                                         + (bb_i2s->dam_ifc*2));
1489
1490                 tegra30_dam_disable_clock(codec_i2s->dam_ifc);
1491                 tegra30_dam_disable_clock(bb_i2s->dam_ifc);
1492         }
1493
1494         /* Decrement the codec and bb i2s playback ref count */
1495         codec_i2s->playback_ref_count--;
1496         bb_i2s->playback_ref_count--;
1497         codec_i2s->capture_ref_count--;
1498         bb_i2s->capture_ref_count--;
1499
1500         /* Soft reset */
1501         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
1502                 codec_i2s->reg_ctrl | TEGRA30_I2S_CTRL_SOFT_RESET);
1503         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL,
1504                 bb_i2s->reg_ctrl | TEGRA30_I2S_CTRL_SOFT_RESET);
1505
1506         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1507         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1508         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_SOFT_RESET;
1509         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_SOFT_RESET;
1510
1511         while ((tegra30_i2s_read(codec_i2s, TEGRA30_I2S_CTRL) &
1512                         TEGRA30_I2S_CTRL_SOFT_RESET)  && dcnt--)
1513                 udelay(100);
1514         dcnt = 10;
1515         while ((tegra30_i2s_read(bb_i2s, TEGRA30_I2S_CTRL) &
1516                         TEGRA30_I2S_CTRL_SOFT_RESET)  && dcnt--)
1517                 udelay(100);
1518
1519         return 0;
1520 }
1521
1522 static int tegra30_i2s_platform_probe(struct platform_device *pdev)
1523 {
1524         struct tegra30_i2s *i2s;
1525         u32 cif_ids[2];
1526         struct resource *mem, *memregion;
1527         void __iomem *regs;
1528         int ret;
1529
1530         /* This needs to be updated for DT */
1531         return -ENODEV;
1532
1533         i2s = &i2scont[pdev->id];
1534         dev_set_drvdata(&pdev->dev, i2s);
1535         i2s->id = pdev->id;
1536
1537         ret = of_property_read_u32_array(pdev->dev.of_node,
1538                                          "nvidia,ahub-cif-ids", cif_ids,
1539                                          ARRAY_SIZE(cif_ids));
1540         if (ret < 0)
1541                 goto err;
1542
1543         i2s->playback_i2s_cif = cif_ids[0];
1544         i2s->capture_i2s_cif = cif_ids[1];
1545
1546         i2s->clk_i2s = clk_get(&pdev->dev, "i2s");
1547         if (IS_ERR(i2s->clk_i2s)) {
1548                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
1549                 ret = PTR_ERR(i2s->clk_i2s);
1550                 goto err;
1551         }
1552         i2s->clk_i2s_sync = clk_get(&pdev->dev, "ext_audio_sync");
1553         if (IS_ERR(i2s->clk_i2s_sync)) {
1554                 dev_err(&pdev->dev, "Can't retrieve i2s_sync clock\n");
1555                 ret = PTR_ERR(i2s->clk_i2s_sync);
1556                 goto err_i2s_clk_put;
1557         }
1558
1559         i2s->clk_audio_2x = clk_get(&pdev->dev, "audio_sync_2x");
1560         if (IS_ERR(i2s->clk_audio_2x)) {
1561                 dev_err(&pdev->dev, "Can't retrieve audio 2x clock\n");
1562                 ret = PTR_ERR(i2s->clk_audio_2x);
1563                 goto err_i2s_sync_clk_put;
1564         }
1565
1566         i2s->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0");
1567         if (IS_ERR(i2s->clk_pll_a_out0)) {
1568                 dev_err(&pdev->dev, "Can't retrieve pll_a_out0 clock\n");
1569                 ret = PTR_ERR(i2s->clk_pll_a_out0);
1570                 goto err_audio_2x_clk_put;
1571         }
1572
1573         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1574         if (!mem) {
1575                 dev_err(&pdev->dev, "No memory resource\n");
1576                 ret = -ENODEV;
1577                 goto err_pll_a_out0_clk_put;
1578         }
1579
1580         memregion = devm_request_mem_region(&pdev->dev, mem->start,
1581                                             resource_size(mem), DRV_NAME);
1582         if (!memregion) {
1583                 dev_err(&pdev->dev, "Memory region already claimed\n");
1584                 ret = -EBUSY;
1585                 goto err_pll_a_out0_clk_put;
1586         }
1587
1588         regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1589         if (!regs) {
1590                 dev_err(&pdev->dev, "ioremap failed\n");
1591                 ret = -ENOMEM;
1592                 goto err_pll_a_out0_clk_put;
1593         }
1594
1595         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1596                                             &tegra30_i2s_regmap_config);
1597         if (IS_ERR(i2s->regmap)) {
1598                 dev_err(&pdev->dev, "regmap init failed\n");
1599                 ret = PTR_ERR(i2s->regmap);
1600                 goto err_pll_a_out0_clk_put;
1601         }
1602         regcache_cache_only(i2s->regmap, true);
1603
1604         pm_runtime_enable(&pdev->dev);
1605         if (!pm_runtime_enabled(&pdev->dev)) {
1606                 ret = tegra30_i2s_runtime_resume(&pdev->dev);
1607                 if (ret)
1608                         goto err_pm_disable;
1609         }
1610
1611         ret = snd_soc_register_dai(&pdev->dev, NULL);
1612         if (ret) {
1613                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
1614                 ret = -ENOMEM;
1615                 goto err_suspend;
1616         }
1617
1618         ret = tegra_pcm_platform_register(&pdev->dev);
1619         if (ret) {
1620                 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
1621                 goto err_unregister_dai;
1622         }
1623
1624         return 0;
1625
1626 err_unregister_dai:
1627         snd_soc_unregister_dai(&pdev->dev);
1628 err_suspend:
1629         if (!pm_runtime_status_suspended(&pdev->dev))
1630                 tegra30_i2s_runtime_suspend(&pdev->dev);
1631 err_pm_disable:
1632         pm_runtime_disable(&pdev->dev);
1633 err_pll_a_out0_clk_put:
1634         clk_put(i2s->clk_pll_a_out0);
1635 err_audio_2x_clk_put:
1636         clk_put(i2s->clk_audio_2x);
1637 err_i2s_sync_clk_put:
1638         clk_put(i2s->clk_i2s_sync);
1639 err_i2s_clk_put:
1640         clk_put(i2s->clk_i2s);
1641 err:
1642         return ret;
1643 }
1644
1645 static int tegra30_i2s_platform_remove(struct platform_device *pdev)
1646 {
1647         struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
1648
1649         pm_runtime_disable(&pdev->dev);
1650         if (!pm_runtime_status_suspended(&pdev->dev))
1651                 tegra30_i2s_runtime_suspend(&pdev->dev);
1652
1653         tegra_pcm_platform_unregister(&pdev->dev);
1654         snd_soc_unregister_dai(&pdev->dev);
1655
1656         clk_put(i2s->clk_pll_a_out0);
1657         clk_put(i2s->clk_audio_2x);
1658         clk_put(i2s->clk_i2s_sync);
1659         clk_put(i2s->clk_i2s);
1660
1661         return 0;
1662 }
1663
1664 static const struct of_device_id tegra30_i2s_of_match[] = {
1665         { .compatible = "nvidia,tegra30-i2s", },
1666         {},
1667 };
1668
1669 static const struct dev_pm_ops tegra30_i2s_pm_ops = {
1670         SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
1671                            tegra30_i2s_runtime_resume, NULL)
1672 };
1673
1674 static struct platform_driver tegra30_i2s_driver = {
1675         .driver = {
1676                 .name = DRV_NAME,
1677                 .owner = THIS_MODULE,
1678                 .of_match_table = tegra30_i2s_of_match,
1679                 .pm = &tegra30_i2s_pm_ops,
1680         },
1681         .probe = tegra30_i2s_platform_probe,
1682         .remove = tegra30_i2s_platform_remove,
1683 };
1684 module_platform_driver(tegra30_i2s_driver);
1685
1686 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
1687 MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
1688 MODULE_LICENSE("GPL");
1689 MODULE_ALIAS("platform:" DRV_NAME);
1690 MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);