asoc: tegra: Add support for K3.10 audio
[linux-3.10.git] / sound / soc / tegra / tegra30_dam.h
1 /*
2  * tegra30_dam.h - Tegra 30 DAM driver.
3  *
4  * Author: Nikesh Oswal <noswal@nvidia.com>
5  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but
12  * WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19  * 02110-1301 USA
20  *
21  */
22
23 #ifndef __TEGRA30_DAM_H
24 #define __TEGRA30_DAM_H
25
26 /* Register offsets from TEGRA30_DAM*_BASE */
27 #define TEGRA30_DAM_CTRL                                0
28 #define TEGRA30_DAM_CLIP                                4
29 #define TEGRA30_DAM_CLIP_THRESHOLD                      8
30 #define TEGRA30_DAM_AUDIOCIF_OUT_CTRL                   0x0C
31 #define TEGRA30_DAM_CH0_CTRL                            0x10
32 #define TEGRA30_DAM_CH0_CONV                            0x14
33 #define TEGRA30_DAM_AUDIOCIF_CH0_CTRL                   0x1C
34 #define TEGRA30_DAM_CH1_CTRL                            0x20
35 #define TEGRA30_DAM_CH1_CONV                            0x24
36 #define TEGRA30_DAM_AUDIOCIF_CH1_CTRL                   0x2C
37 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
38 #define TEGRA30_DAM_CH0_BIQUAD_FIXED_COEF_0             0xf0
39 #define TEGRA30_DAM_FARROW_PARAM_0                      0xf4
40 #define TEGRA30_DAM_AUDIORAMCTL_DAM_CTRL_0              0xf8
41 #define TEGRA30_DAM_AUDIORAMCTL_DAM_DATA_0              0xfc
42 #define TEGRA30_DAM_CTRL_REGINDEX                       (TEGRA30_DAM_AUDIORAMCTL_DAM_DATA_0 >> 2)
43 #else
44 #define TEGRA30_DAM_CTRL_REGINDEX                       (TEGRA30_DAM_AUDIOCIF_CH1_CTRL >> 2)
45 #endif
46 #define TEGRA30_DAM_CTRL_RSVD_6                         6
47 #define TEGRA30_DAM_CTRL_RSVD_10                        10
48
49 #define TEGRA30_NR_DAM_IFC                              3
50
51 #define TEGRA30_DAM_NUM_INPUT_CHANNELS                  2
52
53 /* Fields in TEGRA30_DAM_CTRL */
54 #define TEGRA30_DAM_CTRL_SOFT_RESET_ENABLE              (1 << 31)
55 #define TEGRA30_DAM_CTRL_FSOUT_SHIFT                    4
56 #define TEGRA30_DAM_CTRL_FSOUT_MASK                     (0xf << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
57 #define TEGRA30_DAM_FS_8KHZ                             0
58 #define TEGRA30_DAM_FS_16KHZ                            1
59 #define TEGRA30_DAM_FS_44KHZ                            2
60 #define TEGRA30_DAM_FS_48KHZ                            3
61 #define TEGRA30_DAM_CTRL_FSOUT_FS8                      (TEGRA30_DAM_FS_8KHZ << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
62 #define TEGRA30_DAM_CTRL_FSOUT_FS16                     (TEGRA30_DAM_FS_16KHZ << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
63 #define TEGRA30_DAM_CTRL_FSOUT_FS44                     (TEGRA30_DAM_FS_44KHZ << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
64 #define TEGRA30_DAM_CTRL_FSOUT_FS48                     (TEGRA30_DAM_FS_48KHZ << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
65 #define TEGRA30_DAM_CTRL_CG_EN                          (1 << 1)
66 #define TEGRA30_DAM_CTRL_DAM_EN                         (1 << 0)
67 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
68 #define TEGRA30_DAM_CTRL_STEREO_MIXING_ENABLE   (1 << 3)
69 #endif
70
71
72 /* Fields in TEGRA30_DAM_CLIP */
73 #define TEGRA30_DAM_CLIP_COUNTER_ENABLE                 (1 << 31)
74 #define TEGRA30_DAM_CLIP_COUNT_MASK                     0x7fffffff
75
76
77 /* Fields in TEGRA30_DAM_CH0_CTRL */
78 #define TEGRA30_STEP_RESET                              1
79 #define TEGRA30_DAM_DATA_SYNC                           1
80 #define TEGRA30_DAM_DATA_SYNC_SHIFT                     4
81 #define TEGRA30_DAM_CH0_CTRL_FSIN_SHIFT                 8
82 #define TEGRA30_DAM_CH0_CTRL_STEP_SHIFT                 16
83 #define TEGRA30_DAM_CH0_CTRL_STEP_MASK                  (0xffff << 16)
84 #define TEGRA30_DAM_CH0_CTRL_STEP_RESET                 (TEGRA30_STEP_RESET << 16)
85 #define TEGRA30_DAM_CH0_CTRL_FSIN_MASK                  (0xf << 8)
86 #define TEGRA30_DAM_CH0_CTRL_FSIN_FS8                   (TEGRA30_DAM_FS_8KHZ << 8)
87 #define TEGRA30_DAM_CH0_CTRL_FSIN_FS16                  (TEGRA30_DAM_FS_16KHZ << 8)
88 #define TEGRA30_DAM_CH0_CTRL_FSIN_FS44                  (TEGRA30_DAM_FS_44KHZ << 8)
89 #define TEGRA30_DAM_CH0_CTRL_FSIN_FS48                  (TEGRA30_DAM_FS_48KHZ << 8)
90 #define TEGRA30_DAM_CH0_CTRL_DATA_SYNC_MASK             (0xf << TEGRA30_DAM_DATA_SYNC_SHIFT)
91 #define TEGRA30_DAM_CH0_CTRL_DATA_SYNC                  (TEGRA30_DAM_DATA_SYNC << TEGRA30_DAM_DATA_SYNC_SHIFT)
92 #define TEGRA30_DAM_CH0_CTRL_EN                         (1 << 0)
93 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
94 #define TEGRA30_DAM_CH0_CTRL_COEFF_RAM_ENABLE           (1 << 15)
95 #define TEGRA30_DAM_CH0_CTRL_FILT_STAGES_SHIFT  16
96 #endif
97
98
99 /* Fields in TEGRA30_DAM_CH0_CONV */
100 #define TEGRA30_DAM_GAIN                                1
101 #define TEGRA30_DAM_GAIN_SHIFT                          0
102 #define TEGRA30_DAM_CH0_CONV_GAIN                       (TEGRA30_DAM_GAIN << TEGRA30_DAM_GAIN_SHIFT)
103
104 /* Fields in TEGRA30_DAM_CH1_CTRL */
105 #define TEGRA30_DAM_CH1_CTRL_DATA_SYNC_MASK             (0xf << TEGRA30_DAM_DATA_SYNC_SHIFT)
106 #define TEGRA30_DAM_CH1_CTRL_DATA_SYNC                  (TEGRA30_DAM_DATA_SYNC << TEGRA30_DAM_DATA_SYNC_SHIFT)
107 #define TEGRA30_DAM_CH1_CTRL_EN                         (1 << 0)
108
109 /* Fields in TEGRA30_DAM_CH1_CONV */
110 #define TEGRA30_DAM_CH1_CONV_GAIN                       (TEGRA30_DAM_GAIN << TEGRA30_DAM_GAIN_SHIFT)
111
112 #define TEGRA30_AUDIO_CHANNELS_SHIFT                    24
113 #define TEGRA30_AUDIO_CHANNELS_MASK                     (7 << TEGRA30_AUDIO_CHANNELS_SHIFT)
114 #define TEGRA30_CLIENT_CHANNELS_SHIFT                   16
115 #define TEGRA30_CLIENT_CHANNELS_MASK                    (7 << TEGRA30_CLIENT_CHANNELS_SHIFT)
116 #define TEGRA30_AUDIO_BITS_SHIFT                        12
117 #define TEGRA30_AUDIO_BITS_MASK                         (7 << TEGRA30_AUDIO_BITS_SHIFT)
118 #define TEGRA30_CLIENT_BITS_SHIFT                       8
119 #define TEGRA30_CLIENT_BITS_MASK                        (7 << TEGRA30_CLIENT_BITS_SHIFT)
120 #define TEGRA30_CIF_DIRECTION_TX                        (0 << 2)
121 #define TEGRA30_CIF_DIRECTION_RX                        (1 << 2)
122 #define TEGRA30_CIF_BIT24                               5
123 #define TEGRA30_CIF_BIT16                               3
124 #define TEGRA30_CIF_CH1                                 0
125 #define TEGRA30_CIF_MONOCONV_COPY                       (1<<0)
126 #define TEGRA30_CIF_STEREOCONV_SHIFT            4
127 #define TEGRA30_CIF_STEREOCONV_MASK                     (3 << TEGRA30_CIF_STEREOCONV_SHIFT)
128 #define TEGRA30_CIF_STEREOCONV_CH0                      (0 << TEGRA30_CIF_STEREOCONV_SHIFT)
129 #define TEGRA30_CIF_STEREOCONV_CH1                      (1 << TEGRA30_CIF_STEREOCONV_SHIFT)
130 #define TEGRA30_CIF_STEREOCONV_AVG                      (2 << TEGRA30_CIF_STEREOCONV_SHIFT)
131
132 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
133 /* TEGRA30_DAM_CH0_BIQUAD_FIXED_COEF_0 */
134 #define TEGRA30_DAM_CH0_BIQUAD_FIXED_COEF_0_VAL         0x00800000
135
136 /* TEGRA30_DAM_FARROW_PARAM_0 */
137 #define TEGRA30_FARROW_PARAM_RESET      0xdee9a0a0
138 #define TEGRA30_FARROW_PARAM_1  0
139 #define TEGRA30_FARROW_PARAM_2  0xdee993a0
140 #define TEGRA30_FARROW_PARAM_3  0xcccda093
141 #endif
142
143 /*
144 * Audio Samplerates
145 */
146 #define TEGRA30_AUDIO_SAMPLERATE_8000                   8000
147 #define TEGRA30_AUDIO_SAMPLERATE_16000                  16000
148 #define TEGRA30_AUDIO_SAMPLERATE_44100                  44100
149 #define TEGRA30_AUDIO_SAMPLERATE_48000                  48000
150
151 #define TEGRA30_DAM_CHIN0_SRC                           0
152 #define TEGRA30_DAM_CHIN1                               1
153 #define TEGRA30_DAM_CHOUT                               2
154 #define TEGRA30_DAM_ENABLE                              1
155 #define TEGRA30_DAM_DISABLE                             0
156
157 struct tegra30_dam_context {
158         struct device *dev;
159         int                     outsamplerate;
160         bool                    ch_alloc[TEGRA30_DAM_NUM_INPUT_CHANNELS];
161         int                     ch_enable_refcnt[TEGRA30_DAM_NUM_INPUT_CHANNELS];
162         int                     ch_insamplerate[TEGRA30_DAM_NUM_INPUT_CHANNELS];
163         struct clk              *dam_clk;
164         bool                    in_use;
165         void __iomem            *damregs;
166         struct dentry           *debug;
167         struct regmap *regmap;
168 };
169
170 struct tegra30_dam_src_step_table {
171         int insample;
172         int outsample;
173         int stepreset;
174 };
175
176 void tegra30_dam_disable_clock(int ifc);
177 int tegra30_dam_enable_clock(int ifc);
178 int tegra30_dam_allocate_controller(void);
179 int tegra30_dam_allocate_channel(int ifc, int chid);
180 int tegra30_dam_free_channel(int ifc, int chid);
181 int tegra30_dam_free_controller(int ifc);
182 void tegra30_dam_set_samplerate(int ifc, int chtype, int samplerate);
183 int tegra30_dam_set_gain(int ifc, int chtype, int gain);
184 int tegra30_dam_set_acif(int ifc, int chtype, unsigned int audio_channels,
185         unsigned int audio_bits, unsigned int client_channels,
186         unsigned int client_bits);
187 void tegra30_dam_enable(int ifc, int on, int chtype);
188 int tegra30_dam_set_acif_stereo_conv(int ifc, int chtype, int conv);
189 void tegra30_dam_ch0_set_datasync(int ifc, int datasync);
190 void tegra30_dam_ch1_set_datasync(int ifc, int datasync);
191 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
192 void tegra30_dam_enable_stereo_mixing(int ifc);
193 #endif
194
195 #endif