asoc: tegra: Add support for K3.10 audio
[linux-3.10.git] / sound / soc / tegra / tegra30_ahub.h
1 /*
2  * tegra30_ahub.h - Definitions for Tegra30 AHUB driver
3  *
4  * Copyright (c) 2011-2013 NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #ifndef __TEGRA30_AHUB_H__
20 #define __TEGRA30_AHUB_H__
21
22 /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */
23
24 #if (defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
25 defined(CONFIG_ARCH_TEGRA_11x_SOC) || \
26 defined(CONFIG_ARCH_TEGRA_14x_SOC))
27 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT      28
28 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US    0xf
29 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK       (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT)
30
31 /* Channel count minus 1 */
32 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT      24
33
34 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
35 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US    0xf
36 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US   0xf
37 #else
38 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US    7
39 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US   7
40 #endif
41
42 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK       (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT)
43
44 /* Channel count minus 1 */
45 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT     16
46 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK      (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT)
47 #else /* CONFIG_ARCH_TEGRA_12x_SOC */
48 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT      24
49 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US    0x3f
50 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK       (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT)
51
52 /* Channel count minus 1 */
53 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT      20
54 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US    0xf
55 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK       (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT)
56
57 /* Channel count minus 1 */
58 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT     16
59 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US   0xf
60 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK      (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT)
61 #endif
62
63 #define TEGRA30_AUDIOCIF_BITS_4                         0
64 #define TEGRA30_AUDIOCIF_BITS_8                         1
65 #define TEGRA30_AUDIOCIF_BITS_12                        2
66 #define TEGRA30_AUDIOCIF_BITS_16                        3
67 #define TEGRA30_AUDIOCIF_BITS_20                        4
68 #define TEGRA30_AUDIOCIF_BITS_24                        5
69 #define TEGRA30_AUDIOCIF_BITS_28                        6
70 #define TEGRA30_AUDIOCIF_BITS_32                        7
71
72 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT          12
73 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK           (7                        << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
74 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4              (TEGRA30_AUDIOCIF_BITS_4  << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
75 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8              (TEGRA30_AUDIOCIF_BITS_8  << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
76 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12             (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
77 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16             (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
78 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20             (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
79 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24             (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
80 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28             (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
81 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32             (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
82
83 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT         8
84 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK          (7                        << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
85 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4             (TEGRA30_AUDIOCIF_BITS_4  << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
86 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8             (TEGRA30_AUDIOCIF_BITS_8  << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
87 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12            (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
88 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16            (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
89 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20            (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
90 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24            (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
91 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28            (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
92 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32            (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
93
94 #define TEGRA30_AUDIOCIF_EXPAND_ZERO                    0
95 #define TEGRA30_AUDIOCIF_EXPAND_ONE                     1
96 #define TEGRA30_AUDIOCIF_EXPAND_LFSR                    2
97
98 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT              6
99 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK               (3                            << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
100 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO               (TEGRA30_AUDIOCIF_EXPAND_ZERO << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
101 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE                (TEGRA30_AUDIOCIF_EXPAND_ONE  << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
102 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR               (TEGRA30_AUDIOCIF_EXPAND_LFSR << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
103
104 #define TEGRA30_AUDIOCIF_STEREO_CONV_CH0                0
105 #define TEGRA30_AUDIOCIF_STEREO_CONV_CH1                1
106 #define TEGRA30_AUDIOCIF_STEREO_CONV_AVG                2
107
108 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT         4
109 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK          (3                                << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
110 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0           (TEGRA30_AUDIOCIF_STEREO_CONV_CH0 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
111 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1           (TEGRA30_AUDIOCIF_STEREO_CONV_CH1 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
112 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG           (TEGRA30_AUDIOCIF_STEREO_CONV_AVG << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
113
114 #define TEGRA30_AUDIOCIF_CTRL_REPLICATE                 3
115 #define TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT           3
116 #define TEGRA30_AUDIOCIF_CTRL_REPLICATE_MASK            \
117                 (1 << TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT)
118 #define TEGRA30_AUDIOCIF_DIRECTION_TX                   0
119 #define TEGRA30_AUDIOCIF_DIRECTION_RX                   1
120
121 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT           2
122 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK            (1                             << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
123 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX              (TEGRA30_AUDIOCIF_DIRECTION_TX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
124 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX              (TEGRA30_AUDIOCIF_DIRECTION_RX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
125
126 #define TEGRA30_AUDIOCIF_TRUNCATE_ROUND                 0
127 #define TEGRA30_AUDIOCIF_TRUNCATE_CHOP                  1
128
129 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT            1
130 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK             (1                               << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
131 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND            (TEGRA30_AUDIOCIF_TRUNCATE_ROUND << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
132 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP             (TEGRA30_AUDIOCIF_TRUNCATE_CHOP  << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
133
134 #define TEGRA30_AUDIOCIF_MONO_CONV_ZERO                 0
135 #define TEGRA30_AUDIOCIF_MONO_CONV_COPY                 1
136
137 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT           0
138 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK            (1                               << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
139 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO            (TEGRA30_AUDIOCIF_MONO_CONV_ZERO << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
140 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY            (TEGRA30_AUDIOCIF_MONO_CONV_COPY << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
141
142 /* Registers within TEGRA30_AUDIO_CLUSTER_BASE */
143
144 /* TEGRA30_AHUB_CHANNEL_CTRL */
145
146 #define TEGRA30_AHUB_CHANNEL_CTRL                       0x0
147 #define TEGRA30_AHUB_CHANNEL_CTRL_STRIDE                0x20
148 #define TEGRA30_AHUB_CHANNEL_CTRL_COUNT                 4
149 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_EN                 (1 << 31)
150 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_EN                 (1 << 30)
151 #define TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK              (1 << 29)
152
153 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT    16
154 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US  0xff
155 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK     (TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT)
156
157 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT    8
158 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US  0xff
159 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK     (TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT)
160
161 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN            (1 << 6)
162
163 #define TEGRA30_PACK_8_4                                2
164 #define TEGRA30_PACK_16                                 3
165
166 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT         4
167 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US       3
168 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK          (TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
169 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4           (TEGRA30_PACK_8_4                          << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
170 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16            (TEGRA30_PACK_16                           << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
171
172 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN            (1 << 2)
173
174 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT         0
175 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US       3
176 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK          (TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
177 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4           (TEGRA30_PACK_8_4                          << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
178 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16            (TEGRA30_PACK_16                           << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
179
180 /* TEGRA30_AHUB_CHANNEL_CLEAR */
181
182 #define TEGRA30_AHUB_CHANNEL_CLEAR                      0x4
183 #define TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE               0x20
184 #define TEGRA30_AHUB_CHANNEL_CLEAR_COUNT                4
185 #define TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET        (1 << 31)
186 #define TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET        (1 << 30)
187
188 /* TEGRA30_AHUB_CHANNEL_STATUS */
189
190 #define TEGRA30_AHUB_CHANNEL_STATUS                     0x8
191 #define TEGRA30_AHUB_CHANNEL_STATUS_STRIDE              0x20
192 #define TEGRA30_AHUB_CHANNEL_STATUS_COUNT               4
193 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT       24
194 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US     0xff
195 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK        (TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT)
196 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT       16
197 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US     0xff
198 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK        (TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT)
199 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG             (1 << 1)
200 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG             (1 << 0)
201
202 /* TEGRA30_AHUB_CHANNEL_TXFIFO */
203
204 #define TEGRA30_AHUB_CHANNEL_TXFIFO                     0xc
205 #define TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE              0x20
206 #define TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT               4
207
208 /* TEGRA30_AHUB_CHANNEL_RXFIFO */
209
210 #define TEGRA30_AHUB_CHANNEL_RXFIFO                     0x10
211 #define TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE              0x20
212 #define TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT               4
213
214 /* TEGRA30_AHUB_CIF_TX_CTRL */
215
216 #define TEGRA30_AHUB_CIF_TX_CTRL                        0x14
217 #define TEGRA30_AHUB_CIF_TX_CTRL_STRIDE                 0x20
218 #define TEGRA30_AHUB_CIF_TX_CTRL_COUNT                  4
219 /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */
220
221 /* TEGRA30_AHUB_CIF_RX_CTRL */
222
223 #define TEGRA30_AHUB_CIF_RX_CTRL                        0x18
224 #define TEGRA30_AHUB_CIF_RX_CTRL_STRIDE                 0x20
225 #define TEGRA30_AHUB_CIF_RX_CTRL_COUNT                  4
226 /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */
227
228 /* TEGRA30_AHUB_CONFIG_LINK_CTRL */
229
230 #define TEGRA30_AHUB_CONFIG_LINK_CTRL                                   0x80
231 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT        28
232 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US      0xf
233 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK         (TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT)
234 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT                 16
235 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US               0xfff
236 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK                  (TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT)
237 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT                    5
238 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US                  0xfff
239 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK                     (TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT)
240 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN                             (1 << 2)
241 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR                (1 << 1)
242 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET                        (1 << 0)
243
244 /* TEGRA30_AHUB_MISC_CTRL */
245
246 #define TEGRA30_AHUB_MISC_CTRL                          0x84
247 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE             (1 << 31)
248 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN              (1 << 9)
249 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT      0
250 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK       (0x1f << TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT)
251
252 /* TEGRA30_AHUB_APBDMA_LIVE_STATUS */
253
254 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS                         0x88
255 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL    (1 << 31)
256 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL    (1 << 30)
257 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL    (1 << 29)
258 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL    (1 << 28)
259 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL    (1 << 27)
260 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL    (1 << 26)
261 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL    (1 << 25)
262 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL    (1 << 24)
263 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY   (1 << 23)
264 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY   (1 << 22)
265 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY   (1 << 21)
266 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY   (1 << 20)
267 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY   (1 << 19)
268 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY   (1 << 18)
269 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY   (1 << 17)
270 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY   (1 << 16)
271 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL    (1 << 15)
272 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL    (1 << 14)
273 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL    (1 << 13)
274 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL    (1 << 12)
275 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL    (1 << 11)
276 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL    (1 << 10)
277 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL    (1 << 9)
278 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL    (1 << 8)
279 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY   (1 << 7)
280 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY   (1 << 6)
281 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY   (1 << 5)
282 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY   (1 << 4)
283 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY   (1 << 3)
284 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY   (1 << 2)
285 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY   (1 << 1)
286 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY   (1 << 0)
287
288 /* TEGRA30_AHUB_I2S_LIVE_STATUS */
289
290 #define TEGRA30_AHUB_I2S_LIVE_STATUS                            0x8c
291 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL          (1 << 29)
292 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL          (1 << 28)
293 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL          (1 << 27)
294 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL          (1 << 26)
295 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL          (1 << 25)
296 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL          (1 << 24)
297 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL          (1 << 23)
298 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL          (1 << 22)
299 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL          (1 << 21)
300 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL          (1 << 20)
301 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED       (1 << 19)
302 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED       (1 << 18)
303 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED       (1 << 17)
304 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED       (1 << 16)
305 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED       (1 << 15)
306 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED       (1 << 14)
307 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED       (1 << 13)
308 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED       (1 << 12)
309 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED       (1 << 11)
310 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED       (1 << 10)
311 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY         (1 << 9)
312 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY         (1 << 8)
313 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY         (1 << 7)
314 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY         (1 << 6)
315 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY         (1 << 5)
316 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY         (1 << 4)
317 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY         (1 << 3)
318 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY         (1 << 2)
319 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY         (1 << 1)
320 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY         (1 << 0)
321
322 /* TEGRA30_AHUB_DAM0_LIVE_STATUS */
323
324 #define TEGRA30_AHUB_DAM_LIVE_STATUS                            0x90
325 #define TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE                     0x8
326 #define TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT                      3
327 #define TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED                 (1 << 26)
328 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED                (1 << 25)
329 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED                (1 << 24)
330 #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL                (1 << 15)
331 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL               (1 << 9)
332 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL               (1 << 8)
333 #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY               (1 << 7)
334 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY              (1 << 1)
335 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY              (1 << 0)
336
337 /* TEGRA30_AHUB_SPDIF_LIVE_STATUS */
338
339 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS                          0xa8
340 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED          (1 << 11)
341 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED          (1 << 10)
342 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED          (1 << 9)
343 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED          (1 << 8)
344 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL         (1 << 7)
345 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL         (1 << 6)
346 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL         (1 << 5)
347 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL         (1 << 4)
348 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY        (1 << 3)
349 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY        (1 << 2)
350 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY        (1 << 1)
351 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY        (1 << 0)
352
353 /* TEGRA30_AHUB_I2S_INT_MASK */
354
355 #define TEGRA30_AHUB_I2S_INT_MASK                               0xb0
356
357 /* TEGRA30_AHUB_DAM_INT_MASK */
358
359 #define TEGRA30_AHUB_DAM_INT_MASK                               0xb4
360
361 /* TEGRA30_AHUB_SPDIF_INT_MASK */
362
363 #define TEGRA30_AHUB_SPDIF_INT_MASK                             0xbc
364
365 /* TEGRA30_AHUB_APBIF_INT_MASK */
366
367 #define TEGRA30_AHUB_APBIF_INT_MASK                             0xc0
368
369 /* TEGRA30_AHUB_I2S_INT_STATUS */
370
371 #define TEGRA30_AHUB_I2S_INT_STATUS                             0xc8
372
373 /* TEGRA30_AHUB_DAM_INT_STATUS */
374
375 #define TEGRA30_AHUB_DAM_INT_STATUS                             0xcc
376
377 /* TEGRA30_AHUB_SPDIF_INT_STATUS */
378
379 #define TEGRA30_AHUB_SPDIF_INT_STATUS                           0xd4
380
381 /* TEGRA30_AHUB_APBIF_INT_STATUS */
382
383 #define TEGRA30_AHUB_APBIF_INT_STATUS                           0xd8
384
385 /* TEGRA30_AHUB_I2S_INT_SOURCE */
386
387 #define TEGRA30_AHUB_I2S_INT_SOURCE                             0xe0
388
389 /* TEGRA30_AHUB_DAM_INT_SOURCE */
390
391 #define TEGRA30_AHUB_DAM_INT_SOURCE                             0xe4
392
393 /* TEGRA30_AHUB_SPDIF_INT_SOURCE */
394
395 #define TEGRA30_AHUB_SPDIF_INT_SOURCE                           0xec
396
397 /* TEGRA30_AHUB_APBIF_INT_SOURCE */
398
399 #define TEGRA30_AHUB_APBIF_INT_SOURCE                           0xf0
400
401 /* TEGRA30_AHUB_I2S_INT_SET */
402
403 #define TEGRA30_AHUB_I2S_INT_SET                                0xf8
404
405 /* TEGRA30_AHUB_DAM_INT_SET */
406
407 #define TEGRA30_AHUB_DAM_INT_SET                                0xfc
408
409 /* TEGRA30_AHUB_SPDIF_INT_SET */
410
411 #define TEGRA30_AHUB_SPDIF_INT_SET                              0x100
412
413 /* TEGRA30_AHUB_APBIF_INT_SET */
414
415 #define TEGRA30_AHUB_APBIF_INT_SET                              0x104
416
417 /* Registers within TEGRA30_AHUB_BASE */
418
419 #define TEGRA30_AHUB_AUDIO_RX                                   0x0
420 #define TEGRA30_AHUB_AUDIO_RX_STRIDE                            0x4
421
422 /* This register repeats once for each entry in enum tegra30_ahub_rxcif */
423 /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */
424
425 /* apbif register count */
426 #define TEGRA30_APBIF_CACHE_REG_COUNT_PER_CHANNEL               ((TEGRA30_AHUB_CIF_RX_CTRL>>2) + 1)
427 #define TEGRA30_APBIF_CACHE_REG_COUNT                           ((TEGRA30_APBIF_CACHE_REG_COUNT_PER_CHANNEL + 1) * TEGRA30_AHUB_CHANNEL_CTRL_COUNT)
428
429 /* cache index to be skipped */
430 #define TEGRA30_APBIF_CACHE_REG_INDEX_RSVD                      TEGRA30_APBIF_CACHE_REG_COUNT_PER_CHANNEL
431 #define TEGRA30_APBIF_CACHE_REG_INDEX_RSVD_STRIDE               (TEGRA30_APBIF_CACHE_REG_COUNT_PER_CHANNEL + 1)
432
433 /*
434  * Terminology:
435  * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs,
436  *       I2S controllers, SPDIF controllers, and DAMs.
437  * XBAR: The core cross-bar component of the AHUB.
438  * CIF:  Client Interface; the HW module connecting an audio device to the
439  *       XBAR.
440  * DAM:  Digital Audio Mixer: A HW module that mixes multiple audio streams,
441  *       possibly including sample-rate conversion.
442  *
443  * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio
444  * transmitted by a particular TX CIF.
445  *
446  * This driver is currently very simplistic; many HW features are not
447  * exposed; DAMs are not supported, only 16-bit stereo audio is supported,
448  * etc.
449  */
450
451 enum tegra30_ahub_txcif {
452         TEGRA30_AHUB_TXCIF_APBIF_TX0,
453         TEGRA30_AHUB_TXCIF_APBIF_TX1,
454         TEGRA30_AHUB_TXCIF_APBIF_TX2,
455         TEGRA30_AHUB_TXCIF_APBIF_TX3,
456         TEGRA30_AHUB_TXCIF_I2S0_TX0,
457         TEGRA30_AHUB_TXCIF_I2S1_TX0,
458         TEGRA30_AHUB_TXCIF_I2S2_TX0,
459         TEGRA30_AHUB_TXCIF_I2S3_TX0,
460         TEGRA30_AHUB_TXCIF_I2S4_TX0,
461         TEGRA30_AHUB_TXCIF_DAM0_TX0,
462         TEGRA30_AHUB_TXCIF_DAM1_TX0,
463         TEGRA30_AHUB_TXCIF_DAM2_TX0,
464         TEGRA30_AHUB_TXCIF_SPDIF_TX0,
465         TEGRA30_AHUB_TXCIF_SPDIF_TX1,
466 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
467         TEGRA30_AHUB_TXCIF_APBIF_TX4,
468         TEGRA30_AHUB_TXCIF_APBIF_TX5,
469         TEGRA30_AHUB_TXCIF_APBIF_TX6,
470         TEGRA30_AHUB_TXCIF_APBIF_TX7,
471         TEGRA30_AHUB_TXCIF_APBIF_TX8,
472         TEGRA30_AHUB_TXCIF_APBIF_TX9,
473         TEGRA30_AHUB_TXCIF_AMX0_TX0,
474         TEGRA30_AHUB_TXCIF_ADX0_TX0,
475         TEGRA30_AHUB_TXCIF_ADX0_TX1,
476         TEGRA30_AHUB_TXCIF_ADX0_TX2,
477         TEGRA30_AHUB_TXCIF_ADX0_TX3,
478 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
479         TEGRA30_AHUB_TXCIF_DMIC0_TX0,
480         TEGRA30_AHUB_TXCIF_DMIC1_TX0,
481         TEGRA30_AHUB_TXCIF_RSVD_TX0,
482         TEGRA30_AHUB_TXCIF_RSVD_TX1,
483         TEGRA30_AHUB_TXCIF_BBC1_TX0,
484         TEGRA30_AHUB_TXCIF_BBC1_TX1,
485 #endif
486 #endif
487 };
488
489 enum tegra30_ahub_rxcif {
490         TEGRA30_AHUB_RXCIF_APBIF_RX0,
491         TEGRA30_AHUB_RXCIF_APBIF_RX1,
492         TEGRA30_AHUB_RXCIF_APBIF_RX2,
493         TEGRA30_AHUB_RXCIF_APBIF_RX3,
494         TEGRA30_AHUB_RXCIF_I2S0_RX0,
495         TEGRA30_AHUB_RXCIF_I2S1_RX0,
496         TEGRA30_AHUB_RXCIF_I2S2_RX0,
497         TEGRA30_AHUB_RXCIF_I2S3_RX0,
498         TEGRA30_AHUB_RXCIF_I2S4_RX0,
499         TEGRA30_AHUB_RXCIF_DAM0_RX0,
500         TEGRA30_AHUB_RXCIF_DAM0_RX1,
501         TEGRA30_AHUB_RXCIF_DAM1_RX0,
502         TEGRA30_AHUB_RXCIF_DAM1_RX1,
503         TEGRA30_AHUB_RXCIF_DAM2_RX0,
504         TEGRA30_AHUB_RXCIF_DAM2_RX1,
505         TEGRA30_AHUB_RXCIF_SPDIF_RX0,
506         TEGRA30_AHUB_RXCIF_SPDIF_RX1,
507 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
508         TEGRA30_AHUB_RXCIF_APBIF_RX4,
509         TEGRA30_AHUB_RXCIF_APBIF_RX5,
510         TEGRA30_AHUB_RXCIF_APBIF_RX6,
511         TEGRA30_AHUB_RXCIF_APBIF_RX7,
512         TEGRA30_AHUB_RXCIF_APBIF_RX8,
513         TEGRA30_AHUB_RXCIF_APBIF_RX9,
514         TEGRA30_AHUB_RXCIF_AMX0_RX0,
515         TEGRA30_AHUB_RXCIF_AMX0_RX1,
516         TEGRA30_AHUB_RXCIF_AMX0_RX2,
517         TEGRA30_AHUB_RXCIF_AMX0_RX3,
518         TEGRA30_AHUB_RXCIF_ADX0_RX0,
519 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
520         TEGRA30_AHUB_RXCIF_BBC1_RX0,
521         TEGRA30_AHUB_RXCIF_BBC1_RX1,
522 #endif
523 #endif
524         TEGRA30_AHUB_AUDIO_RX_COUNT,
525 };
526
527 extern void tegra30_ahub_enable_clocks(void);
528 extern void tegra30_ahub_disable_clocks(void);
529 extern void tegra30_ahub_clock_set_rate(int rate);
530
531 extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
532                                          unsigned long *fiforeg,
533                                          unsigned long *reqsel);
534 extern int tegra30_ahub_set_rx_cif_channels(enum tegra30_ahub_rxcif rxcif,
535                                             unsigned int audio_ch,
536                                             unsigned int client_ch);
537 extern int tegra30_ahub_set_rx_cif_stereo_conv(enum tegra30_ahub_rxcif rxcif);
538 extern int tegra30_ahub_set_rx_cif_bits(enum tegra30_ahub_rxcif rxcif,
539                                             unsigned int audio_bits,
540                                             unsigned int client_bits);
541 extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
542 extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
543 extern int tegra30_ahub_set_rx_fifo_pack_mode(enum tegra30_ahub_rxcif rxcif,
544                                                 unsigned int pack_mode);
545 extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif);
546
547 extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
548                                          unsigned long *fiforeg,
549                                          unsigned long *reqsel);
550 extern int tegra30_ahub_set_tx_cif_channels(enum tegra30_ahub_txcif txcif,
551                                             unsigned int audio_ch,
552                                             unsigned int client_ch);
553 extern int tegra30_ahub_set_tx_cif_bits(enum tegra30_ahub_txcif txcif,
554                                             unsigned int audio_bits,
555                                             unsigned int client_bits);
556 extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif);
557 extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif);
558 extern int tegra30_ahub_set_tx_fifo_pack_mode(enum tegra30_ahub_txcif txcif,
559                                                 unsigned int pack_mode);
560 extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif);
561
562 extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
563                                           enum tegra30_ahub_txcif txcif);
564 extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif);
565
566 extern int tegra30_ahub_rx_fifo_is_enabled(int i2s_id);
567 extern int tegra30_ahub_tx_fifo_is_enabled(int i2s_id);
568 extern int tegra30_ahub_rx_fifo_is_empty(int i2s_id);
569 extern int tegra30_ahub_tx_fifo_is_empty(int i2s_id);
570 extern int tegra30_ahub_dam_ch0_is_enabled(int dam_id);
571 extern int tegra30_ahub_dam_ch1_is_enabled(int dam_id);
572 extern int tegra30_ahub_dam_tx_is_enabled(int dam_id);
573 extern int tegra30_ahub_dam_ch0_is_empty(int dam_id);
574 extern int tegra30_ahub_dam_ch1_is_empty(int dam_id);
575 extern int tegra30_ahub_dam_tx_is_empty(int dam_id);
576
577
578 #ifdef CONFIG_PM
579 extern int tegra30_ahub_apbif_resume(void);
580 #endif
581
582 struct tegra30_ahub {
583         struct device *dev;
584         struct clk *clk_d_audio;
585         struct clk *clk_apbif;
586         int dma_sel;
587         resource_size_t apbif_addr;
588         struct regmap *regmap_apbif;
589         struct regmap *regmap_ahub;
590         DECLARE_BITMAP(rx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
591         DECLARE_BITMAP(tx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
592         struct dentry *debug;
593 };
594
595 #endif