ASoC: Fix WM8993 MCLK configuration for high frequency MCLKs
[linux-3.10.git] / sound / soc / codecs / wm8993.c
1 /*
2  * wm8993.c -- WM8993 ALSA SoC audio driver
3  *
4  * Copyright 2009 Wolfson Microelectronics plc
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/spi/spi.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/tlv.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <sound/wm8993.h>
28
29 #include "wm8993.h"
30 #include "wm_hubs.h"
31
32 static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = {
33         0x8993,     /* R0   - Software Reset */
34         0x0000,     /* R1   - Power Management (1) */
35         0x6000,     /* R2   - Power Management (2) */
36         0x0000,     /* R3   - Power Management (3) */
37         0x4050,     /* R4   - Audio Interface (1) */
38         0x4000,     /* R5   - Audio Interface (2) */
39         0x01C8,     /* R6   - Clocking 1 */
40         0x0000,     /* R7   - Clocking 2 */
41         0x0000,     /* R8   - Audio Interface (3) */
42         0x0040,     /* R9   - Audio Interface (4) */
43         0x0004,     /* R10  - DAC CTRL */
44         0x00C0,     /* R11  - Left DAC Digital Volume */
45         0x00C0,     /* R12  - Right DAC Digital Volume */
46         0x0000,     /* R13  - Digital Side Tone */
47         0x0300,     /* R14  - ADC CTRL */
48         0x00C0,     /* R15  - Left ADC Digital Volume */
49         0x00C0,     /* R16  - Right ADC Digital Volume */
50         0x0000,     /* R17 */
51         0x0000,     /* R18  - GPIO CTRL 1 */
52         0x0010,     /* R19  - GPIO1 */
53         0x0000,     /* R20  - IRQ_DEBOUNCE */
54         0x0000,     /* R21 */
55         0x8000,     /* R22  - GPIOCTRL 2 */
56         0x0800,     /* R23  - GPIO_POL */
57         0x008B,     /* R24  - Left Line Input 1&2 Volume */
58         0x008B,     /* R25  - Left Line Input 3&4 Volume */
59         0x008B,     /* R26  - Right Line Input 1&2 Volume */
60         0x008B,     /* R27  - Right Line Input 3&4 Volume */
61         0x006D,     /* R28  - Left Output Volume */
62         0x006D,     /* R29  - Right Output Volume */
63         0x0066,     /* R30  - Line Outputs Volume */
64         0x0020,     /* R31  - HPOUT2 Volume */
65         0x0079,     /* R32  - Left OPGA Volume */
66         0x0079,     /* R33  - Right OPGA Volume */
67         0x0003,     /* R34  - SPKMIXL Attenuation */
68         0x0003,     /* R35  - SPKMIXR Attenuation */
69         0x0011,     /* R36  - SPKOUT Mixers */
70         0x0100,     /* R37  - SPKOUT Boost */
71         0x0079,     /* R38  - Speaker Volume Left */
72         0x0079,     /* R39  - Speaker Volume Right */
73         0x0000,     /* R40  - Input Mixer2 */
74         0x0000,     /* R41  - Input Mixer3 */
75         0x0000,     /* R42  - Input Mixer4 */
76         0x0000,     /* R43  - Input Mixer5 */
77         0x0000,     /* R44  - Input Mixer6 */
78         0x0000,     /* R45  - Output Mixer1 */
79         0x0000,     /* R46  - Output Mixer2 */
80         0x0000,     /* R47  - Output Mixer3 */
81         0x0000,     /* R48  - Output Mixer4 */
82         0x0000,     /* R49  - Output Mixer5 */
83         0x0000,     /* R50  - Output Mixer6 */
84         0x0000,     /* R51  - HPOUT2 Mixer */
85         0x0000,     /* R52  - Line Mixer1 */
86         0x0000,     /* R53  - Line Mixer2 */
87         0x0000,     /* R54  - Speaker Mixer */
88         0x0000,     /* R55  - Additional Control */
89         0x0000,     /* R56  - AntiPOP1 */
90         0x0000,     /* R57  - AntiPOP2 */
91         0x0000,     /* R58  - MICBIAS */
92         0x0000,     /* R59 */
93         0x0000,     /* R60  - FLL Control 1 */
94         0x0000,     /* R61  - FLL Control 2 */
95         0x0000,     /* R62  - FLL Control 3 */
96         0x2EE0,     /* R63  - FLL Control 4 */
97         0x0002,     /* R64  - FLL Control 5 */
98         0x2287,     /* R65  - Clocking 3 */
99         0x025F,     /* R66  - Clocking 4 */
100         0x0000,     /* R67  - MW Slave Control */
101         0x0000,     /* R68 */
102         0x0002,     /* R69  - Bus Control 1 */
103         0x0000,     /* R70  - Write Sequencer 0 */
104         0x0000,     /* R71  - Write Sequencer 1 */
105         0x0000,     /* R72  - Write Sequencer 2 */
106         0x0000,     /* R73  - Write Sequencer 3 */
107         0x0000,     /* R74  - Write Sequencer 4 */
108         0x0000,     /* R75  - Write Sequencer 5 */
109         0x1F25,     /* R76  - Charge Pump 1 */
110         0x0000,     /* R77 */
111         0x0000,     /* R78 */
112         0x0000,     /* R79 */
113         0x0000,     /* R80 */
114         0x0000,     /* R81  - Class W 0 */
115         0x0000,     /* R82 */
116         0x0000,     /* R83 */
117         0x0000,     /* R84  - DC Servo 0 */
118         0x054A,     /* R85  - DC Servo 1 */
119         0x0000,     /* R86 */
120         0x0000,     /* R87  - DC Servo 3 */
121         0x0000,     /* R88  - DC Servo Readback 0 */
122         0x0000,     /* R89  - DC Servo Readback 1 */
123         0x0000,     /* R90  - DC Servo Readback 2 */
124         0x0000,     /* R91 */
125         0x0000,     /* R92 */
126         0x0000,     /* R93 */
127         0x0000,     /* R94 */
128         0x0000,     /* R95 */
129         0x0100,     /* R96  - Analogue HP 0 */
130         0x0000,     /* R97 */
131         0x0000,     /* R98  - EQ1 */
132         0x000C,     /* R99  - EQ2 */
133         0x000C,     /* R100 - EQ3 */
134         0x000C,     /* R101 - EQ4 */
135         0x000C,     /* R102 - EQ5 */
136         0x000C,     /* R103 - EQ6 */
137         0x0FCA,     /* R104 - EQ7 */
138         0x0400,     /* R105 - EQ8 */
139         0x00D8,     /* R106 - EQ9 */
140         0x1EB5,     /* R107 - EQ10 */
141         0xF145,     /* R108 - EQ11 */
142         0x0B75,     /* R109 - EQ12 */
143         0x01C5,     /* R110 - EQ13 */
144         0x1C58,     /* R111 - EQ14 */
145         0xF373,     /* R112 - EQ15 */
146         0x0A54,     /* R113 - EQ16 */
147         0x0558,     /* R114 - EQ17 */
148         0x168E,     /* R115 - EQ18 */
149         0xF829,     /* R116 - EQ19 */
150         0x07AD,     /* R117 - EQ20 */
151         0x1103,     /* R118 - EQ21 */
152         0x0564,     /* R119 - EQ22 */
153         0x0559,     /* R120 - EQ23 */
154         0x4000,     /* R121 - EQ24 */
155         0x0000,     /* R122 - Digital Pulls */
156         0x0F08,     /* R123 - DRC Control 1 */
157         0x0000,     /* R124 - DRC Control 2 */
158         0x0080,     /* R125 - DRC Control 3 */
159         0x0000,     /* R126 - DRC Control 4 */
160 };
161
162 static struct {
163         int ratio;
164         int clk_sys_rate;
165 } clk_sys_rates[] = {
166         { 64,   0 },
167         { 128,  1 },
168         { 192,  2 },
169         { 256,  3 },
170         { 384,  4 },
171         { 512,  5 },
172         { 768,  6 },
173         { 1024, 7 },
174         { 1408, 8 },
175         { 1536, 9 },
176 };
177
178 static struct {
179         int rate;
180         int sample_rate;
181 } sample_rates[] = {
182         { 8000,  0  },
183         { 11025, 1  },
184         { 12000, 1  },
185         { 16000, 2  },
186         { 22050, 3  },
187         { 24000, 3  },
188         { 32000, 4  },
189         { 44100, 5  },
190         { 48000, 5  },
191 };
192
193 static struct {
194         int div; /* *10 due to .5s */
195         int bclk_div;
196 } bclk_divs[] = {
197         { 10,  0  },
198         { 15,  1  },
199         { 20,  2  },
200         { 30,  3  },
201         { 40,  4  },
202         { 55,  5  },
203         { 60,  6  },
204         { 80,  7  },
205         { 110, 8  },
206         { 120, 9  },
207         { 160, 10 },
208         { 220, 11 },
209         { 240, 12 },
210         { 320, 13 },
211         { 440, 14 },
212         { 480, 15 },
213 };
214
215 struct wm8993_priv {
216         u16 reg_cache[WM8993_REGISTER_COUNT];
217         struct wm8993_platform_data pdata;
218         struct snd_soc_codec codec;
219         int master;
220         int sysclk_source;
221         unsigned int mclk_rate;
222         unsigned int sysclk_rate;
223         unsigned int fs;
224         unsigned int bclk;
225         int class_w_users;
226         unsigned int fll_fref;
227         unsigned int fll_fout;
228 };
229
230 static unsigned int wm8993_read_hw(struct snd_soc_codec *codec, u8 reg)
231 {
232         struct i2c_msg xfer[2];
233         u16 data;
234         int ret;
235         struct i2c_client *i2c = codec->control_data;
236
237         /* Write register */
238         xfer[0].addr = i2c->addr;
239         xfer[0].flags = 0;
240         xfer[0].len = 1;
241         xfer[0].buf = &reg;
242
243         /* Read data */
244         xfer[1].addr = i2c->addr;
245         xfer[1].flags = I2C_M_RD;
246         xfer[1].len = 2;
247         xfer[1].buf = (u8 *)&data;
248
249         ret = i2c_transfer(i2c->adapter, xfer, 2);
250         if (ret != 2) {
251                 dev_err(codec->dev, "Failed to read 0x%x: %d\n", reg, ret);
252                 return 0;
253         }
254
255         return (data >> 8) | ((data & 0xff) << 8);
256 }
257
258 static int wm8993_volatile(unsigned int reg)
259 {
260         switch (reg) {
261         case WM8993_SOFTWARE_RESET:
262         case WM8993_DC_SERVO_0:
263         case WM8993_DC_SERVO_READBACK_0:
264         case WM8993_DC_SERVO_READBACK_1:
265         case WM8993_DC_SERVO_READBACK_2:
266                 return 1;
267         default:
268                 return 0;
269         }
270 }
271
272 static unsigned int wm8993_read(struct snd_soc_codec *codec,
273                                 unsigned int reg)
274 {
275         u16 *reg_cache = codec->reg_cache;
276
277         BUG_ON(reg > WM8993_MAX_REGISTER);
278
279         if (wm8993_volatile(reg))
280                 return wm8993_read_hw(codec, reg);
281         else
282                 return reg_cache[reg];
283 }
284
285 static int wm8993_write(struct snd_soc_codec *codec, unsigned int reg,
286                         unsigned int value)
287 {
288         u16 *reg_cache = codec->reg_cache;
289         u8 data[3];
290         int ret;
291
292         BUG_ON(reg > WM8993_MAX_REGISTER);
293
294         /* data is
295          *   D15..D9 WM8993 register offset
296          *   D8...D0 register data
297          */
298         data[0] = reg;
299         data[1] = value >> 8;
300         data[2] = value & 0x00ff;
301
302         if (!wm8993_volatile(reg))
303                 reg_cache[reg] = value;
304
305         ret = codec->hw_write(codec->control_data, data, 3);
306
307         if (ret == 3)
308                 return 0;
309         if (ret < 0)
310                 return ret;
311         return -EIO;
312 }
313
314 struct _fll_div {
315         u16 fll_fratio;
316         u16 fll_outdiv;
317         u16 fll_clk_ref_div;
318         u16 n;
319         u16 k;
320 };
321
322 /* The size in bits of the FLL divide multiplied by 10
323  * to allow rounding later */
324 #define FIXED_FLL_SIZE ((1 << 16) * 10)
325
326 static struct {
327         unsigned int min;
328         unsigned int max;
329         u16 fll_fratio;
330         int ratio;
331 } fll_fratios[] = {
332         {       0,    64000, 4, 16 },
333         {   64000,   128000, 3,  8 },
334         {  128000,   256000, 2,  4 },
335         {  256000,  1000000, 1,  2 },
336         { 1000000, 13500000, 0,  1 },
337 };
338
339 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
340                        unsigned int Fout)
341 {
342         u64 Kpart;
343         unsigned int K, Ndiv, Nmod, target;
344         unsigned int div;
345         int i;
346
347         /* Fref must be <=13.5MHz */
348         div = 1;
349         fll_div->fll_clk_ref_div = 0;
350         while ((Fref / div) > 13500000) {
351                 div *= 2;
352                 fll_div->fll_clk_ref_div++;
353
354                 if (div > 8) {
355                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
356                                Fref);
357                         return -EINVAL;
358                 }
359         }
360
361         pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
362
363         /* Apply the division for our remaining calculations */
364         Fref /= div;
365
366         /* Fvco should be 90-100MHz; don't check the upper bound */
367         div = 0;
368         target = Fout * 2;
369         while (target < 90000000) {
370                 div++;
371                 target *= 2;
372                 if (div > 7) {
373                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
374                                Fout);
375                         return -EINVAL;
376                 }
377         }
378         fll_div->fll_outdiv = div;
379
380         pr_debug("Fvco=%dHz\n", target);
381
382         /* Find an appropraite FLL_FRATIO and factor it out of the target */
383         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
384                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
385                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
386                         target /= fll_fratios[i].ratio;
387                         break;
388                 }
389         }
390         if (i == ARRAY_SIZE(fll_fratios)) {
391                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
392                 return -EINVAL;
393         }
394
395         /* Now, calculate N.K */
396         Ndiv = target / Fref;
397
398         fll_div->n = Ndiv;
399         Nmod = target % Fref;
400         pr_debug("Nmod=%d\n", Nmod);
401
402         /* Calculate fractional part - scale up so we can round. */
403         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
404
405         do_div(Kpart, Fref);
406
407         K = Kpart & 0xFFFFFFFF;
408
409         if ((K % 10) >= 5)
410                 K += 5;
411
412         /* Move down to proper range now rounding is done */
413         fll_div->k = K / 10;
414
415         pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
416                  fll_div->n, fll_div->k,
417                  fll_div->fll_fratio, fll_div->fll_outdiv,
418                  fll_div->fll_clk_ref_div);
419
420         return 0;
421 }
422
423 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id,
424                           unsigned int Fref, unsigned int Fout)
425 {
426         struct snd_soc_codec *codec = dai->codec;
427         struct wm8993_priv *wm8993 = codec->private_data;
428         u16 reg1, reg4, reg5;
429         struct _fll_div fll_div;
430         int ret;
431
432         /* Any change? */
433         if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
434                 return 0;
435
436         /* Disable the FLL */
437         if (Fout == 0) {
438                 dev_dbg(codec->dev, "FLL disabled\n");
439                 wm8993->fll_fref = 0;
440                 wm8993->fll_fout = 0;
441
442                 reg1 = wm8993_read(codec, WM8993_FLL_CONTROL_1);
443                 reg1 &= ~WM8993_FLL_ENA;
444                 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1);
445
446                 return 0;
447         }
448
449         ret = fll_factors(&fll_div, Fref, Fout);
450         if (ret != 0)
451                 return ret;
452
453         reg5 = wm8993_read(codec, WM8993_FLL_CONTROL_5);
454         reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
455
456         switch (fll_id) {
457         case WM8993_FLL_MCLK:
458                 break;
459
460         case WM8993_FLL_LRCLK:
461                 reg5 |= 1;
462                 break;
463
464         case WM8993_FLL_BCLK:
465                 reg5 |= 2;
466                 break;
467
468         default:
469                 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
470                 return -EINVAL;
471         }
472
473         /* Any FLL configuration change requires that the FLL be
474          * disabled first. */
475         reg1 = wm8993_read(codec, WM8993_FLL_CONTROL_1);
476         reg1 &= ~WM8993_FLL_ENA;
477         wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1);
478
479         /* Apply the configuration */
480         if (fll_div.k)
481                 reg1 |= WM8993_FLL_FRAC_MASK;
482         else
483                 reg1 &= ~WM8993_FLL_FRAC_MASK;
484         wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1);
485
486         wm8993_write(codec, WM8993_FLL_CONTROL_2,
487                      (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
488                      (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
489         wm8993_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
490
491         reg4 = wm8993_read(codec, WM8993_FLL_CONTROL_4);
492         reg4 &= ~WM8993_FLL_N_MASK;
493         reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
494         wm8993_write(codec, WM8993_FLL_CONTROL_4, reg4);
495
496         reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
497         reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
498         wm8993_write(codec, WM8993_FLL_CONTROL_5, reg5);
499
500         /* Enable the FLL */
501         wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
502
503         dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
504
505         wm8993->fll_fref = Fref;
506         wm8993->fll_fout = Fout;
507
508         return 0;
509 }
510
511 static int configure_clock(struct snd_soc_codec *codec)
512 {
513         struct wm8993_priv *wm8993 = codec->private_data;
514         unsigned int reg;
515
516         /* This should be done on init() for bypass paths */
517         switch (wm8993->sysclk_source) {
518         case WM8993_SYSCLK_MCLK:
519                 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
520
521                 reg = wm8993_read(codec, WM8993_CLOCKING_2);
522                 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
523                 if (wm8993->mclk_rate > 13500000) {
524                         reg |= WM8993_MCLK_DIV;
525                         wm8993->sysclk_rate = wm8993->mclk_rate / 2;
526                 } else {
527                         reg &= ~WM8993_MCLK_DIV;
528                         wm8993->sysclk_rate = wm8993->mclk_rate;
529                 }
530                 wm8993_write(codec, WM8993_CLOCKING_2, reg);
531                 break;
532
533         case WM8993_SYSCLK_FLL:
534                 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
535                         wm8993->fll_fout);
536
537                 reg = wm8993_read(codec, WM8993_CLOCKING_2);
538                 reg |= WM8993_SYSCLK_SRC;
539                 if (wm8993->fll_fout > 13500000) {
540                         reg |= WM8993_MCLK_DIV;
541                         wm8993->sysclk_rate = wm8993->fll_fout / 2;
542                 } else {
543                         reg &= ~WM8993_MCLK_DIV;
544                         wm8993->sysclk_rate = wm8993->fll_fout;
545                 }
546                 wm8993_write(codec, WM8993_CLOCKING_2, reg);
547                 break;
548
549         default:
550                 dev_err(codec->dev, "System clock not configured\n");
551                 return -EINVAL;
552         }
553
554         dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
555
556         return 0;
557 }
558
559 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
560 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
561 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
562 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
563 static const unsigned int drc_max_tlv[] = {
564         TLV_DB_RANGE_HEAD(4),
565         0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
566         3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
567 };
568 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
569 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
570 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
571 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
572 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
573
574 static const char *dac_deemph_text[] = {
575         "None",
576         "32kHz",
577         "44.1kHz",
578         "48kHz",
579 };
580
581 static const struct soc_enum dac_deemph =
582         SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text);
583
584 static const char *adc_hpf_text[] = {
585         "Hi-Fi",
586         "Voice 1",
587         "Voice 2",
588         "Voice 3",
589 };
590
591 static const struct soc_enum adc_hpf =
592         SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text);
593
594 static const char *drc_path_text[] = {
595         "ADC",
596         "DAC"
597 };
598
599 static const struct soc_enum drc_path =
600         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text);
601
602 static const char *drc_r0_text[] = {
603         "1",
604         "1/2",
605         "1/4",
606         "1/8",
607         "1/16",
608         "0",
609 };
610
611 static const struct soc_enum drc_r0 =
612         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text);
613
614 static const char *drc_r1_text[] = {
615         "1",
616         "1/2",
617         "1/4",
618         "1/8",
619         "0",
620 };
621
622 static const struct soc_enum drc_r1 =
623         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text);
624
625 static const char *drc_attack_text[] = {
626         "Reserved",
627         "181us",
628         "363us",
629         "726us",
630         "1.45ms",
631         "2.9ms",
632         "5.8ms",
633         "11.6ms",
634         "23.2ms",
635         "46.4ms",
636         "92.8ms",
637         "185.6ms",
638 };
639
640 static const struct soc_enum drc_attack =
641         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text);
642
643 static const char *drc_decay_text[] = {
644         "186ms",
645         "372ms",
646         "743ms",
647         "1.49s",
648         "2.97ms",
649         "5.94ms",
650         "11.89ms",
651         "23.78ms",
652         "47.56ms",
653 };
654
655 static const struct soc_enum drc_decay =
656         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text);
657
658 static const char *drc_ff_text[] = {
659         "5 samples",
660         "9 samples",
661 };
662
663 static const struct soc_enum drc_ff =
664         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text);
665
666 static const char *drc_qr_rate_text[] = {
667         "0.725ms",
668         "1.45ms",
669         "5.8ms",
670 };
671
672 static const struct soc_enum drc_qr_rate =
673         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text);
674
675 static const char *drc_smooth_text[] = {
676         "Low",
677         "Medium",
678         "High",
679 };
680
681 static const struct soc_enum drc_smooth =
682         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text);
683
684 static const struct snd_kcontrol_new wm8993_snd_controls[] = {
685 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
686                5, 9, 12, 0, sidetone_tlv),
687
688 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
689 SOC_ENUM("DRC Path", drc_path),
690 SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8993_DRC_CONTROL_2,
691                2, 60, 1, drc_comp_threash),
692 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
693                11, 30, 1, drc_comp_amp),
694 SOC_ENUM("DRC R0", drc_r0),
695 SOC_ENUM("DRC R1", drc_r1),
696 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
697                drc_min_tlv),
698 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
699                drc_max_tlv),
700 SOC_ENUM("DRC Attack Rate", drc_attack),
701 SOC_ENUM("DRC Decay Rate", drc_decay),
702 SOC_ENUM("DRC FF Delay", drc_ff),
703 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
704 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
705 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
706                drc_qr_tlv),
707 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
708 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
709 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
710 SOC_ENUM("DRC Smoothing Hysteresis Threashold", drc_smooth),
711 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
712                drc_startup_tlv),
713
714 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
715
716 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
717                  WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
718 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
719 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
720
721 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
722                  WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
723 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
724                dac_boost_tlv),
725 SOC_ENUM("DAC Deemphasis", dac_deemph),
726
727 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
728                2, 1, 1, wm_hubs_spkmix_tlv),
729
730 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
731                2, 1, 1, wm_hubs_spkmix_tlv),
732 };
733
734 static const struct snd_kcontrol_new wm8993_eq_controls[] = {
735 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
736 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
737 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
738 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
739 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
740 };
741
742 static int clk_sys_event(struct snd_soc_dapm_widget *w,
743                          struct snd_kcontrol *kcontrol, int event)
744 {
745         struct snd_soc_codec *codec = w->codec;
746
747         switch (event) {
748         case SND_SOC_DAPM_PRE_PMU:
749                 return configure_clock(codec);
750
751         case SND_SOC_DAPM_POST_PMD:
752                 break;
753         }
754
755         return 0;
756 }
757
758 /*
759  * When used with DAC outputs only the WM8993 charge pump supports
760  * operation in class W mode, providing very low power consumption
761  * when used with digital sources.  Enable and disable this mode
762  * automatically depending on the mixer configuration.
763  *
764  * Currently the only supported paths are the direct DAC->headphone
765  * paths (which provide minimum power consumption anyway).
766  */
767 static int class_w_put(struct snd_kcontrol *kcontrol,
768                        struct snd_ctl_elem_value *ucontrol)
769 {
770         struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
771         struct snd_soc_codec *codec = widget->codec;
772         struct wm8993_priv *wm8993 = codec->private_data;
773         int ret;
774
775         /* Turn it off if we're using the main output mixer */
776         if (ucontrol->value.integer.value[0] == 0) {
777                 if (wm8993->class_w_users == 0) {
778                         dev_dbg(codec->dev, "Disabling Class W\n");
779                         snd_soc_update_bits(codec, WM8993_CLASS_W_0,
780                                             WM8993_CP_DYN_FREQ |
781                                             WM8993_CP_DYN_V,
782                                             0);
783                 }
784                 wm8993->class_w_users++;
785         }
786
787         /* Implement the change */
788         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
789
790         /* Enable it if we're using the direct DAC path */
791         if (ucontrol->value.integer.value[0] == 1) {
792                 if (wm8993->class_w_users == 1) {
793                         dev_dbg(codec->dev, "Enabling Class W\n");
794                         snd_soc_update_bits(codec, WM8993_CLASS_W_0,
795                                             WM8993_CP_DYN_FREQ |
796                                             WM8993_CP_DYN_V,
797                                             WM8993_CP_DYN_FREQ |
798                                             WM8993_CP_DYN_V);
799                 }
800                 wm8993->class_w_users--;
801         }
802
803         dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
804                 wm8993->class_w_users);
805
806         return ret;
807 }
808
809 #define SOC_DAPM_ENUM_W(xname, xenum) \
810 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
811         .info = snd_soc_info_enum_double, \
812         .get = snd_soc_dapm_get_enum_double, \
813         .put = class_w_put, \
814         .private_value = (unsigned long)&xenum }
815
816 static const char *hp_mux_text[] = {
817         "Mixer",
818         "DAC",
819 };
820
821 static const struct soc_enum hpl_enum =
822         SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
823
824 static const struct snd_kcontrol_new hpl_mux =
825         SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
826
827 static const struct soc_enum hpr_enum =
828         SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
829
830 static const struct snd_kcontrol_new hpr_mux =
831         SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
832
833 static const struct snd_kcontrol_new left_speaker_mixer[] = {
834 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
835 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
836 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
837 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
838 };
839
840 static const struct snd_kcontrol_new right_speaker_mixer[] = {
841 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
842 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
843 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
844 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
845 };
846
847 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
848 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
849                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
850 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
851 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
852
853
854 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8993_POWER_MANAGEMENT_2, 1, 0),
855 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8993_POWER_MANAGEMENT_2, 0, 0),
856
857 SND_SOC_DAPM_DAC("DACL", "Playback", WM8993_POWER_MANAGEMENT_3, 1, 0),
858 SND_SOC_DAPM_DAC("DACR", "Playback", WM8993_POWER_MANAGEMENT_3, 0, 0),
859
860 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
861 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
862
863 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
864                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
865 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
866                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
867
868 };
869
870 static const struct snd_soc_dapm_route routes[] = {
871         { "ADCL", NULL, "CLK_SYS" },
872         { "ADCL", NULL, "CLK_DSP" },
873         { "ADCR", NULL, "CLK_SYS" },
874         { "ADCR", NULL, "CLK_DSP" },
875
876         { "DACL", NULL, "CLK_SYS" },
877         { "DACL", NULL, "CLK_DSP" },
878         { "DACR", NULL, "CLK_SYS" },
879         { "DACR", NULL, "CLK_DSP" },
880
881         { "Left Output Mixer", "DAC Switch", "DACL" },
882
883         { "Right Output Mixer", "DAC Switch", "DACR" },
884
885         { "Left Output PGA", NULL, "CLK_SYS" },
886
887         { "Right Output PGA", NULL, "CLK_SYS" },
888
889         { "SPKL", "DAC Switch", "DACL" },
890         { "SPKL", NULL, "CLK_SYS" },
891
892         { "SPKR", "DAC Switch", "DACR" },
893         { "SPKR", NULL, "CLK_SYS" },
894
895         { "Left Headphone Mux", "DAC", "DACL" },
896         { "Right Headphone Mux", "DAC", "DACR" },
897 };
898
899 static int wm8993_set_bias_level(struct snd_soc_codec *codec,
900                                  enum snd_soc_bias_level level)
901 {
902         struct wm8993_priv *wm8993 = codec->private_data;
903
904         switch (level) {
905         case SND_SOC_BIAS_ON:
906         case SND_SOC_BIAS_PREPARE:
907                 /* VMID=2*40k */
908                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
909                                     WM8993_VMID_SEL_MASK, 0x2);
910                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
911                                     WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
912                 break;
913
914         case SND_SOC_BIAS_STANDBY:
915                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
916                         /* Bring up VMID with fast soft start */
917                         snd_soc_update_bits(codec, WM8993_ANTIPOP2,
918                                             WM8993_STARTUP_BIAS_ENA |
919                                             WM8993_VMID_BUF_ENA |
920                                             WM8993_VMID_RAMP_MASK |
921                                             WM8993_BIAS_SRC,
922                                             WM8993_STARTUP_BIAS_ENA |
923                                             WM8993_VMID_BUF_ENA |
924                                             WM8993_VMID_RAMP_MASK |
925                                             WM8993_BIAS_SRC);
926
927                         /* If either line output is single ended we
928                          * need the VMID buffer */
929                         if (!wm8993->pdata.lineout1_diff ||
930                             !wm8993->pdata.lineout2_diff)
931                                 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
932                                                  WM8993_LINEOUT_VMID_BUF_ENA,
933                                                  WM8993_LINEOUT_VMID_BUF_ENA);
934
935                         /* VMID=2*40k */
936                         snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
937                                             WM8993_VMID_SEL_MASK |
938                                             WM8993_BIAS_ENA,
939                                             WM8993_BIAS_ENA | 0x2);
940                         msleep(32);
941
942                         /* Switch to normal bias */
943                         snd_soc_update_bits(codec, WM8993_ANTIPOP2,
944                                             WM8993_BIAS_SRC |
945                                             WM8993_STARTUP_BIAS_ENA, 0);
946                 }
947
948                 /* VMID=2*240k */
949                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
950                                     WM8993_VMID_SEL_MASK, 0x4);
951
952                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
953                                     WM8993_TSHUT_ENA, 0);
954                 break;
955
956         case SND_SOC_BIAS_OFF:
957                 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
958                                     WM8993_LINEOUT_VMID_BUF_ENA, 0);
959
960                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
961                                     WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
962                                     0);
963                 break;
964         }
965
966         codec->bias_level = level;
967
968         return 0;
969 }
970
971 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
972                              int clk_id, unsigned int freq, int dir)
973 {
974         struct snd_soc_codec *codec = codec_dai->codec;
975         struct wm8993_priv *wm8993 = codec->private_data;
976
977         switch (clk_id) {
978         case WM8993_SYSCLK_MCLK:
979                 wm8993->mclk_rate = freq;
980         case WM8993_SYSCLK_FLL:
981                 wm8993->sysclk_source = clk_id;
982                 break;
983
984         default:
985                 return -EINVAL;
986         }
987
988         return 0;
989 }
990
991 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
992                               unsigned int fmt)
993 {
994         struct snd_soc_codec *codec = dai->codec;
995         struct wm8993_priv *wm8993 = codec->private_data;
996         unsigned int aif1 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_1);
997         unsigned int aif4 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_4);
998
999         aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1000                   WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1001         aif4 &= ~WM8993_LRCLK_DIR;
1002
1003         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1004         case SND_SOC_DAIFMT_CBS_CFS:
1005                 wm8993->master = 0;
1006                 break;
1007         case SND_SOC_DAIFMT_CBS_CFM:
1008                 aif4 |= WM8993_LRCLK_DIR;
1009                 wm8993->master = 1;
1010                 break;
1011         case SND_SOC_DAIFMT_CBM_CFS:
1012                 aif1 |= WM8993_BCLK_DIR;
1013                 wm8993->master = 1;
1014                 break;
1015         case SND_SOC_DAIFMT_CBM_CFM:
1016                 aif1 |= WM8993_BCLK_DIR;
1017                 aif4 |= WM8993_LRCLK_DIR;
1018                 wm8993->master = 1;
1019                 break;
1020         default:
1021                 return -EINVAL;
1022         }
1023
1024         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1025         case SND_SOC_DAIFMT_DSP_B:
1026                 aif1 |= WM8993_AIF_LRCLK_INV;
1027         case SND_SOC_DAIFMT_DSP_A:
1028                 aif1 |= 0x18;
1029                 break;
1030         case SND_SOC_DAIFMT_I2S:
1031                 aif1 |= 0x10;
1032                 break;
1033         case SND_SOC_DAIFMT_RIGHT_J:
1034                 break;
1035         case SND_SOC_DAIFMT_LEFT_J:
1036                 aif1 |= 0x8;
1037                 break;
1038         default:
1039                 return -EINVAL;
1040         }
1041
1042         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1043         case SND_SOC_DAIFMT_DSP_A:
1044         case SND_SOC_DAIFMT_DSP_B:
1045                 /* frame inversion not valid for DSP modes */
1046                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1047                 case SND_SOC_DAIFMT_NB_NF:
1048                         break;
1049                 case SND_SOC_DAIFMT_IB_NF:
1050                         aif1 |= WM8993_AIF_BCLK_INV;
1051                         break;
1052                 default:
1053                         return -EINVAL;
1054                 }
1055                 break;
1056
1057         case SND_SOC_DAIFMT_I2S:
1058         case SND_SOC_DAIFMT_RIGHT_J:
1059         case SND_SOC_DAIFMT_LEFT_J:
1060                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1061                 case SND_SOC_DAIFMT_NB_NF:
1062                         break;
1063                 case SND_SOC_DAIFMT_IB_IF:
1064                         aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1065                         break;
1066                 case SND_SOC_DAIFMT_IB_NF:
1067                         aif1 |= WM8993_AIF_BCLK_INV;
1068                         break;
1069                 case SND_SOC_DAIFMT_NB_IF:
1070                         aif1 |= WM8993_AIF_LRCLK_INV;
1071                         break;
1072                 default:
1073                         return -EINVAL;
1074                 }
1075                 break;
1076         default:
1077                 return -EINVAL;
1078         }
1079
1080         wm8993_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1081         wm8993_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1082
1083         return 0;
1084 }
1085
1086 static int wm8993_hw_params(struct snd_pcm_substream *substream,
1087                             struct snd_pcm_hw_params *params,
1088                             struct snd_soc_dai *dai)
1089 {
1090         struct snd_soc_codec *codec = dai->codec;
1091         struct wm8993_priv *wm8993 = codec->private_data;
1092         int ret, i, best, best_val, cur_val;
1093         unsigned int clocking1, clocking3, aif1, aif4;
1094
1095         clocking1 = wm8993_read(codec, WM8993_CLOCKING_1);
1096         clocking1 &= ~WM8993_BCLK_DIV_MASK;
1097
1098         clocking3 = wm8993_read(codec, WM8993_CLOCKING_3);
1099         clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1100
1101         aif1 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_1);
1102         aif1 &= ~WM8993_AIF_WL_MASK;
1103
1104         aif4 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_4);
1105         aif4 &= ~WM8993_LRCLK_RATE_MASK;
1106
1107         /* What BCLK do we need? */
1108         wm8993->fs = params_rate(params);
1109         wm8993->bclk = 2 * wm8993->fs;
1110         switch (params_format(params)) {
1111         case SNDRV_PCM_FORMAT_S16_LE:
1112                 wm8993->bclk *= 16;
1113                 break;
1114         case SNDRV_PCM_FORMAT_S20_3LE:
1115                 wm8993->bclk *= 20;
1116                 aif1 |= 0x8;
1117                 break;
1118         case SNDRV_PCM_FORMAT_S24_LE:
1119                 wm8993->bclk *= 24;
1120                 aif1 |= 0x10;
1121                 break;
1122         case SNDRV_PCM_FORMAT_S32_LE:
1123                 wm8993->bclk *= 32;
1124                 aif1 |= 0x18;
1125                 break;
1126         default:
1127                 return -EINVAL;
1128         }
1129
1130         dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1131
1132         ret = configure_clock(codec);
1133         if (ret != 0)
1134                 return ret;
1135
1136         /* Select nearest CLK_SYS_RATE */
1137         best = 0;
1138         best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1139                        - wm8993->fs);
1140         for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1141                 cur_val = abs((wm8993->sysclk_rate /
1142                                clk_sys_rates[i].ratio) - wm8993->fs);;
1143                 if (cur_val < best_val) {
1144                         best = i;
1145                         best_val = cur_val;
1146                 }
1147         }
1148         dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1149                 clk_sys_rates[best].ratio);
1150         clocking3 |= (clk_sys_rates[best].clk_sys_rate
1151                       << WM8993_CLK_SYS_RATE_SHIFT);
1152
1153         /* SAMPLE_RATE */
1154         best = 0;
1155         best_val = abs(wm8993->fs - sample_rates[0].rate);
1156         for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1157                 /* Closest match */
1158                 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1159                 if (cur_val < best_val) {
1160                         best = i;
1161                         best_val = cur_val;
1162                 }
1163         }
1164         dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1165                 sample_rates[best].rate);
1166         clocking3 |= (sample_rates[best].sample_rate
1167                       << WM8993_SAMPLE_RATE_SHIFT);
1168
1169         /* BCLK_DIV */
1170         best = 0;
1171         best_val = INT_MAX;
1172         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1173                 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1174                         - wm8993->bclk;
1175                 if (cur_val < 0) /* Table is sorted */
1176                         break;
1177                 if (cur_val < best_val) {
1178                         best = i;
1179                         best_val = cur_val;
1180                 }
1181         }
1182         wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1183         dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1184                 bclk_divs[best].div, wm8993->bclk);
1185         clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1186
1187         /* LRCLK is a simple fraction of BCLK */
1188         dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1189         aif4 |= wm8993->bclk / wm8993->fs;
1190
1191         wm8993_write(codec, WM8993_CLOCKING_1, clocking1);
1192         wm8993_write(codec, WM8993_CLOCKING_3, clocking3);
1193         wm8993_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1194         wm8993_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1195
1196         /* ReTune Mobile? */
1197         if (wm8993->pdata.num_retune_configs) {
1198                 u16 eq1 = wm8993_read(codec, WM8993_EQ1);
1199                 struct wm8993_retune_mobile_setting *s;
1200
1201                 best = 0;
1202                 best_val = abs(wm8993->pdata.retune_configs[0].rate
1203                                - wm8993->fs);
1204                 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1205                         cur_val = abs(wm8993->pdata.retune_configs[i].rate
1206                                       - wm8993->fs);
1207                         if (cur_val < best_val) {
1208                                 best_val = cur_val;
1209                                 best = i;
1210                         }
1211                 }
1212                 s = &wm8993->pdata.retune_configs[best];
1213
1214                 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1215                         s->name, s->rate);
1216
1217                 /* Disable EQ while we reconfigure */
1218                 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
1219
1220                 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1221                         wm8993_write(codec, WM8993_EQ1 + i, s->config[i]);
1222
1223                 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1224         }
1225
1226         return 0;
1227 }
1228
1229 static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1230 {
1231         struct snd_soc_codec *codec = codec_dai->codec;
1232         unsigned int reg;
1233
1234         reg = wm8993_read(codec, WM8993_DAC_CTRL);
1235
1236         if (mute)
1237                 reg |= WM8993_DAC_MUTE;
1238         else
1239                 reg &= ~WM8993_DAC_MUTE;
1240
1241         wm8993_write(codec, WM8993_DAC_CTRL, reg);
1242
1243         return 0;
1244 }
1245
1246 static struct snd_soc_dai_ops wm8993_ops = {
1247         .set_sysclk = wm8993_set_sysclk,
1248         .set_fmt = wm8993_set_dai_fmt,
1249         .hw_params = wm8993_hw_params,
1250         .digital_mute = wm8993_digital_mute,
1251         .set_pll = wm8993_set_fll,
1252 };
1253
1254 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1255
1256 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1257                         SNDRV_PCM_FMTBIT_S20_3LE |\
1258                         SNDRV_PCM_FMTBIT_S24_LE |\
1259                         SNDRV_PCM_FMTBIT_S32_LE)
1260
1261 struct snd_soc_dai wm8993_dai = {
1262         .name = "WM8993",
1263         .playback = {
1264                 .stream_name = "Playback",
1265                 .channels_min = 1,
1266                 .channels_max = 2,
1267                 .rates = WM8993_RATES,
1268                 .formats = WM8993_FORMATS,
1269         },
1270         .capture = {
1271                  .stream_name = "Capture",
1272                  .channels_min = 1,
1273                  .channels_max = 2,
1274                  .rates = WM8993_RATES,
1275                  .formats = WM8993_FORMATS,
1276          },
1277         .ops = &wm8993_ops,
1278         .symmetric_rates = 1,
1279 };
1280 EXPORT_SYMBOL_GPL(wm8993_dai);
1281
1282 static struct snd_soc_codec *wm8993_codec;
1283
1284 static int wm8993_probe(struct platform_device *pdev)
1285 {
1286         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1287         struct snd_soc_codec *codec;
1288         struct wm8993_priv *wm8993;
1289         int ret = 0;
1290
1291         if (!wm8993_codec) {
1292                 dev_err(&pdev->dev, "I2C device not yet probed\n");
1293                 goto err;
1294         }
1295
1296         socdev->card->codec = wm8993_codec;
1297         codec = wm8993_codec;
1298         wm8993 = codec->private_data;
1299
1300         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1301         if (ret < 0) {
1302                 dev_err(codec->dev, "failed to create pcms\n");
1303                 goto err;
1304         }
1305
1306         snd_soc_add_controls(codec, wm8993_snd_controls,
1307                              ARRAY_SIZE(wm8993_snd_controls));
1308         if (wm8993->pdata.num_retune_configs != 0) {
1309                 dev_dbg(codec->dev, "Using ReTune Mobile\n");
1310         } else {
1311                 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
1312                 snd_soc_add_controls(codec, wm8993_eq_controls,
1313                                      ARRAY_SIZE(wm8993_eq_controls));
1314         }
1315
1316         snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets,
1317                                   ARRAY_SIZE(wm8993_dapm_widgets));
1318         wm_hubs_add_analogue_controls(codec);
1319
1320         snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes));
1321         wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
1322                                     wm8993->pdata.lineout2_diff);
1323
1324         snd_soc_dapm_new_widgets(codec);
1325
1326         ret = snd_soc_init_card(socdev);
1327         if (ret < 0) {
1328                 dev_err(codec->dev, "failed to register card\n");
1329                 goto card_err;
1330         }
1331
1332         return ret;
1333
1334 card_err:
1335         snd_soc_free_pcms(socdev);
1336         snd_soc_dapm_free(socdev);
1337 err:
1338         return ret;
1339 }
1340
1341 static int wm8993_remove(struct platform_device *pdev)
1342 {
1343         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1344
1345         snd_soc_free_pcms(socdev);
1346         snd_soc_dapm_free(socdev);
1347
1348         return 0;
1349 }
1350
1351 struct snd_soc_codec_device soc_codec_dev_wm8993 = {
1352         .probe =        wm8993_probe,
1353         .remove =       wm8993_remove,
1354 };
1355 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8993);
1356
1357 static int wm8993_i2c_probe(struct i2c_client *i2c,
1358                             const struct i2c_device_id *id)
1359 {
1360         struct wm8993_priv *wm8993;
1361         struct snd_soc_codec *codec;
1362         unsigned int val;
1363         int ret;
1364
1365         if (wm8993_codec) {
1366                 dev_err(&i2c->dev, "A WM8993 is already registered\n");
1367                 return -EINVAL;
1368         }
1369
1370         wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL);
1371         if (wm8993 == NULL)
1372                 return -ENOMEM;
1373
1374         codec = &wm8993->codec;
1375         if (i2c->dev.platform_data)
1376                 memcpy(&wm8993->pdata, i2c->dev.platform_data,
1377                        sizeof(wm8993->pdata));
1378
1379         mutex_init(&codec->mutex);
1380         INIT_LIST_HEAD(&codec->dapm_widgets);
1381         INIT_LIST_HEAD(&codec->dapm_paths);
1382
1383         codec->name = "WM8993";
1384         codec->read = wm8993_read;
1385         codec->write = wm8993_write;
1386         codec->hw_write = (hw_write_t)i2c_master_send;
1387         codec->reg_cache = wm8993->reg_cache;
1388         codec->reg_cache_size = ARRAY_SIZE(wm8993->reg_cache);
1389         codec->bias_level = SND_SOC_BIAS_OFF;
1390         codec->set_bias_level = wm8993_set_bias_level;
1391         codec->dai = &wm8993_dai;
1392         codec->num_dai = 1;
1393         codec->private_data = wm8993;
1394
1395         memcpy(wm8993->reg_cache, wm8993_reg_defaults,
1396                sizeof(wm8993->reg_cache));
1397
1398         i2c_set_clientdata(i2c, wm8993);
1399         codec->control_data = i2c;
1400         wm8993_codec = codec;
1401
1402         codec->dev = &i2c->dev;
1403
1404         val = wm8993_read_hw(codec, WM8993_SOFTWARE_RESET);
1405         if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) {
1406                 dev_err(codec->dev, "Invalid ID register value %x\n", val);
1407                 ret = -EINVAL;
1408                 goto err;
1409         }
1410
1411         ret = wm8993_write(codec, WM8993_SOFTWARE_RESET, 0xffff);
1412         if (ret != 0)
1413                 goto err;
1414
1415         /* By default we're using the output mixers */
1416         wm8993->class_w_users = 2;
1417
1418         /* Latch volume update bits and default ZC on */
1419         snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1420                             WM8993_DAC_VU, WM8993_DAC_VU);
1421         snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1422                             WM8993_ADC_VU, WM8993_ADC_VU);
1423
1424         /* Manualy manage the HPOUT sequencing for independent stereo
1425          * control. */
1426         snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
1427                             WM8993_HPOUT1_AUTO_PU, 0);
1428
1429         /* Use automatic clock configuration */
1430         snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1431
1432         if (!wm8993->pdata.lineout1_diff)
1433                 snd_soc_update_bits(codec, WM8993_LINE_MIXER1,
1434                                     WM8993_LINEOUT1_MODE,
1435                                     WM8993_LINEOUT1_MODE);
1436         if (!wm8993->pdata.lineout2_diff)
1437                 snd_soc_update_bits(codec, WM8993_LINE_MIXER2,
1438                                     WM8993_LINEOUT2_MODE,
1439                                     WM8993_LINEOUT2_MODE);
1440
1441         if (wm8993->pdata.lineout1fb)
1442                 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
1443                                     WM8993_LINEOUT1_FB, WM8993_LINEOUT1_FB);
1444
1445         if (wm8993->pdata.lineout2fb)
1446                 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
1447                                     WM8993_LINEOUT2_FB, WM8993_LINEOUT2_FB);
1448
1449         /* Apply the microphone bias/detection configuration - the
1450          * platform data is directly applicable to the register. */
1451         snd_soc_update_bits(codec, WM8993_MICBIAS,
1452                             WM8993_JD_SCTHR_MASK | WM8993_JD_THR_MASK |
1453                             WM8993_MICB1_LVL | WM8993_MICB2_LVL,
1454                             wm8993->pdata.jd_scthr << WM8993_JD_SCTHR_SHIFT |
1455                             wm8993->pdata.jd_thr << WM8993_JD_THR_SHIFT |
1456                             wm8993->pdata.micbias1_lvl |
1457                             wm8993->pdata.micbias1_lvl << 1);
1458
1459         ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1460         if (ret != 0)
1461                 goto err;
1462
1463         wm8993_dai.dev = codec->dev;
1464
1465         ret = snd_soc_register_dai(&wm8993_dai);
1466         if (ret != 0)
1467                 goto err_bias;
1468
1469         ret = snd_soc_register_codec(codec);
1470
1471         return 0;
1472
1473 err_bias:
1474         wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1475 err:
1476         wm8993_codec = NULL;
1477         kfree(wm8993);
1478         return ret;
1479 }
1480
1481 static int wm8993_i2c_remove(struct i2c_client *client)
1482 {
1483         struct wm8993_priv *wm8993 = i2c_get_clientdata(client);
1484
1485         snd_soc_unregister_codec(&wm8993->codec);
1486         snd_soc_unregister_dai(&wm8993_dai);
1487
1488         wm8993_set_bias_level(&wm8993->codec, SND_SOC_BIAS_OFF);
1489         kfree(wm8993);
1490
1491         return 0;
1492 }
1493
1494 static const struct i2c_device_id wm8993_i2c_id[] = {
1495         { "wm8993", 0 },
1496         { }
1497 };
1498 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1499
1500 static struct i2c_driver wm8993_i2c_driver = {
1501         .driver = {
1502                 .name = "WM8993",
1503                 .owner = THIS_MODULE,
1504         },
1505         .probe = wm8993_i2c_probe,
1506         .remove = wm8993_i2c_remove,
1507         .id_table = wm8993_i2c_id,
1508 };
1509
1510
1511 static int __init wm8993_modinit(void)
1512 {
1513         int ret;
1514
1515         ret = i2c_add_driver(&wm8993_i2c_driver);
1516         if (ret != 0)
1517                 pr_err("WM8993: Unable to register I2C driver: %d\n", ret);
1518
1519         return ret;
1520 }
1521 module_init(wm8993_modinit);
1522
1523 static void __exit wm8993_exit(void)
1524 {
1525         i2c_del_driver(&wm8993_i2c_driver);
1526 }
1527 module_exit(wm8993_exit);
1528
1529
1530 MODULE_DESCRIPTION("ASoC WM8993 driver");
1531 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1532 MODULE_LICENSE("GPL");