sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #include <linux/pm_runtime.h>
  50 #include <linux/clocksource.h>
  51 #include <linux/time.h>
  52 #include <linux/completion.h>
  53 #include <linux/clk.h>
  54
  55 #ifdef CONFIG_X86
  56 /* for snoop control */
  57 #include <asm/pgtable.h>
  58 #include <asm/cacheflush.h>
  59 #endif
  60 #include <sound/core.h>
  61 #include <sound/initval.h>
  62 #include <linux/vgaarb.h>
  63 #include <linux/vga_switcheroo.h>
  64 #include <linux/firmware.h>
  65 #include "hda_codec.h"
  66
  67 #ifdef CONFIG_SND_HDA_VPR
  68 #include <linux/nvmap.h>
  69 #endif
  70
  71 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  72 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  73 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  74 static char *model[SNDRV_CARDS];
  75 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  76 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  77 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  78 static int probe_only[SNDRV_CARDS];
  79 static int jackpoll_ms[SNDRV_CARDS];
  80 static bool single_cmd;
  81 static int enable_msi = -1;
  82 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  83 static char *patch[SNDRV_CARDS];
  84 #endif
  85 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  86 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  87                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  88 #endif
  89
  90 module_param_array(index, int, NULL, 0444);
  91 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  92 module_param_array(id, charp, NULL, 0444);
  93 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  94 module_param_array(enable, bool, NULL, 0444);
  95 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  96 module_param_array(model, charp, NULL, 0444);
  97 MODULE_PARM_DESC(model, "Use the given board model.");
  98 module_param_array(position_fix, int, NULL, 0444);
  99 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 100                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
 101 module_param_array(bdl_pos_adj, int, NULL, 0644);
 102 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 103 module_param_array(probe_mask, int, NULL, 0444);
 104 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 105 module_param_array(probe_only, int, NULL, 0444);
 106 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 107 module_param_array(jackpoll_ms, int, NULL, 0444);
 108 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 109 module_param(single_cmd, bool, 0444);
 110 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 111                  "(for debugging only).");
 112 module_param(enable_msi, bint, 0444);
 113 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 114 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 115 module_param_array(patch, charp, NULL, 0444);
 116 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 117 #endif
 118 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 119 module_param_array(beep_mode, bool, NULL, 0444);
 120 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 121                             "(0=off, 1=on) (default=1).");
 122 #endif
 123
 124 #ifdef CONFIG_PM
 125 static int param_set_xint(const char *val, const struct kernel_param *kp);
 126 static struct kernel_param_ops param_ops_xint = {
 127         .set = param_set_xint,
 128         .get = param_get_int,
 129 };
 130 #define param_check_xint param_check_int
 131
 132 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 133 module_param(power_save, xint, 0644);
 134 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 135                  "(in second, 0 = disable).");
 136
 137 /* reset the HD-audio controller in power save mode.
 138  * this may give more power-saving, but will take longer time to
 139  * wake up.
 140  */
 141 static bool power_save_controller = 1;
 142 module_param(power_save_controller, bool, 0644);
 143 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 144 #endif /* CONFIG_PM */
 145
 146 static int align_buffer_size = -1;
 147 module_param(align_buffer_size, bint, 0644);
 148 MODULE_PARM_DESC(align_buffer_size,
 149                 "Force buffer and period sizes to be multiple of 128 bytes.");
 150
 151 #ifdef CONFIG_X86
 152 static bool hda_snoop = true;
 153 module_param_named(snoop, hda_snoop, bool, 0444);
 154 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 155 #define azx_snoop(chip)         (chip)->snoop
 156 #else
 157 #define hda_snoop               true
 158 #define azx_snoop(chip)         true
 159 #endif
 160
 161
 162 MODULE_LICENSE("GPL");
 163 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 164                          "{Intel, ICH6M},"
 165                          "{Intel, ICH7},"
 166                          "{Intel, ESB2},"
 167                          "{Intel, ICH8},"
 168                          "{Intel, ICH9},"
 169                          "{Intel, ICH10},"
 170                          "{Intel, PCH},"
 171                          "{Intel, CPT},"
 172                          "{Intel, PPT},"
 173                          "{Intel, LPT},"
 174                          "{Intel, LPT_LP},"
 175                          "{Intel, HPT},"
 176                          "{Intel, PBG},"
 177                          "{Intel, SCH},"
 178                          "{ATI, SB450},"
 179                          "{ATI, SB600},"
 180                          "{ATI, RS600},"
 181                          "{ATI, RS690},"
 182                          "{ATI, RS780},"
 183                          "{ATI, R600},"
 184                          "{ATI, RV630},"
 185                          "{ATI, RV610},"
 186                          "{ATI, RV670},"
 187                          "{ATI, RV635},"
 188                          "{ATI, RV620},"
 189                          "{ATI, RV770},"
 190                          "{VIA, VT8251},"
 191                          "{VIA, VT8237A},"
 192                          "{SiS, SIS966},"
 193                          "{ULI, M5461}}");
 194 MODULE_DESCRIPTION("Intel HDA driver");
 195
 196 #ifdef CONFIG_SND_VERBOSE_PRINTK
 197 #define SFX     /* nop */
 198 #else
 199 #define SFX     "hda-intel "
 200 #endif
 201
 202 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 203 #ifdef CONFIG_SND_HDA_CODEC_HDMI
 204 #define SUPPORT_VGA_SWITCHEROO
 205 #endif
 206 #endif
 207
 208
 209 /*
 210  * registers
 211  */
 212 #define ICH6_REG_GCAP                   0x00
 213 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 214 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 215 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 216 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 217 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 218 #define ICH6_REG_VMIN                   0x02
 219 #define ICH6_REG_VMAJ                   0x03
 220 #define ICH6_REG_OUTPAY                 0x04
 221 #define ICH6_REG_INPAY                  0x06
 222 #define ICH6_REG_GCTL                   0x08
 223 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 224 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 225 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 226 #define ICH6_REG_WAKEEN                 0x0c
 227 #define ICH6_REG_STATESTS               0x0e
 228 #define ICH6_REG_GSTS                   0x10
 229 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 230 #define ICH6_REG_INTCTL                 0x20
 231 #define ICH6_REG_INTSTS                 0x24
 232 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 233 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 234 #define ICH6_REG_SSYNC                  0x38
 235 #define ICH6_REG_CORBLBASE              0x40
 236 #define ICH6_REG_CORBUBASE              0x44
 237 #define ICH6_REG_CORBWP                 0x48
 238 #define ICH6_REG_CORBRP                 0x4a
 239 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 240 #define ICH6_REG_CORBCTL                0x4c
 241 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 242 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 243 #define ICH6_REG_CORBSTS                0x4d
 244 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 245 #define ICH6_REG_CORBSIZE               0x4e
 246
 247 #define ICH6_REG_RIRBLBASE              0x50
 248 #define ICH6_REG_RIRBUBASE              0x54
 249 #define ICH6_REG_RIRBWP                 0x58
 250 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 251 #define ICH6_REG_RINTCNT                0x5a
 252 #define ICH6_REG_RIRBCTL                0x5c
 253 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 254 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 255 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 256 #define ICH6_REG_RIRBSTS                0x5d
 257 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 258 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 259 #define ICH6_REG_RIRBSIZE               0x5e
 260
 261 #define ICH6_REG_IC                     0x60
 262 #define ICH6_REG_IR                     0x64
 263 #define ICH6_REG_IRS                    0x68
 264 #define   ICH6_IRS_VALID        (1<<1)
 265 #define   ICH6_IRS_BUSY         (1<<0)
 266
 267 #define ICH6_REG_DPLBASE                0x70
 268 #define ICH6_REG_DPUBASE                0x74
 269 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 270
 271 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 272 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 273
 274 /* stream register offsets from stream base */
 275 #define ICH6_REG_SD_CTL                 0x00
 276 #define ICH6_REG_SD_STS                 0x03
 277 #define ICH6_REG_SD_LPIB                0x04
 278 #define ICH6_REG_SD_CBL                 0x08
 279 #define ICH6_REG_SD_LVI                 0x0c
 280 #define ICH6_REG_SD_FIFOW               0x0e
 281 #define ICH6_REG_SD_FIFOSIZE            0x10
 282 #define ICH6_REG_SD_FORMAT              0x12
 283 #define ICH6_REG_SD_BDLPL               0x18
 284 #define ICH6_REG_SD_BDLPU               0x1c
 285
 286 /* PCI space */
 287 #define ICH6_PCIREG_TCSEL       0x44
 288
 289 /*
 290  * other constants
 291  */
 292
 293 /* max number of SDs */
 294 /* ICH, ATI and VIA have 4 playback and 4 capture */
 295 #define ICH6_NUM_CAPTURE        4
 296 #define ICH6_NUM_PLAYBACK       4
 297
 298 /* ULI has 6 playback and 5 capture */
 299 #define ULI_NUM_CAPTURE         5
 300 #define ULI_NUM_PLAYBACK        6
 301
 302 /* ATI HDMI has 1 playback and 0 capture */
 303 #define ATIHDMI_NUM_CAPTURE     0
 304 #define ATIHDMI_NUM_PLAYBACK    1
 305
 306 /* TERA has 4 playback and 3 capture */
 307 #define TERA_NUM_CAPTURE        3
 308 #define TERA_NUM_PLAYBACK       4
 309
 310 /* this number is statically defined for simplicity */
 311 #define MAX_AZX_DEV             16
 312
 313 /* max number of fragments - we may use more if allocating more pages for BDL */
 314 #define BDL_SIZE                4096
 315 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 316 #define AZX_MAX_FRAG            32
 317 /* max buffer size - no h/w limit, you can increase as you like */
 318 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 319
 320 /* RIRB int mask: overrun[2], response[0] */
 321 #define RIRB_INT_RESPONSE       0x01
 322 #define RIRB_INT_OVERRUN        0x04
 323 #define RIRB_INT_MASK           0x05
 324
 325 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 326 #define AZX_MAX_CODECS          8
 327 #define AZX_DEFAULT_CODECS      4
 328 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 329
 330 /* SD_CTL bits */
 331 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 332 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 333 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 334 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 335 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 336 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 337 #define SD_CTL_STREAM_TAG_SHIFT 20
 338
 339 /* SD_CTL and SD_STS */
 340 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 341 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 342 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 343 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 344                                  SD_INT_COMPLETE)
 345
 346 /* SD_STS */
 347 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 348
 349 /* INTCTL and INTSTS */
 350 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 351 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 352 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 353
 354 /* below are so far hardcoded - should read registers in future */
 355 #define ICH6_MAX_CORB_ENTRIES   256
 356 #define ICH6_MAX_RIRB_ENTRIES   256
 357
 358 /* position fix mode */
 359 enum {
 360         POS_FIX_AUTO,
 361         POS_FIX_LPIB,
 362         POS_FIX_POSBUF,
 363         POS_FIX_VIACOMBO,
 364         POS_FIX_COMBO,
 365 };
 366
 367 /* Defines for ATI HD Audio support in SB450 south bridge */
 368 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 369 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 370
 371 /* Defines for Nvidia HDA support */
 372 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 373 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 374 #define NVIDIA_HDA_ISTRM_COH          0x4d
 375 #define NVIDIA_HDA_OSTRM_COH          0x4c
 376 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 377
 378 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
 379 /* Defines for Nvidia Tegra HDA support */
 380 #define NVIDIA_TEGRA_HDA_BAR0_OFFSET           0x8000
 381
 382 #define NVIDIA_TEGRA_HDA_CFG_CMD_OFFSET        0x1004
 383 #define NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET       0x1010
 384
 385 #define NVIDIA_TEGRA_HDA_ENABLE_IO_SPACE       (1 << 0)
 386 #define NVIDIA_TEGRA_HDA_ENABLE_MEM_SPACE      (1 << 1)
 387 #define NVIDIA_TEGRA_HDA_ENABLE_BUS_MASTER     (1 << 2)
 388 #define NVIDIA_TEGRA_HDA_ENABLE_SERR           (1 << 8)
 389 #define NVIDIA_TEGRA_HDA_DISABLE_INTR          (1 << 10)
 390 #define NVIDIA_TEGRA_HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
 391 #define NVIDIA_TEGRA_HDA_BAR0_FINAL_PROGRAM    (1 << 14)
 392
 393 /* IPFS */
 394 #define NVIDIA_TEGRA_HDA_IPFS_CONFIG           0x180
 395 #define NVIDIA_TEGRA_HDA_IPFS_EN_FPCI          0x1
 396
 397 #define NVIDIA_TEGRA_HDA_IPFS_FPCI_BAR0        0x80
 398 #define NVIDIA_TEGRA_HDA_FPCI_BAR0_START       0x40
 399
 400 #define NVIDIA_TEGRA_HDA_IPFS_INTR_MASK        0x188
 401 #define NVIDIA_TEGRA_HDA_IPFS_EN_INTR          (1 << 16)
 402 #endif /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
 403
 404 /* Defines for Intel SCH HDA snoop control */
 405 #define INTEL_SCH_HDA_DEVC      0x78
 406 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 407
 408 /* Define IN stream 0 FIFO size offset in VIA controller */
 409 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 410 /* Define VIA HD Audio Device ID*/
 411 #define VIA_HDAC_DEVICE_ID              0x3288
 412
 413 /* HD Audio class code */
 414 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 415
 416 /*
 417  */
 418
 419 struct azx_dev {
 420         struct snd_dma_buffer bdl; /* BDL buffer */
 421         u32 *posbuf;            /* position buffer pointer */
 422
 423         unsigned int bufsize;   /* size of the play buffer in bytes */
 424         unsigned int period_bytes; /* size of the period in bytes */
 425         unsigned int frags;     /* number for period in the play buffer */
 426         unsigned int fifo_size; /* FIFO size */
 427         unsigned long start_wallclk;    /* start + minimum wallclk */
 428         unsigned long period_wallclk;   /* wallclk for period */
 429
 430         void __iomem *sd_addr;  /* stream descriptor pointer */
 431
 432         u32 sd_int_sta_mask;    /* stream int status mask */
 433
 434         /* pcm support */
 435         struct snd_pcm_substream *substream;    /* assigned substream,
 436                                                  * set in PCM open
 437                                                  */
 438         unsigned int format_val;        /* format value to be set in the
 439                                          * controller and the codec
 440                                          */
 441         unsigned char stream_tag;       /* assigned stream */
 442         unsigned char index;            /* stream index */
 443         int assigned_key;               /* last device# key assigned to */
 444
 445         unsigned int opened :1;
 446         unsigned int running :1;
 447         unsigned int irq_pending :1;
 448         unsigned int prepared:1;
 449         unsigned int locked:1;
 450         /*
 451          * For VIA:
 452          *  A flag to ensure DMA position is 0
 453          *  when link position is not greater than FIFO size
 454          */
 455         unsigned int insufficient :1;
 456         unsigned int wc_marked:1;
 457         unsigned int no_period_wakeup:1;
 458
 459         struct timecounter  azx_tc;
 460         struct cyclecounter azx_cc;
 461
 462 #ifdef CONFIG_SND_HDA_DSP_LOADER
 463         struct mutex dsp_mutex;
 464 #endif
 465 };
 466
 467 /* DSP lock helpers */
 468 #ifdef CONFIG_SND_HDA_DSP_LOADER
 469 #define dsp_lock_init(dev)      mutex_init(&(dev)->dsp_mutex)
 470 #define dsp_lock(dev)           mutex_lock(&(dev)->dsp_mutex)
 471 #define dsp_unlock(dev)         mutex_unlock(&(dev)->dsp_mutex)
 472 #define dsp_is_locked(dev)      ((dev)->locked)
 473 #else
 474 #define dsp_lock_init(dev)      do {} while (0)
 475 #define dsp_lock(dev)           do {} while (0)
 476 #define dsp_unlock(dev)         do {} while (0)
 477 #define dsp_is_locked(dev)      0
 478 #endif
 479
 480 /* CORB/RIRB */
 481 struct azx_rb {
 482         u32 *buf;               /* CORB/RIRB buffer
 483                                  * Each CORB entry is 4byte, RIRB is 8byte
 484                                  */
 485         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 486         /* for RIRB */
 487         unsigned short rp, wp;  /* read/write pointers */
 488         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 489         u32 res[AZX_MAX_CODECS];        /* last read value */
 490 };
 491
 492 struct azx_pcm {
 493         struct azx *chip;
 494         struct snd_pcm *pcm;
 495         struct hda_codec *codec;
 496         struct hda_pcm_stream *hinfo[2];
 497         struct list_head list;
 498 };
 499
 500 struct azx {
 501         struct snd_card *card;
 502         struct pci_dev *pci;
 503         struct platform_device *pdev;
 504         struct device *dev;
 505         int irq_id;
 506         int dev_index;
 507
 508         /* chip type specific */
 509         int driver_type;
 510         unsigned int driver_caps;
 511         int playback_streams;
 512         int playback_index_offset;
 513         int capture_streams;
 514         int capture_index_offset;
 515         int num_streams;
 516
 517         /* pci resources */
 518         unsigned long addr;
 519         void __iomem *remap_addr;
 520 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
 521         void __iomem *remap_config_addr;
 522 #endif
 523         int irq;
 524
 525 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
 526         /* platform driver clocks */
 527         struct clk **platform_clks;
 528         int platform_clk_count;
 529         int platform_clk_enable;
 530 #endif
 531
 532 #ifdef CONFIG_SND_HDA_VPR
 533         struct nvmap_client *hda_vpr;
 534         struct nvmap_handle_ref *handle_ref;
 535         unsigned char *vaddr;
 536         phys_addr_t paddr;
 537 #endif
 538
 539         /* locks */
 540         spinlock_t reg_lock;
 541         struct mutex open_mutex;
 542         struct completion probe_wait;
 543
 544         /* streams (x num_streams) */
 545         struct azx_dev *azx_dev;
 546
 547         /* PCM */
 548         struct list_head pcm_list; /* azx_pcm list */
 549
 550         /* HD codec */
 551         unsigned short codec_mask;
 552         int  codec_probe_mask; /* copied from probe_mask option */
 553         struct hda_bus *bus;
 554         unsigned int beep_mode;
 555
 556         /* CORB/RIRB */
 557         struct azx_rb corb;
 558         struct azx_rb rirb;
 559
 560         /* CORB/RIRB and position buffers */
 561         struct snd_dma_buffer rb;
 562         struct snd_dma_buffer posbuf;
 563
 564 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 565         const struct firmware *fw;
 566 #endif
 567
 568         /* flags */
 569         int position_fix[2]; /* for both playback/capture streams */
 570         int poll_count;
 571         unsigned int running :1;
 572         unsigned int initialized :1;
 573         unsigned int single_cmd :1;
 574         unsigned int polling_mode :1;
 575         unsigned int msi :1;
 576         unsigned int irq_pending_warned :1;
 577         unsigned int probing :1; /* codec probing phase */
 578         unsigned int snoop:1;
 579         unsigned int align_buffer_size:1;
 580         unsigned int region_requested:1;
 581
 582         /* VGA-switcheroo setup */
 583         unsigned int use_vga_switcheroo:1;
 584         unsigned int vga_switcheroo_registered:1;
 585         unsigned int init_failed:1; /* delayed init failed */
 586         unsigned int disabled:1; /* disabled by VGA-switcher */
 587
 588         /* for debugging */
 589         unsigned int last_cmd[AZX_MAX_CODECS];
 590
 591         /* for pending irqs */
 592         struct work_struct irq_pending_work;
 593
 594         /* reboot notifier (for mysterious hangup problem at power-down) */
 595         struct notifier_block reboot_notifier;
 596
 597         /* card list (for power_save trigger) */
 598         struct list_head list;
 599
 600 #ifdef CONFIG_SND_HDA_DSP_LOADER
 601         struct azx_dev saved_azx_dev;
 602 #endif
 603 };
 604
 605 #define CREATE_TRACE_POINTS
 606 #include "hda_intel_trace.h"
 607
 608 /* driver types */
 609 enum {
 610         AZX_DRIVER_ICH,
 611         AZX_DRIVER_PCH,
 612         AZX_DRIVER_SCH,
 613         AZX_DRIVER_ATI,
 614         AZX_DRIVER_ATIHDMI,
 615         AZX_DRIVER_ATIHDMI_NS,
 616         AZX_DRIVER_VIA,
 617         AZX_DRIVER_SIS,
 618         AZX_DRIVER_ULI,
 619         AZX_DRIVER_NVIDIA,
 620         AZX_DRIVER_NVIDIA_TEGRA,
 621         AZX_DRIVER_TERA,
 622         AZX_DRIVER_CTX,
 623         AZX_DRIVER_CTHDA,
 624         AZX_DRIVER_GENERIC,
 625         AZX_NUM_DRIVERS, /* keep this as last entry */
 626 };
 627
 628 /* driver quirks (capabilities) */
 629 /* bits 0-7 are used for indicating driver type */
 630 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 631 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 632 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 633 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 634 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 635 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 636 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 637 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 638 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 639 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 640 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 641 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 642 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 643 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 644 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
 645 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
 646 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
 647 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
 648
 649 /* quirks for Intel PCH */
 650 #define AZX_DCAPS_INTEL_PCH_NOPM \
 651         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
 652          AZX_DCAPS_COUNT_LPIB_DELAY)
 653
 654 #define AZX_DCAPS_INTEL_PCH \
 655         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
 656
 657 /* quirks for ATI SB / AMD Hudson */
 658 #define AZX_DCAPS_PRESET_ATI_SB \
 659         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 660          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 661
 662 /* quirks for ATI/AMD HDMI */
 663 #define AZX_DCAPS_PRESET_ATI_HDMI \
 664         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 665
 666 /* quirks for Nvidia */
 667 #define AZX_DCAPS_PRESET_NVIDIA \
 668         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
 669          AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
 670
 671 #define AZX_DCAPS_PRESET_CTHDA \
 672         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
 673
 674 /*
 675  * VGA-switcher support
 676  */
 677 #ifdef SUPPORT_VGA_SWITCHEROO
 678 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 679 #else
 680 #define use_vga_switcheroo(chip)        0
 681 #endif
 682
 683 static char *driver_short_names[] = {
 684         [AZX_DRIVER_ICH] = "HDA Intel",
 685         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 686         [AZX_DRIVER_SCH] = "HDA Intel MID",
 687         [AZX_DRIVER_ATI] = "HDA ATI SB",
 688         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 689         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 690         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 691         [AZX_DRIVER_SIS] = "HDA SIS966",
 692         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 693         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 694         [AZX_DRIVER_NVIDIA_TEGRA] = "HDA NVIDIA Tegra",
 695         [AZX_DRIVER_TERA] = "HDA Teradici",
 696         [AZX_DRIVER_CTX] = "HDA Creative",
 697         [AZX_DRIVER_CTHDA] = "HDA Creative",
 698         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 699 };
 700
 701 /*
 702  * macros for easy use
 703  */
 704 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
 705 #define MASK_LONG_ALIGN         0x3UL
 706 #define SHIFT_BYTE              3
 707 #define SHIFT_BITS(reg)         ((reg & MASK_LONG_ALIGN) << SHIFT_BYTE)
 708 #define ADDR_ALIGN_L(base, reg) (base + (reg & ~MASK_LONG_ALIGN))
 709 #define MASK(bits)              (BIT(bits) - 1)
 710 #define MASK_REG(reg, bits)     (MASK(bits) << SHIFT_BITS(reg))
 711
 712 #define tegra_write(base, reg, val, bits) \
 713         writel((readl(ADDR_ALIGN_L(base, reg)) & ~MASK_REG(reg, bits)) | \
 714                ((val) << SHIFT_BITS(reg)), ADDR_ALIGN_L(base, reg))
 715
 716 #define tegra_read(base, reg, bits) \
 717         ((readl(ADDR_ALIGN_L(base, reg)) >> SHIFT_BITS(reg)) & MASK(bits))
 718
 719 #define azx_writel(chip, reg, value) \
 720         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 721 #define azx_readl(chip, reg) \
 722         readl((chip)->remap_addr + ICH6_REG_##reg)
 723 #define azx_writew(chip, reg, value) \
 724         tegra_write((chip)->remap_addr, ICH6_REG_##reg, value, 16)
 725 #define azx_readw(chip, reg) \
 726         tegra_read((chip)->remap_addr, ICH6_REG_##reg, 16)
 727 #define azx_writeb(chip, reg, value) \
 728         tegra_write((chip)->remap_addr, ICH6_REG_##reg, value, 8)
 729 #define azx_readb(chip, reg) \
 730         tegra_read((chip)->remap_addr, ICH6_REG_##reg, 8)
 731
 732 #define azx_sd_writel(dev, reg, value) \
 733         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 734 #define azx_sd_readl(dev, reg) \
 735         readl((dev)->sd_addr + ICH6_REG_##reg)
 736 #define azx_sd_writew(dev, reg, value) \
 737         tegra_write((dev)->sd_addr, ICH6_REG_##reg, value, 16)
 738 #define azx_sd_readw(dev, reg) \
 739         tegra_read((dev)->sd_addr, ICH6_REG_##reg, 16)
 740 #define azx_sd_writeb(dev, reg, value) \
 741         tegra_write((dev)->sd_addr, ICH6_REG_##reg, value, 8)
 742 #define azx_sd_readb(dev, reg) \
 743         tegra_read((dev)->sd_addr, ICH6_REG_##reg, 8)
 744
 745 #else /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
 746 #define azx_writel(chip,reg,value) \
 747         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 748 #define azx_readl(chip,reg) \
 749         readl((chip)->remap_addr + ICH6_REG_##reg)
 750 #define azx_writew(chip,reg,value) \
 751         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 752 #define azx_readw(chip,reg) \
 753         readw((chip)->remap_addr + ICH6_REG_##reg)
 754 #define azx_writeb(chip,reg,value) \
 755         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 756 #define azx_readb(chip,reg) \
 757         readb((chip)->remap_addr + ICH6_REG_##reg)
 758
 759 #define azx_sd_writel(dev,reg,value) \
 760         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 761 #define azx_sd_readl(dev,reg) \
 762         readl((dev)->sd_addr + ICH6_REG_##reg)
 763 #define azx_sd_writew(dev,reg,value) \
 764         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 765 #define azx_sd_readw(dev,reg) \
 766         readw((dev)->sd_addr + ICH6_REG_##reg)
 767 #define azx_sd_writeb(dev,reg,value) \
 768         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 769 #define azx_sd_readb(dev,reg) \
 770         readb((dev)->sd_addr + ICH6_REG_##reg)
 771
 772 #endif /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
 773
 774 /* for pcm support */
 775 #define get_azx_dev(substream) (substream->runtime->private_data)
 776
 777 #ifdef CONFIG_X86
 778 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 779 {
 780         int pages;
 781
 782         if (azx_snoop(chip))
 783                 return;
 784         if (!dmab || !dmab->area || !dmab->bytes)
 785                 return;
 786
 787 #ifdef CONFIG_SND_DMA_SGBUF
 788         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 789                 struct snd_sg_buf *sgbuf = dmab->private_data;
 790                 if (on)
 791                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 792                 else
 793                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 794                 return;
 795         }
 796 #endif
 797
 798         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 799         if (on)
 800                 set_memory_wc((unsigned long)dmab->area, pages);
 801         else
 802                 set_memory_wb((unsigned long)dmab->area, pages);
 803 }
 804
 805 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 806                                  bool on)
 807 {
 808         __mark_pages_wc(chip, buf, on);
 809 }
 810 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 811                                    struct snd_pcm_substream *substream, bool on)
 812 {
 813         if (azx_dev->wc_marked != on) {
 814                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 815                 azx_dev->wc_marked = on;
 816         }
 817 }
 818 #else
 819 /* NOP for other archs */
 820 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 821                                  bool on)
 822 {
 823 }
 824 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 825                                    struct snd_pcm_substream *substream, bool on)
 826 {
 827 }
 828 #endif
 829
 830 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 831 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 832 /*
 833  * Interface for HD codec
 834  */
 835
 836 /*
 837  * CORB / RIRB interface
 838  */
 839 static int azx_alloc_cmd_io(struct azx *chip)
 840 {
 841         int err;
 842
 843         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 844         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 845                                   chip->dev,
 846                                   PAGE_SIZE, &chip->rb);
 847         if (err < 0) {
 848                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
 849                 return err;
 850         }
 851         mark_pages_wc(chip, &chip->rb, true);
 852         return 0;
 853 }
 854
 855 static void azx_init_cmd_io(struct azx *chip)
 856 {
 857         spin_lock_irq(&chip->reg_lock);
 858         /* CORB set up */
 859         chip->corb.addr = chip->rb.addr;
 860         chip->corb.buf = (u32 *)chip->rb.area;
 861         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 862         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 863
 864         /* set the corb size to 256 entries (ULI requires explicitly) */
 865         azx_writeb(chip, CORBSIZE, 0x02);
 866         /* set the corb write pointer to 0 */
 867         azx_writew(chip, CORBWP, 0);
 868         /* reset the corb hw read pointer */
 869         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 870         /* enable corb dma */
 871         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 872
 873         /* RIRB set up */
 874         chip->rirb.addr = chip->rb.addr + 2048;
 875         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 876         chip->rirb.wp = chip->rirb.rp = 0;
 877         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 878         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 879         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 880
 881         /* set the rirb size to 256 entries (ULI requires explicitly) */
 882         azx_writeb(chip, RIRBSIZE, 0x02);
 883         /* reset the rirb hw write pointer */
 884         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 885         /* set N=1, get RIRB response interrupt for new entry */
 886         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 887                 azx_writew(chip, RINTCNT, 0xc0);
 888         else
 889                 azx_writew(chip, RINTCNT, 1);
 890         /* enable rirb dma and response irq */
 891         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 892         spin_unlock_irq(&chip->reg_lock);
 893 }
 894
 895 static void azx_free_cmd_io(struct azx *chip)
 896 {
 897         spin_lock_irq(&chip->reg_lock);
 898         /* disable ringbuffer DMAs */
 899         azx_writeb(chip, RIRBCTL, 0);
 900         azx_writeb(chip, CORBCTL, 0);
 901         spin_unlock_irq(&chip->reg_lock);
 902 }
 903
 904 static unsigned int azx_command_addr(u32 cmd)
 905 {
 906         unsigned int addr = cmd >> 28;
 907
 908         if (addr >= AZX_MAX_CODECS) {
 909                 snd_BUG();
 910                 addr = 0;
 911         }
 912
 913         return addr;
 914 }
 915
 916 static unsigned int azx_response_addr(u32 res)
 917 {
 918         unsigned int addr = res & 0xf;
 919
 920         if (addr >= AZX_MAX_CODECS) {
 921                 snd_BUG();
 922                 addr = 0;
 923         }
 924
 925         return addr;
 926 }
 927
 928 /* send a command */
 929 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 930 {
 931         struct azx *chip = bus->private_data;
 932         unsigned int addr = azx_command_addr(val);
 933         unsigned int wp, rp;
 934
 935         spin_lock_irq(&chip->reg_lock);
 936
 937         /* add command to corb */
 938         wp = azx_readw(chip, CORBWP);
 939         if (wp == 0xffff) {
 940                 /* something wrong, controller likely turned to D3 */
 941                 spin_unlock_irq(&chip->reg_lock);
 942                 return -EIO;
 943         }
 944         wp++;
 945         wp %= ICH6_MAX_CORB_ENTRIES;
 946
 947         rp = azx_readw(chip, CORBRP);
 948         if (wp == rp) {
 949                 /* oops, it's full */
 950                 spin_unlock_irq(&chip->reg_lock);
 951                 return -EAGAIN;
 952         }
 953
 954         chip->rirb.cmds[addr]++;
 955         chip->corb.buf[wp] = cpu_to_le32(val);
 956         azx_writel(chip, CORBWP, wp);
 957
 958         spin_unlock_irq(&chip->reg_lock);
 959
 960         return 0;
 961 }
 962
 963 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 964
 965 /* retrieve RIRB entry - called from interrupt handler */
 966 static void azx_update_rirb(struct azx *chip)
 967 {
 968         unsigned int rp, wp;
 969         unsigned int addr;
 970         u32 res, res_ex;
 971
 972         wp = azx_readw(chip, RIRBWP);
 973         if (wp == 0xffff) {
 974                 /* something wrong, controller likely turned to D3 */
 975                 return;
 976         }
 977
 978         if (wp == chip->rirb.wp)
 979                 return;
 980         chip->rirb.wp = wp;
 981
 982         while (chip->rirb.rp != wp) {
 983                 chip->rirb.rp++;
 984                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 985
 986                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 987                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 988                 res = le32_to_cpu(chip->rirb.buf[rp]);
 989                 addr = azx_response_addr(res_ex);
 990                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 991                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 992                 else if (chip->rirb.cmds[addr]) {
 993                         chip->rirb.res[addr] = res;
 994                         smp_wmb();
 995                         chip->rirb.cmds[addr]--;
 996                 } else
 997                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
 998                                    "last cmd=%#08x\n",
 999                                    pci_name(chip->pci),
1000                                    res, res_ex,
1001                                    chip->last_cmd[addr]);
1002         }
1003 }
1004
1005 /* receive a response */
1006 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
1007                                           unsigned int addr)
1008 {
1009         struct azx *chip = bus->private_data;
1010         unsigned long timeout;
1011         unsigned long loopcounter;
1012         int do_poll = 0;
1013
1014  again:
1015         timeout = jiffies + msecs_to_jiffies(1000);
1016
1017         for (loopcounter = 0;; loopcounter++) {
1018                 if (chip->polling_mode || do_poll) {
1019                         spin_lock_irq(&chip->reg_lock);
1020                         azx_update_rirb(chip);
1021                         spin_unlock_irq(&chip->reg_lock);
1022                 }
1023                 if (!chip->rirb.cmds[addr]) {
1024                         smp_rmb();
1025                         bus->rirb_error = 0;
1026
1027                         if (!do_poll)
1028                                 chip->poll_count = 0;
1029                         return chip->rirb.res[addr]; /* the last value */
1030                 }
1031                 if (time_after(jiffies, timeout))
1032                         break;
1033                 if (bus->needs_damn_long_delay || loopcounter > 3000)
1034                         msleep(2); /* temporary workaround */
1035                 else {
1036                         udelay(10);
1037                         cond_resched();
1038                 }
1039         }
1040
1041         if (!chip->polling_mode && chip->poll_count < 2) {
1042                 snd_printdd(SFX "%s: azx_get_response timeout, "
1043                            "polling the codec once: last cmd=0x%08x\n",
1044                            pci_name(chip->pci), chip->last_cmd[addr]);
1045                 do_poll = 1;
1046                 chip->poll_count++;
1047                 goto again;
1048         }
1049
1050
1051         if (!chip->polling_mode) {
1052                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
1053                            "switching to polling mode: last cmd=0x%08x\n",
1054                            pci_name(chip->pci), chip->last_cmd[addr]);
1055                 chip->polling_mode = 1;
1056                 goto again;
1057         }
1058
1059         if (chip->msi) {
1060                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
1061                            "disabling MSI: last cmd=0x%08x\n",
1062                            pci_name(chip->pci), chip->last_cmd[addr]);
1063                 free_irq(chip->irq, chip);
1064                 chip->irq = -1;
1065                 pci_disable_msi(chip->pci);
1066                 chip->msi = 0;
1067                 if (azx_acquire_irq(chip, 1) < 0) {
1068                         bus->rirb_error = 1;
1069                         return -1;
1070                 }
1071                 goto again;
1072         }
1073
1074         if (chip->probing) {
1075                 /* If this critical timeout happens during the codec probing
1076                  * phase, this is likely an access to a non-existing codec
1077                  * slot.  Better to return an error and reset the system.
1078                  */
1079                 return -1;
1080         }
1081
1082         /* a fatal communication error; need either to reset or to fallback
1083          * to the single_cmd mode
1084          */
1085         bus->rirb_error = 1;
1086         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
1087                 bus->response_reset = 1;
1088                 return -1; /* give a chance to retry */
1089         }
1090
1091         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
1092                    "switching to single_cmd mode: last cmd=0x%08x\n",
1093                    chip->last_cmd[addr]);
1094         chip->single_cmd = 1;
1095         bus->response_reset = 0;
1096         /* release CORB/RIRB */
1097         azx_free_cmd_io(chip);
1098         /* disable unsolicited responses */
1099         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1100         return -1;
1101 }
1102
1103 /*
1104  * Use the single immediate command instead of CORB/RIRB for simplicity
1105  *
1106  * Note: according to Intel, this is not preferred use.  The command was
1107  *       intended for the BIOS only, and may get confused with unsolicited
1108  *       responses.  So, we shouldn't use it for normal operation from the
1109  *       driver.
1110  *       I left the codes, however, for debugging/testing purposes.
1111  */
1112
1113 /* receive a response */
1114 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1115 {
1116         int timeout = 50;
1117
1118         while (timeout--) {
1119                 /* check IRV busy bit */
1120                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1121                         /* reuse rirb.res as the response return value */
1122                         chip->rirb.res[addr] = azx_readl(chip, IR);
1123                         return 0;
1124                 }
1125                 udelay(1);
1126         }
1127         if (printk_ratelimit())
1128                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1129                            pci_name(chip->pci), azx_readw(chip, IRS));
1130         chip->rirb.res[addr] = -1;
1131         return -EIO;
1132 }
1133
1134 /* send a command */
1135 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1136 {
1137         struct azx *chip = bus->private_data;
1138         unsigned int addr = azx_command_addr(val);
1139         int timeout = 50;
1140
1141         bus->rirb_error = 0;
1142         while (timeout--) {
1143                 /* check ICB busy bit */
1144                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1145                         /* Clear IRV valid bit */
1146                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1147                                    ICH6_IRS_VALID);
1148                         azx_writel(chip, IC, val);
1149                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1150                                    ICH6_IRS_BUSY);
1151                         return azx_single_wait_for_response(chip, addr);
1152                 }
1153                 udelay(1);
1154         }
1155         if (printk_ratelimit())
1156                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1157                            pci_name(chip->pci), azx_readw(chip, IRS), val);
1158         return -EIO;
1159 }
1160
1161 /* receive a response */
1162 static unsigned int azx_single_get_response(struct hda_bus *bus,
1163                                             unsigned int addr)
1164 {
1165         struct azx *chip = bus->private_data;
1166         return chip->rirb.res[addr];
1167 }
1168
1169 /*
1170  * The below are the main callbacks from hda_codec.
1171  *
1172  * They are just the skeleton to call sub-callbacks according to the
1173  * current setting of chip->single_cmd.
1174  */
1175
1176 /* send a command */
1177 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1178 {
1179         struct azx *chip = bus->private_data;
1180
1181         if (chip->disabled)
1182                 return 0;
1183         chip->last_cmd[azx_command_addr(val)] = val;
1184         if (chip->single_cmd)
1185                 return azx_single_send_cmd(bus, val);
1186         else
1187                 return azx_corb_send_cmd(bus, val);
1188 }
1189
1190 /* get a response */
1191 static unsigned int azx_get_response(struct hda_bus *bus,
1192                                      unsigned int addr)
1193 {
1194         struct azx *chip = bus->private_data;
1195         if (chip->disabled)
1196                 return 0;
1197         if (chip->single_cmd)
1198                 return azx_single_get_response(bus, addr);
1199         else
1200                 return azx_rirb_get_response(bus, addr);
1201 }
1202
1203 #ifdef CONFIG_PM
1204 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1205 #endif
1206
1207 #ifdef CONFIG_SND_HDA_DSP_LOADER
1208 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1209                                 unsigned int byte_size,
1210                                 struct snd_dma_buffer *bufp);
1211 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1212 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1213                                  struct snd_dma_buffer *dmab);
1214 #endif
1215
1216 /* reset codec link */
1217 static int azx_reset(struct azx *chip, int full_reset)
1218 {
1219         unsigned long timeout;
1220
1221         if (!full_reset)
1222                 goto __skip;
1223
1224         /* clear STATESTS */
1225         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1226
1227         /* reset controller */
1228         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1229
1230         timeout = jiffies + msecs_to_jiffies(100);
1231         while (azx_readb(chip, GCTL) &&
1232                         time_before(jiffies, timeout))
1233                 usleep_range(500, 1000);
1234
1235         /* delay for >= 100us for codec PLL to settle per spec
1236          * Rev 0.9 section 5.5.1
1237          */
1238         usleep_range(500, 1000);
1239
1240         /* Bring controller out of reset */
1241         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1242
1243         timeout = jiffies + msecs_to_jiffies(100);
1244         while (!azx_readb(chip, GCTL) &&
1245                         time_before(jiffies, timeout))
1246                 usleep_range(500, 1000);
1247
1248         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1249         usleep_range(1000, 1200);
1250
1251       __skip:
1252         /* check to see if controller is ready */
1253         if (!azx_readb(chip, GCTL)) {
1254                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1255                 return -EBUSY;
1256         }
1257
1258         /* Accept unsolicited responses */
1259         if (!chip->single_cmd)
1260                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1261                            ICH6_GCTL_UNSOL);
1262
1263         /* detect codecs */
1264         if (!chip->codec_mask) {
1265                 chip->codec_mask = azx_readw(chip, STATESTS);
1266                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1267         }
1268
1269         return 0;
1270 }
1271
1272
1273 /*
1274  * Lowlevel interface
1275  */
1276
1277 /* enable interrupts */
1278 static void azx_int_enable(struct azx *chip)
1279 {
1280         /* enable controller CIE and GIE */
1281         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1282                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1283 }
1284
1285 /* disable interrupts */
1286 static void azx_int_disable(struct azx *chip)
1287 {
1288         int i;
1289
1290         /* disable interrupts in stream descriptor */
1291         for (i = 0; i < chip->num_streams; i++) {
1292                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1293                 azx_sd_writeb(azx_dev, SD_CTL,
1294                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1295         }
1296
1297         /* disable SIE for all streams */
1298         azx_writeb(chip, INTCTL, 0);
1299
1300         /* disable controller CIE and GIE */
1301         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1302                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1303 }
1304
1305 /* clear interrupts */
1306 static void azx_int_clear(struct azx *chip)
1307 {
1308         int i;
1309
1310         /* clear stream status */
1311         for (i = 0; i < chip->num_streams; i++) {
1312                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1313                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1314         }
1315
1316         /* clear STATESTS */
1317         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1318
1319         /* clear rirb status */
1320         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1321
1322         /* clear int status */
1323         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1324 }
1325
1326 /* start a stream */
1327 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1328 {
1329         /*
1330          * Before stream start, initialize parameter
1331          */
1332         azx_dev->insufficient = 1;
1333
1334         /* enable SIE */
1335         azx_writel(chip, INTCTL,
1336                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1337         /* set DMA start and interrupt mask */
1338         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1339                       SD_CTL_DMA_START | SD_INT_MASK);
1340 }
1341
1342 /* stop DMA */
1343 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1344 {
1345         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1346                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1347         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1348 }
1349
1350 /* stop a stream */
1351 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1352 {
1353         azx_stream_clear(chip, azx_dev);
1354         /* disable SIE */
1355         azx_writel(chip, INTCTL,
1356                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1357 }
1358
1359
1360 /*
1361  * reset and start the controller registers
1362  */
1363 static void azx_init_chip(struct azx *chip, int full_reset)
1364 {
1365         if (chip->initialized)
1366                 return;
1367
1368         /* reset controller */
1369         azx_reset(chip, full_reset);
1370
1371         /* initialize interrupts */
1372         azx_int_clear(chip);
1373         azx_int_enable(chip);
1374
1375         /* initialize the codec command I/O */
1376         if (!chip->single_cmd)
1377                 azx_init_cmd_io(chip);
1378
1379         /* program the position buffer */
1380         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1381         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1382
1383         chip->initialized = 1;
1384 }
1385
1386 /*
1387  * initialize the PCI registers
1388  */
1389 /* update bits in a PCI register byte */
1390 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1391                             unsigned char mask, unsigned char val)
1392 {
1393         unsigned char data;
1394
1395         pci_read_config_byte(pci, reg, &data);
1396         data &= ~mask;
1397         data |= (val & mask);
1398         pci_write_config_byte(pci, reg, data);
1399 }
1400
1401 static void azx_init_pci(struct azx *chip)
1402 {
1403         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1404          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1405          * Ensuring these bits are 0 clears playback static on some HD Audio
1406          * codecs.
1407          * The PCI register TCSEL is defined in the Intel manuals.
1408          */
1409         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1410                 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1411                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1412         }
1413
1414         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1415          * we need to enable snoop.
1416          */
1417         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1418                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1419                 update_pci_byte(chip->pci,
1420                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1421                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1422         }
1423
1424         /* For NVIDIA HDA, enable snoop */
1425         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1426                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1427                 update_pci_byte(chip->pci,
1428                                 NVIDIA_HDA_TRANSREG_ADDR,
1429                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1430                 update_pci_byte(chip->pci,
1431                                 NVIDIA_HDA_ISTRM_COH,
1432                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1433                 update_pci_byte(chip->pci,
1434                                 NVIDIA_HDA_OSTRM_COH,
1435                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1436         }
1437
1438         /* Enable SCH/PCH snoop if needed */
1439         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1440                 unsigned short snoop;
1441                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1442                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1443                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1444                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1445                         if (!azx_snoop(chip))
1446                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1447                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1448                         pci_read_config_word(chip->pci,
1449                                 INTEL_SCH_HDA_DEVC, &snoop);
1450                 }
1451                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1452                                 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1453                                 ? "Disabled" : "Enabled");
1454         }
1455 }
1456
1457 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
1458 /*
1459  * initialize the platform specific registers
1460  */
1461 static void reg_update_bits(void __iomem *base, unsigned int reg,
1462                             unsigned int mask, unsigned int val)
1463 {
1464         unsigned int data;
1465
1466         data = readl(base + reg);
1467         data &= ~mask;
1468         data |= (val & mask);
1469         writel(data, base + reg);
1470 }
1471
1472 static void azx_init_platform(struct azx *chip)
1473 {
1474         switch (chip->driver_type) {
1475 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
1476         case AZX_DRIVER_NVIDIA_TEGRA:
1477                 /*Enable the PCI access */
1478                 reg_update_bits(chip->remap_config_addr,
1479                                 NVIDIA_TEGRA_HDA_IPFS_CONFIG,
1480                                 NVIDIA_TEGRA_HDA_IPFS_EN_FPCI,
1481                                 NVIDIA_TEGRA_HDA_IPFS_EN_FPCI);
1482                 /* Enable MEM/IO space and bus master */
1483                 reg_update_bits(chip->remap_config_addr,
1484                                 NVIDIA_TEGRA_HDA_CFG_CMD_OFFSET, 0x507,
1485                                 NVIDIA_TEGRA_HDA_ENABLE_MEM_SPACE |
1486                                 NVIDIA_TEGRA_HDA_ENABLE_IO_SPACE |
1487                                 NVIDIA_TEGRA_HDA_ENABLE_BUS_MASTER |
1488                                 NVIDIA_TEGRA_HDA_ENABLE_SERR);
1489                 reg_update_bits(chip->remap_config_addr,
1490                                 NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET, 0xFFFFFFFF,
1491                                 NVIDIA_TEGRA_HDA_BAR0_INIT_PROGRAM);
1492                 reg_update_bits(chip->remap_config_addr,
1493                                 NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET, 0xFFFFFFFF,
1494                                 NVIDIA_TEGRA_HDA_BAR0_FINAL_PROGRAM);
1495                 reg_update_bits(chip->remap_config_addr,
1496                                 NVIDIA_TEGRA_HDA_IPFS_FPCI_BAR0, 0xFFFFFFFF,
1497                                 NVIDIA_TEGRA_HDA_FPCI_BAR0_START);
1498                 reg_update_bits(chip->remap_config_addr,
1499                                 NVIDIA_TEGRA_HDA_IPFS_INTR_MASK,
1500                                 NVIDIA_TEGRA_HDA_IPFS_EN_INTR,
1501                                 NVIDIA_TEGRA_HDA_IPFS_EN_INTR);
1502                 break;
1503 #endif
1504         default:
1505                 break;
1506         }
1507
1508         return;
1509 }
1510
1511 static void azx_platform_enable_clocks(struct azx *chip)
1512 {
1513         int i;
1514
1515         for (i = 0; i < chip->platform_clk_count; i++)
1516                 clk_enable(chip->platform_clks[i]);
1517
1518         chip->platform_clk_enable++;
1519 }
1520
1521 static void azx_platform_disable_clocks(struct azx *chip)
1522 {
1523         int i;
1524
1525         if (!chip->platform_clk_enable)
1526                 return;
1527
1528         for (i = 0; i < chip->platform_clk_count; i++)
1529                 clk_disable(chip->platform_clks[i]);
1530
1531         chip->platform_clk_enable--;
1532 }
1533 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
1534
1535 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1536
1537 /*
1538  * interrupt handler
1539  */
1540 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1541 {
1542         struct azx *chip = dev_id;
1543         struct azx_dev *azx_dev;
1544         u32 status;
1545         u8 sd_status;
1546         int i, ok;
1547
1548 #ifdef CONFIG_PM_RUNTIME
1549         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1550                 return IRQ_NONE;
1551 #endif
1552
1553         spin_lock(&chip->reg_lock);
1554
1555         if (chip->disabled) {
1556                 spin_unlock(&chip->reg_lock);
1557                 return IRQ_NONE;
1558         }
1559
1560         status = azx_readl(chip, INTSTS);
1561         if (status == 0) {
1562                 spin_unlock(&chip->reg_lock);
1563                 return IRQ_NONE;
1564         }
1565
1566         for (i = 0; i < chip->num_streams; i++) {
1567                 azx_dev = &chip->azx_dev[i];
1568                 if (status & azx_dev->sd_int_sta_mask) {
1569                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1570                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1571                         if (!azx_dev->substream || !azx_dev->running ||
1572                             !(sd_status & SD_INT_COMPLETE))
1573                                 continue;
1574                         /* check whether this IRQ is really acceptable */
1575                         ok = azx_position_ok(chip, azx_dev);
1576                         if (ok == 1) {
1577                                 azx_dev->irq_pending = 0;
1578                                 spin_unlock(&chip->reg_lock);
1579                                 snd_pcm_period_elapsed(azx_dev->substream);
1580                                 spin_lock(&chip->reg_lock);
1581                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1582                                 /* bogus IRQ, process it later */
1583                                 azx_dev->irq_pending = 1;
1584                                 queue_work(chip->bus->workq,
1585                                            &chip->irq_pending_work);
1586                         }
1587                 }
1588         }
1589
1590         /* clear rirb int */
1591         status = azx_readb(chip, RIRBSTS);
1592         if (status & RIRB_INT_MASK) {
1593                 if (status & RIRB_INT_RESPONSE) {
1594                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1595                                 udelay(80);
1596                         azx_update_rirb(chip);
1597                 }
1598                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1599         }
1600
1601 #if 0
1602         /* clear state status int */
1603         if (azx_readb(chip, STATESTS) & 0x04)
1604                 azx_writeb(chip, STATESTS, 0x04);
1605 #endif
1606         spin_unlock(&chip->reg_lock);
1607
1608         return IRQ_HANDLED;
1609 }
1610
1611
1612 /*
1613  * set up a BDL entry
1614  */
1615 static int setup_bdle(struct azx *chip,
1616                       struct snd_dma_buffer *dmab,
1617                       struct azx_dev *azx_dev, u32 **bdlp,
1618                       int ofs, int size, int with_ioc)
1619 {
1620         u32 *bdl = *bdlp;
1621
1622         while (size > 0) {
1623                 dma_addr_t addr;
1624                 int chunk;
1625
1626                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1627                         return -EINVAL;
1628
1629                 addr = snd_sgbuf_get_addr(dmab, ofs);
1630                 /* program the address field of the BDL entry */
1631                 bdl[0] = cpu_to_le32((u32)addr);
1632                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1633                 /* program the size field of the BDL entry */
1634                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1635                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1636                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1637                         u32 remain = 0x1000 - (ofs & 0xfff);
1638                         if (chunk > remain)
1639                                 chunk = remain;
1640                 }
1641                 bdl[2] = cpu_to_le32(chunk);
1642                 /* program the IOC to enable interrupt
1643                  * only when the whole fragment is processed
1644                  */
1645                 size -= chunk;
1646                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1647                 bdl += 4;
1648                 azx_dev->frags++;
1649                 ofs += chunk;
1650         }
1651         *bdlp = bdl;
1652         return ofs;
1653 }
1654
1655 /*
1656  * set up BDL entries
1657  */
1658 static int azx_setup_periods(struct azx *chip,
1659                              struct snd_pcm_substream *substream,
1660                              struct azx_dev *azx_dev)
1661 {
1662         u32 *bdl;
1663         int i, ofs, periods, period_bytes;
1664         int pos_adj;
1665
1666         /* reset BDL address */
1667         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1668         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1669
1670         period_bytes = azx_dev->period_bytes;
1671         periods = azx_dev->bufsize / period_bytes;
1672
1673         /* program the initial BDL entries */
1674         bdl = (u32 *)azx_dev->bdl.area;
1675         ofs = 0;
1676         azx_dev->frags = 0;
1677         pos_adj = bdl_pos_adj[chip->dev_index];
1678         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1679                 struct snd_pcm_runtime *runtime = substream->runtime;
1680                 int pos_align = pos_adj;
1681                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1682                 if (!pos_adj)
1683                         pos_adj = pos_align;
1684                 else
1685                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1686                                 pos_align;
1687                 pos_adj = frames_to_bytes(runtime, pos_adj);
1688                 if (pos_adj >= period_bytes) {
1689                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1690                                    pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1691                         pos_adj = 0;
1692                 } else {
1693                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1694                                          azx_dev,
1695                                          &bdl, ofs, pos_adj, true);
1696                         if (ofs < 0)
1697                                 goto error;
1698                 }
1699         } else
1700                 pos_adj = 0;
1701         for (i = 0; i < periods; i++) {
1702                 if (i == periods - 1 && pos_adj)
1703                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1704                                          azx_dev, &bdl, ofs,
1705                                          period_bytes - pos_adj, 0);
1706                 else
1707                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1708                                          azx_dev, &bdl, ofs,
1709                                          period_bytes,
1710                                          !azx_dev->no_period_wakeup);
1711                 if (ofs < 0)
1712                         goto error;
1713         }
1714         return 0;
1715
1716  error:
1717         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1718                    pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1719         return -EINVAL;
1720 }
1721
1722 /* reset stream */
1723 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1724 {
1725         unsigned char val;
1726         int timeout;
1727
1728         azx_stream_clear(chip, azx_dev);
1729
1730         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1731                       SD_CTL_STREAM_RESET);
1732         udelay(3);
1733         timeout = 300;
1734         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1735                --timeout)
1736                 ;
1737         val &= ~SD_CTL_STREAM_RESET;
1738         azx_sd_writeb(azx_dev, SD_CTL, val);
1739         udelay(3);
1740
1741         timeout = 300;
1742         /* waiting for hardware to report that the stream is out of reset */
1743         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1744                --timeout)
1745                 ;
1746
1747         /* reset first position - may not be synced with hw at this time */
1748         *azx_dev->posbuf = 0;
1749 }
1750
1751 /*
1752  * set up the SD for streaming
1753  */
1754 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1755 {
1756         unsigned int val;
1757         /* make sure the run bit is zero for SD */
1758         azx_stream_clear(chip, azx_dev);
1759         /* program the stream_tag */
1760         val = azx_sd_readl(azx_dev, SD_CTL);
1761         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1762                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1763         if (!azx_snoop(chip))
1764                 val |= SD_CTL_TRAFFIC_PRIO;
1765         azx_sd_writel(azx_dev, SD_CTL, val);
1766
1767         /* program the length of samples in cyclic buffer */
1768         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1769
1770         /* program the stream format */
1771         /* this value needs to be the same as the one programmed */
1772         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1773
1774         /* program the stream LVI (last valid index) of the BDL */
1775         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1776
1777         /* program the BDL address */
1778         /* lower BDL address */
1779         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1780         /* upper BDL address */
1781         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1782
1783         /* enable the position buffer */
1784         if (chip->position_fix[0] != POS_FIX_LPIB ||
1785             chip->position_fix[1] != POS_FIX_LPIB) {
1786                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1787                         azx_writel(chip, DPLBASE,
1788                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1789         }
1790
1791         /* set the interrupt enable bits in the descriptor control register */
1792         azx_sd_writel(azx_dev, SD_CTL,
1793                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1794
1795         return 0;
1796 }
1797
1798 /*
1799  * Probe the given codec address
1800  */
1801 static int probe_codec(struct azx *chip, int addr)
1802 {
1803         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1804                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1805         unsigned int res;
1806
1807         mutex_lock(&chip->bus->cmd_mutex);
1808         chip->probing = 1;
1809         azx_send_cmd(chip->bus, cmd);
1810         res = azx_get_response(chip->bus, addr);
1811         chip->probing = 0;
1812         mutex_unlock(&chip->bus->cmd_mutex);
1813         if (res == -1)
1814                 return -EIO;
1815         snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1816         return 0;
1817 }
1818
1819 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1820                                  struct hda_pcm *cpcm);
1821 static void azx_stop_chip(struct azx *chip);
1822
1823 static void azx_bus_reset(struct hda_bus *bus)
1824 {
1825         struct azx *chip = bus->private_data;
1826
1827         bus->in_reset = 1;
1828         azx_stop_chip(chip);
1829         azx_init_chip(chip, 1);
1830 #ifdef CONFIG_PM
1831         if (chip->initialized) {
1832                 struct azx_pcm *p;
1833                 list_for_each_entry(p, &chip->pcm_list, list)
1834                         snd_pcm_suspend_all(p->pcm);
1835                 snd_hda_suspend(chip->bus);
1836                 snd_hda_resume(chip->bus);
1837         }
1838 #endif
1839         bus->in_reset = 0;
1840 }
1841
1842 static int get_jackpoll_interval(struct azx *chip)
1843 {
1844         int i = jackpoll_ms[chip->dev_index];
1845         unsigned int j;
1846         if (i == 0)
1847                 return 0;
1848         if (i < 50 || i > 60000)
1849                 j = 0;
1850         else
1851                 j = msecs_to_jiffies(i);
1852         if (j == 0)
1853                 snd_printk(KERN_WARNING SFX
1854                            "jackpoll_ms value out of range: %d\n", i);
1855         return j;
1856 }
1857
1858 /*
1859  * Codec initialization
1860  */
1861
1862 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1863 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1864         [AZX_DRIVER_NVIDIA] = 8,
1865         [AZX_DRIVER_TERA] = 1,
1866 };
1867
1868 static int azx_codec_create(struct azx *chip, const char *model)
1869 {
1870         struct hda_bus_template bus_temp;
1871         int c, codecs, err;
1872         int max_slots;
1873
1874         memset(&bus_temp, 0, sizeof(bus_temp));
1875         bus_temp.private_data = chip;
1876         bus_temp.modelname = model;
1877         bus_temp.pci = chip->pci;
1878         bus_temp.pdev = chip->pdev;
1879         bus_temp.ops.command = azx_send_cmd;
1880         bus_temp.ops.get_response = azx_get_response;
1881         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1882         bus_temp.ops.bus_reset = azx_bus_reset;
1883 #ifdef CONFIG_PM
1884         bus_temp.power_save = &power_save;
1885         bus_temp.ops.pm_notify = azx_power_notify;
1886 #endif
1887 #ifdef CONFIG_SND_HDA_DSP_LOADER
1888         bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1889         bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1890         bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1891 #endif
1892
1893         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1894         if (err < 0)
1895                 return err;
1896
1897         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1898                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1899                 chip->bus->needs_damn_long_delay = 1;
1900         }
1901
1902         codecs = 0;
1903         max_slots = azx_max_codecs[chip->driver_type];
1904         if (!max_slots)
1905                 max_slots = AZX_DEFAULT_CODECS;
1906
1907         /* First try to probe all given codec slots */
1908         for (c = 0; c < max_slots; c++) {
1909                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1910                         if (probe_codec(chip, c) < 0) {
1911                                 /* Some BIOSen give you wrong codec addresses
1912                                  * that don't exist
1913                                  */
1914                                 snd_printk(KERN_WARNING SFX
1915                                            "%s: Codec #%d probe error; "
1916                                            "disabling it...\n", pci_name(chip->pci), c);
1917                                 chip->codec_mask &= ~(1 << c);
1918                                 /* More badly, accessing to a non-existing
1919                                  * codec often screws up the controller chip,
1920                                  * and disturbs the further communications.
1921                                  * Thus if an error occurs during probing,
1922                                  * better to reset the controller chip to
1923                                  * get back to the sanity state.
1924                                  */
1925                                 azx_stop_chip(chip);
1926                                 azx_init_chip(chip, 1);
1927                         }
1928                 }
1929         }
1930
1931         /* AMD chipsets often cause the communication stalls upon certain
1932          * sequence like the pin-detection.  It seems that forcing the synced
1933          * access works around the stall.  Grrr...
1934          */
1935         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1936                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1937                         pci_name(chip->pci));
1938                 chip->bus->sync_write = 1;
1939                 chip->bus->allow_bus_reset = 1;
1940         }
1941
1942         /* Then create codec instances */
1943         for (c = 0; c < max_slots; c++) {
1944                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1945                         struct hda_codec *codec;
1946                         err = snd_hda_codec_new(chip->bus, c, &codec);
1947                         if (err < 0)
1948                                 continue;
1949                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1950                         codec->beep_mode = chip->beep_mode;
1951                         codecs++;
1952                 }
1953         }
1954         if (!codecs) {
1955                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1956                 return -ENXIO;
1957         }
1958         return 0;
1959 }
1960
1961 /* configure each codec instance */
1962 static int azx_codec_configure(struct azx *chip)
1963 {
1964         struct hda_codec *codec;
1965         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1966                 snd_hda_codec_configure(codec);
1967         }
1968         return 0;
1969 }
1970
1971
1972 /*
1973  * PCM support
1974  */
1975
1976 /* assign a stream for the PCM */
1977 static inline struct azx_dev *
1978 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1979 {
1980         int dev, i, nums;
1981         struct azx_dev *res = NULL;
1982         /* make a non-zero unique key for the substream */
1983         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1984                 (substream->stream + 1);
1985
1986         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1987                 dev = chip->playback_index_offset;
1988                 nums = chip->playback_streams;
1989         } else {
1990                 dev = chip->capture_index_offset;
1991                 nums = chip->capture_streams;
1992         }
1993         for (i = 0; i < nums; i++, dev++) {
1994                 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1995                 dsp_lock(azx_dev);
1996                 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1997                         res = azx_dev;
1998                         if (res->assigned_key == key) {
1999                                 res->opened = 1;
2000                                 res->assigned_key = key;
2001                                 dsp_unlock(azx_dev);
2002                                 return azx_dev;
2003                         }
2004                 }
2005                 dsp_unlock(azx_dev);
2006         }
2007         if (res) {
2008                 dsp_lock(res);
2009                 res->opened = 1;
2010                 res->assigned_key = key;
2011                 dsp_unlock(res);
2012         }
2013         return res;
2014 }
2015
2016 /* release the assigned stream */
2017 static inline void azx_release_device(struct azx_dev *azx_dev)
2018 {
2019         azx_dev->opened = 0;
2020 }
2021
2022 static cycle_t azx_cc_read(const struct cyclecounter *cc)
2023 {
2024         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
2025         struct snd_pcm_substream *substream = azx_dev->substream;
2026         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2027         struct azx *chip = apcm->chip;
2028
2029         return azx_readl(chip, WALLCLK);
2030 }
2031
2032 static void azx_timecounter_init(struct snd_pcm_substream *substream,
2033                                 bool force, cycle_t last)
2034 {
2035         struct azx_dev *azx_dev = get_azx_dev(substream);
2036         struct timecounter *tc = &azx_dev->azx_tc;
2037         struct cyclecounter *cc = &azx_dev->azx_cc;
2038         u64 nsec;
2039
2040         cc->read = azx_cc_read;
2041         cc->mask = CLOCKSOURCE_MASK(32);
2042
2043         /*
2044          * Converting from 24 MHz to ns means applying a 125/3 factor.
2045          * To avoid any saturation issues in intermediate operations,
2046          * the 125 factor is applied first. The division is applied
2047          * last after reading the timecounter value.
2048          * Applying the 1/3 factor as part of the multiplication
2049          * requires at least 20 bits for a decent precision, however
2050          * overflows occur after about 4 hours or less, not a option.
2051          */
2052
2053         cc->mult = 125; /* saturation after 195 years */
2054         cc->shift = 0;
2055
2056         nsec = 0; /* audio time is elapsed time since trigger */
2057         timecounter_init(tc, cc, nsec);
2058         if (force)
2059                 /*
2060                  * force timecounter to use predefined value,
2061                  * used for synchronized starts
2062                  */
2063                 tc->cycle_last = last;
2064 }
2065
2066 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
2067                                 u64 nsec)
2068 {
2069         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2070         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2071         u64 codec_frames, codec_nsecs;
2072
2073         if (!hinfo->ops.get_delay)
2074                 return nsec;
2075
2076         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
2077         codec_nsecs = div_u64(codec_frames * 1000000000LL,
2078                               substream->runtime->rate);
2079
2080         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2081                 return nsec + codec_nsecs;
2082
2083         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
2084 }
2085
2086 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
2087                                 struct timespec *ts)
2088 {
2089         struct azx_dev *azx_dev = get_azx_dev(substream);
2090         u64 nsec;
2091
2092         nsec = timecounter_read(&azx_dev->azx_tc);
2093         nsec = div_u64(nsec, 3); /* can be optimized */
2094         nsec = azx_adjust_codec_delay(substream, nsec);
2095
2096         *ts = ns_to_timespec(nsec);
2097
2098         return 0;
2099 }
2100
2101 static struct snd_pcm_hardware azx_pcm_hw = {
2102         .info =                 (SNDRV_PCM_INFO_MMAP |
2103                                  SNDRV_PCM_INFO_INTERLEAVED |
2104                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
2105                                  SNDRV_PCM_INFO_MMAP_VALID |
2106                                  /* No full-resume yet implemented */
2107                                  /* SNDRV_PCM_INFO_RESUME |*/
2108                                  SNDRV_PCM_INFO_PAUSE |
2109                                  SNDRV_PCM_INFO_SYNC_START |
2110                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
2111                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
2112         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
2113         .rates =                SNDRV_PCM_RATE_48000,
2114         .rate_min =             48000,
2115         .rate_max =             48000,
2116         .channels_min =         2,
2117         .channels_max =         2,
2118         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
2119         .period_bytes_min =     128,
2120         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
2121         .periods_min =          2,
2122         .periods_max =          AZX_MAX_FRAG,
2123         .fifo_size =            0,
2124 };
2125
2126 static int azx_pcm_open(struct snd_pcm_substream *substream)
2127 {
2128         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2129         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2130         struct azx *chip = apcm->chip;
2131         struct azx_dev *azx_dev;
2132         struct snd_pcm_runtime *runtime = substream->runtime;
2133         unsigned long flags;
2134         int err;
2135         int buff_step;
2136
2137         mutex_lock(&chip->open_mutex);
2138         azx_dev = azx_assign_device(chip, substream);
2139         if (azx_dev == NULL) {
2140                 mutex_unlock(&chip->open_mutex);
2141                 return -EBUSY;
2142         }
2143         runtime->hw = azx_pcm_hw;
2144         runtime->hw.channels_min = hinfo->channels_min;
2145         runtime->hw.channels_max = hinfo->channels_max;
2146         runtime->hw.formats = hinfo->formats;
2147         runtime->hw.rates = hinfo->rates;
2148         snd_pcm_limit_hw_rates(runtime);
2149         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
2150
2151         /* avoid wrap-around with wall-clock */
2152         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2153                                 20,
2154                                 178000000);
2155
2156         if (chip->align_buffer_size)
2157                 /* constrain buffer sizes to be multiple of 128
2158                    bytes. This is more efficient in terms of memory
2159                    access but isn't required by the HDA spec and
2160                    prevents users from specifying exact period/buffer
2161                    sizes. For example for 44.1kHz, a period size set
2162                    to 20ms will be rounded to 19.59ms. */
2163                 buff_step = 128;
2164         else
2165                 /* Don't enforce steps on buffer sizes, still need to
2166                    be multiple of 4 bytes (HDA spec). Tested on Intel
2167                    HDA controllers, may not work on all devices where
2168                    option needs to be disabled */
2169                 buff_step = 4;
2170
2171         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2172                                    buff_step);
2173         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2174                                    buff_step);
2175         snd_hda_power_up_d3wait(apcm->codec);
2176         err = hinfo->ops.open(hinfo, apcm->codec, substream);
2177         if (err < 0) {
2178                 azx_release_device(azx_dev);
2179                 snd_hda_power_down(apcm->codec);
2180                 mutex_unlock(&chip->open_mutex);
2181                 return err;
2182         }
2183         snd_pcm_limit_hw_rates(runtime);
2184         /* sanity check */
2185         if (snd_BUG_ON(!runtime->hw.channels_min) ||
2186             snd_BUG_ON(!runtime->hw.channels_max) ||
2187             snd_BUG_ON(!runtime->hw.formats) ||
2188             snd_BUG_ON(!runtime->hw.rates)) {
2189                 azx_release_device(azx_dev);
2190                 hinfo->ops.close(hinfo, apcm->codec, substream);
2191                 snd_hda_power_down(apcm->codec);
2192                 mutex_unlock(&chip->open_mutex);
2193                 return -EINVAL;
2194         }
2195
2196         /* disable WALLCLOCK timestamps for capture streams
2197            until we figure out how to handle digital inputs */
2198         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2199                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2200
2201         spin_lock_irqsave(&chip->reg_lock, flags);
2202         azx_dev->substream = substream;
2203         azx_dev->running = 0;
2204         spin_unlock_irqrestore(&chip->reg_lock, flags);
2205
2206         runtime->private_data = azx_dev;
2207         snd_pcm_set_sync(substream);
2208         mutex_unlock(&chip->open_mutex);
2209         return 0;
2210 }
2211
2212 static int azx_pcm_close(struct snd_pcm_substream *substream)
2213 {
2214         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2215         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2216         struct azx *chip = apcm->chip;
2217         struct azx_dev *azx_dev = get_azx_dev(substream);
2218         unsigned long flags;
2219
2220         mutex_lock(&chip->open_mutex);
2221         spin_lock_irqsave(&chip->reg_lock, flags);
2222         azx_dev->substream = NULL;
2223         azx_dev->running = 0;
2224         spin_unlock_irqrestore(&chip->reg_lock, flags);
2225         azx_release_device(azx_dev);
2226         hinfo->ops.close(hinfo, apcm->codec, substream);
2227         snd_hda_power_down(apcm->codec);
2228         mutex_unlock(&chip->open_mutex);
2229         return 0;
2230 }
2231
2232 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2233                              struct snd_pcm_hw_params *hw_params)
2234 {
2235         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2236         struct azx *chip = apcm->chip;
2237         struct azx_dev *azx_dev = get_azx_dev(substream);
2238         int ret;
2239
2240         dsp_lock(azx_dev);
2241         if (dsp_is_locked(azx_dev)) {
2242                 ret = -EBUSY;
2243                 goto unlock;
2244         }
2245
2246         mark_runtime_wc(chip, azx_dev, substream, false);
2247         azx_dev->bufsize = 0;
2248         azx_dev->period_bytes = 0;
2249         azx_dev->format_val = 0;
2250         ret = snd_pcm_lib_malloc_pages(substream,
2251                                         params_buffer_bytes(hw_params));
2252         if (ret < 0)
2253                 goto unlock;
2254         mark_runtime_wc(chip, azx_dev, substream, true);
2255  unlock:
2256         dsp_unlock(azx_dev);
2257         return ret;
2258 }
2259
2260 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2261 {
2262         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2263         struct azx_dev *azx_dev = get_azx_dev(substream);
2264         struct azx *chip = apcm->chip;
2265         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2266
2267         /* reset BDL address */
2268         dsp_lock(azx_dev);
2269         if (!dsp_is_locked(azx_dev)) {
2270                 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2271                 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2272                 azx_sd_writel(azx_dev, SD_CTL, 0);
2273                 azx_dev->bufsize = 0;
2274                 azx_dev->period_bytes = 0;
2275                 azx_dev->format_val = 0;
2276         }
2277
2278         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2279
2280         mark_runtime_wc(chip, azx_dev, substream, false);
2281         azx_dev->prepared = 0;
2282         dsp_unlock(azx_dev);
2283         return snd_pcm_lib_free_pages(substream);
2284 }
2285
2286 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2287 {
2288         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2289         struct azx *chip = apcm->chip;
2290         struct azx_dev *azx_dev = get_azx_dev(substream);
2291         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2292         struct snd_pcm_runtime *runtime = substream->runtime;
2293         unsigned int bufsize, period_bytes, format_val, stream_tag;
2294         int err;
2295         struct hda_spdif_out *spdif =
2296                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2297         unsigned short ctls = spdif ? spdif->ctls : 0;
2298
2299         dsp_lock(azx_dev);
2300         if (dsp_is_locked(azx_dev)) {
2301                 err = -EBUSY;
2302                 goto unlock;
2303         }
2304
2305         azx_stream_reset(chip, azx_dev);
2306         format_val = snd_hda_calc_stream_format(runtime->rate,
2307                                                 runtime->channels,
2308                                                 runtime->format,
2309                                                 hinfo->maxbps,
2310                                                 ctls);
2311         if (!format_val) {
2312                 snd_printk(KERN_ERR SFX
2313                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2314                            pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2315                 err = -EINVAL;
2316                 goto unlock;
2317         }
2318
2319         bufsize = snd_pcm_lib_buffer_bytes(substream);
2320         period_bytes = snd_pcm_lib_period_bytes(substream);
2321
2322         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2323                     pci_name(chip->pci), bufsize, format_val);
2324
2325         if (bufsize != azx_dev->bufsize ||
2326             period_bytes != azx_dev->period_bytes ||
2327             format_val != azx_dev->format_val ||
2328             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2329                 azx_dev->bufsize = bufsize;
2330                 azx_dev->period_bytes = period_bytes;
2331                 azx_dev->format_val = format_val;
2332                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2333                 err = azx_setup_periods(chip, substream, azx_dev);
2334                 if (err < 0)
2335                         goto unlock;
2336         }
2337
2338         /* wallclk has 24Mhz clock source */
2339         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2340                                                 runtime->rate) * 1000);
2341         azx_setup_controller(chip, azx_dev);
2342         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2343                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2344         else
2345                 azx_dev->fifo_size = 0;
2346
2347         stream_tag = azx_dev->stream_tag;
2348         /* CA-IBG chips need the playback stream starting from 1 */
2349         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2350             stream_tag > chip->capture_streams)
2351                 stream_tag -= chip->capture_streams;
2352         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2353                                      azx_dev->format_val, substream);
2354
2355  unlock:
2356         if (!err)
2357                 azx_dev->prepared = 1;
2358         dsp_unlock(azx_dev);
2359         return err;
2360 }
2361
2362 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2363 {
2364         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2365         struct azx *chip = apcm->chip;
2366         struct azx_dev *azx_dev;
2367         struct snd_pcm_substream *s;
2368         int rstart = 0, start, nsync = 0, sbits = 0;
2369         int nwait, timeout;
2370
2371         azx_dev = get_azx_dev(substream);
2372         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2373
2374         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2375                 return -EPIPE;
2376
2377         switch (cmd) {
2378         case SNDRV_PCM_TRIGGER_START:
2379                 rstart = 1;
2380         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2381         case SNDRV_PCM_TRIGGER_RESUME:
2382                 start = 1;
2383                 break;
2384         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2385         case SNDRV_PCM_TRIGGER_SUSPEND:
2386         case SNDRV_PCM_TRIGGER_STOP:
2387                 start = 0;
2388                 break;
2389         default:
2390                 return -EINVAL;
2391         }
2392
2393         snd_pcm_group_for_each_entry(s, substream) {
2394                 if (s->pcm->card != substream->pcm->card)
2395                         continue;
2396                 azx_dev = get_azx_dev(s);
2397                 sbits |= 1 << azx_dev->index;
2398                 nsync++;
2399                 snd_pcm_trigger_done(s, substream);
2400         }
2401
2402         spin_lock(&chip->reg_lock);
2403
2404         /* first, set SYNC bits of corresponding streams */
2405         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2406                 azx_writel(chip, OLD_SSYNC,
2407                         azx_readl(chip, OLD_SSYNC) | sbits);
2408         else
2409                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2410
2411         snd_pcm_group_for_each_entry(s, substream) {
2412                 if (s->pcm->card != substream->pcm->card)
2413                         continue;
2414                 azx_dev = get_azx_dev(s);
2415                 if (start) {
2416                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2417                         if (!rstart)
2418                                 azx_dev->start_wallclk -=
2419                                                 azx_dev->period_wallclk;
2420                         azx_stream_start(chip, azx_dev);
2421                 } else {
2422                         azx_stream_stop(chip, azx_dev);
2423                 }
2424                 azx_dev->running = start;
2425         }
2426         spin_unlock(&chip->reg_lock);
2427         if (start) {
2428                 /* wait until all FIFOs get ready */
2429                 for (timeout = 5000; timeout; timeout--) {
2430                         nwait = 0;
2431                         snd_pcm_group_for_each_entry(s, substream) {
2432                                 if (s->pcm->card != substream->pcm->card)
2433                                         continue;
2434                                 azx_dev = get_azx_dev(s);
2435                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2436                                       SD_STS_FIFO_READY))
2437                                         nwait++;
2438                         }
2439                         if (!nwait)
2440                                 break;
2441                         cpu_relax();
2442                 }
2443         } else {
2444                 /* wait until all RUN bits are cleared */
2445                 for (timeout = 5000; timeout; timeout--) {
2446                         nwait = 0;
2447                         snd_pcm_group_for_each_entry(s, substream) {
2448                                 if (s->pcm->card != substream->pcm->card)
2449                                         continue;
2450                                 azx_dev = get_azx_dev(s);
2451                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2452                                     SD_CTL_DMA_START)
2453                                         nwait++;
2454                         }
2455                         if (!nwait)
2456                                 break;
2457                         cpu_relax();
2458                 }
2459         }
2460         spin_lock(&chip->reg_lock);
2461         /* reset SYNC bits */
2462         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2463                 azx_writel(chip, OLD_SSYNC,
2464                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2465         else
2466                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2467         if (start) {
2468                 azx_timecounter_init(substream, 0, 0);
2469                 if (nsync > 1) {
2470                         cycle_t cycle_last;
2471
2472                         /* same start cycle for master and group */
2473                         azx_dev = get_azx_dev(substream);
2474                         cycle_last = azx_dev->azx_tc.cycle_last;
2475
2476                         snd_pcm_group_for_each_entry(s, substream) {
2477                                 if (s->pcm->card != substream->pcm->card)
2478                                         continue;
2479                                 azx_timecounter_init(s, 1, cycle_last);
2480                         }
2481                 }
2482         }
2483         spin_unlock(&chip->reg_lock);
2484         return 0;
2485 }
2486
2487 /* get the current DMA position with correction on VIA chips */
2488 static unsigned int azx_via_get_position(struct azx *chip,
2489                                          struct azx_dev *azx_dev)
2490 {
2491         unsigned int link_pos, mini_pos, bound_pos;
2492         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2493         unsigned int fifo_size;
2494
2495         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2496         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2497                 /* Playback, no problem using link position */
2498                 return link_pos;
2499         }
2500
2501         /* Capture */
2502         /* For new chipset,
2503          * use mod to get the DMA position just like old chipset
2504          */
2505         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2506         mod_dma_pos %= azx_dev->period_bytes;
2507
2508         /* azx_dev->fifo_size can't get FIFO size of in stream.
2509          * Get from base address + offset.
2510          */
2511         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2512
2513         if (azx_dev->insufficient) {
2514                 /* Link position never gather than FIFO size */
2515                 if (link_pos <= fifo_size)
2516                         return 0;
2517
2518                 azx_dev->insufficient = 0;
2519         }
2520
2521         if (link_pos <= fifo_size)
2522                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2523         else
2524                 mini_pos = link_pos - fifo_size;
2525
2526         /* Find nearest previous boudary */
2527         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2528         mod_link_pos = link_pos % azx_dev->period_bytes;
2529         if (mod_link_pos >= fifo_size)
2530                 bound_pos = link_pos - mod_link_pos;
2531         else if (mod_dma_pos >= mod_mini_pos)
2532                 bound_pos = mini_pos - mod_mini_pos;
2533         else {
2534                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2535                 if (bound_pos >= azx_dev->bufsize)
2536                         bound_pos = 0;
2537         }
2538
2539         /* Calculate real DMA position we want */
2540         return bound_pos + mod_dma_pos;
2541 }
2542
2543 static unsigned int azx_get_position(struct azx *chip,
2544                                      struct azx_dev *azx_dev,
2545                                      bool with_check)
2546 {
2547         struct snd_pcm_substream *substream = azx_dev->substream;
2548         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2549         unsigned int pos;
2550         int stream = substream->stream;
2551         struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2552         int delay = 0;
2553
2554         switch (chip->position_fix[stream]) {
2555         case POS_FIX_LPIB:
2556                 /* read LPIB */
2557                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2558                 break;
2559         case POS_FIX_VIACOMBO:
2560                 pos = azx_via_get_position(chip, azx_dev);
2561                 break;
2562         default:
2563                 /* use the position buffer */
2564                 pos = le32_to_cpu(*azx_dev->posbuf);
2565                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2566                         if (!pos || pos == (u32)-1) {
2567                                 printk(KERN_WARNING
2568                                        "hda-intel: Invalid position buffer, "
2569                                        "using LPIB read method instead.\n");
2570                                 chip->position_fix[stream] = POS_FIX_LPIB;
2571                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2572                         } else
2573                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2574                 }
2575                 break;
2576         }
2577
2578         if (pos >= azx_dev->bufsize)
2579                 pos = 0;
2580
2581         /* calculate runtime delay from LPIB */
2582         if (substream->runtime &&
2583             chip->position_fix[stream] == POS_FIX_POSBUF &&
2584             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2585                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2586                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2587                         delay = pos - lpib_pos;
2588                 else
2589                         delay = lpib_pos - pos;
2590                 if (delay < 0)
2591                         delay += azx_dev->bufsize;
2592                 if (delay >= azx_dev->period_bytes) {
2593                         snd_printk(KERN_WARNING SFX
2594                                    "%s: Unstable LPIB (%d >= %d); "
2595                                    "disabling LPIB delay counting\n",
2596                                    pci_name(chip->pci), delay, azx_dev->period_bytes);
2597                         delay = 0;
2598                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2599                 }
2600                 delay = bytes_to_frames(substream->runtime, delay);
2601         }
2602
2603         if (substream->runtime) {
2604                 if (hinfo->ops.get_delay)
2605                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2606                                                       substream);
2607                 substream->runtime->delay = delay;
2608         }
2609
2610         trace_azx_get_position(chip, azx_dev, pos, delay);
2611         return pos;
2612 }
2613
2614 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2615 {
2616         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2617         struct azx *chip = apcm->chip;
2618         struct azx_dev *azx_dev = get_azx_dev(substream);
2619         return bytes_to_frames(substream->runtime,
2620                                azx_get_position(chip, azx_dev, false));
2621 }
2622
2623 /*
2624  * Check whether the current DMA position is acceptable for updating
2625  * periods.  Returns non-zero if it's OK.
2626  *
2627  * Many HD-audio controllers appear pretty inaccurate about
2628  * the update-IRQ timing.  The IRQ is issued before actually the
2629  * data is processed.  So, we need to process it afterwords in a
2630  * workqueue.
2631  */
2632 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2633 {
2634         u32 wallclk;
2635         unsigned int pos;
2636
2637         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2638         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2639                 return -1;      /* bogus (too early) interrupt */
2640
2641         pos = azx_get_position(chip, azx_dev, true);
2642
2643         if (WARN_ONCE(!azx_dev->period_bytes,
2644                       "hda-intel: zero azx_dev->period_bytes"))
2645                 return -1; /* this shouldn't happen! */
2646         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2647             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2648                 /* NG - it's below the first next period boundary */
2649                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2650         azx_dev->start_wallclk += wallclk;
2651         return 1; /* OK, it's fine */
2652 }
2653
2654 /*
2655  * The work for pending PCM period updates.
2656  */
2657 static void azx_irq_pending_work(struct work_struct *work)
2658 {
2659         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2660         int i, pending, ok;
2661
2662         if (!chip->irq_pending_warned) {
2663                 printk(KERN_WARNING
2664                        "hda-intel: IRQ timing workaround is activated "
2665                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2666                        chip->card->number);
2667                 chip->irq_pending_warned = 1;
2668         }
2669
2670         for (;;) {
2671                 pending = 0;
2672                 spin_lock_irq(&chip->reg_lock);
2673                 for (i = 0; i < chip->num_streams; i++) {
2674                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2675                         if (!azx_dev->irq_pending ||
2676                             !azx_dev->substream ||
2677                             !azx_dev->running)
2678                                 continue;
2679                         ok = azx_position_ok(chip, azx_dev);
2680                         if (ok > 0) {
2681                                 azx_dev->irq_pending = 0;
2682                                 spin_unlock(&chip->reg_lock);
2683                                 snd_pcm_period_elapsed(azx_dev->substream);
2684                                 spin_lock(&chip->reg_lock);
2685                         } else if (ok < 0) {
2686                                 pending = 0;    /* too early */
2687                         } else
2688                                 pending++;
2689                 }
2690                 spin_unlock_irq(&chip->reg_lock);
2691                 if (!pending)
2692                         return;
2693                 msleep(1);
2694         }
2695 }
2696
2697 /* clear irq_pending flags and assure no on-going workq */
2698 static void azx_clear_irq_pending(struct azx *chip)
2699 {
2700         int i;
2701
2702         spin_lock_irq(&chip->reg_lock);
2703         for (i = 0; i < chip->num_streams; i++)
2704                 chip->azx_dev[i].irq_pending = 0;
2705         spin_unlock_irq(&chip->reg_lock);
2706 }
2707
2708 #ifdef CONFIG_X86
2709 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2710                         struct vm_area_struct *area)
2711 {
2712         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2713         struct azx *chip = apcm->chip;
2714         if (!azx_snoop(chip))
2715                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2716         return snd_pcm_lib_default_mmap(substream, area);
2717 }
2718 #else
2719 #define azx_pcm_mmap    NULL
2720 #endif
2721
2722 static struct snd_pcm_ops azx_pcm_ops = {
2723         .open = azx_pcm_open,
2724         .close = azx_pcm_close,
2725         .ioctl = snd_pcm_lib_ioctl,
2726         .hw_params = azx_pcm_hw_params,
2727         .hw_free = azx_pcm_hw_free,
2728         .prepare = azx_pcm_prepare,
2729         .trigger = azx_pcm_trigger,
2730         .pointer = azx_pcm_pointer,
2731         .wall_clock =  azx_get_wallclock_tstamp,
2732         .mmap = azx_pcm_mmap,
2733         .page = snd_pcm_sgbuf_ops_page,
2734 };
2735
2736 static void azx_pcm_free(struct snd_pcm *pcm)
2737 {
2738         struct azx_pcm *apcm = pcm->private_data;
2739         if (apcm) {
2740                 list_del(&apcm->list);
2741                 kfree(apcm);
2742         }
2743 }
2744
2745 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2746
2747 static int
2748 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2749                       struct hda_pcm *cpcm)
2750 {
2751         struct azx *chip = bus->private_data;
2752         struct snd_pcm *pcm;
2753         struct azx_pcm *apcm;
2754         int pcm_dev = cpcm->device;
2755         unsigned int size;
2756         int s, err;
2757
2758         list_for_each_entry(apcm, &chip->pcm_list, list) {
2759                 if (apcm->pcm->device == pcm_dev) {
2760                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2761                                    pci_name(chip->pci), pcm_dev);
2762                         return -EBUSY;
2763                 }
2764         }
2765         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2766                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2767                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2768                           &pcm);
2769         if (err < 0)
2770                 return err;
2771         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2772         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2773         if (apcm == NULL)
2774                 return -ENOMEM;
2775         apcm->chip = chip;
2776         apcm->pcm = pcm;
2777         apcm->codec = codec;
2778         pcm->private_data = apcm;
2779         pcm->private_free = azx_pcm_free;
2780         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2781                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2782         list_add_tail(&apcm->list, &chip->pcm_list);
2783         cpcm->pcm = pcm;
2784         for (s = 0; s < 2; s++) {
2785                 apcm->hinfo[s] = &cpcm->stream[s];
2786                 if (cpcm->stream[s].substreams)
2787                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2788         }
2789         /* buffer pre-allocation */
2790         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2791         if (size > MAX_PREALLOC_SIZE)
2792                 size = MAX_PREALLOC_SIZE;
2793 #ifdef CONFIG_SND_HDA_VPR
2794         chip->hda_vpr = nvmap_create_client(nvmap_dev, "hda_vpr");
2795         for (s = 0; s < 2; s++) {
2796                 struct snd_pcm_substream *substream;
2797                 for (substream = pcm->streams[s].substream;
2798                   substream; substream = substream->next) {
2799                         chip->handle_ref = nvmap_alloc(chip->hda_vpr, size, 32,
2800                           NVMAP_HANDLE_WRITE_COMBINE, NVMAP_HEAP_CARVEOUT_VPR);
2801                         chip->vaddr =
2802                           (unsigned char *) nvmap_mmap(chip->handle_ref);
2803                         chip->paddr =
2804                           nvmap_pin(chip->hda_vpr, chip->handle_ref);
2805                         snd_printk(KERN_DEBUG SFX
2806                           "paddr=%08x vaddr=%08x\n", chip->paddr, chip->vaddr);
2807                         substream->dma_buffer.area = chip->vaddr;
2808                         substream->dma_buffer.addr = chip->paddr;
2809                         substream->dma_buffer.bytes = size;
2810                         substream->dma_buffer.dev.dev = chip->dev;
2811                         if (substream->dma_buffer.bytes > 0)
2812                                 substream->buffer_bytes_max =
2813                                    substream->dma_buffer.bytes;
2814                         substream->dma_max = MAX_PREALLOC_SIZE;
2815                 }
2816         }
2817 #else
2818         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2819                                               chip->dev,
2820                                               size, MAX_PREALLOC_SIZE);
2821 #endif
2822         return 0;
2823 }
2824
2825 /*
2826  * mixer creation - all stuff is implemented in hda module
2827  */
2828 static int azx_mixer_create(struct azx *chip)
2829 {
2830         return snd_hda_build_controls(chip->bus);
2831 }
2832
2833
2834 /*
2835  * initialize SD streams
2836  */
2837 static int azx_init_stream(struct azx *chip)
2838 {
2839         int i;
2840
2841         /* initialize each stream (aka device)
2842          * assign the starting bdl address to each stream (device)
2843          * and initialize
2844          */
2845         for (i = 0; i < chip->num_streams; i++) {
2846                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2847                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2848                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2849                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2850                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2851                 azx_dev->sd_int_sta_mask = 1 << i;
2852                 /* stream tag: must be non-zero and unique */
2853                 azx_dev->index = i;
2854                 azx_dev->stream_tag = i + 1;
2855         }
2856
2857         return 0;
2858 }
2859
2860 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2861 {
2862         if (request_irq(chip->irq_id, azx_interrupt,
2863                         chip->msi ? 0 : IRQF_SHARED,
2864                         KBUILD_MODNAME, chip)) {
2865                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2866                        "disabling device\n", chip->irq_id);
2867                 if (do_disconnect)
2868                         snd_card_disconnect(chip->card);
2869                 return -1;
2870         }
2871         chip->irq = chip->irq_id;
2872         if (chip->pci)
2873                 pci_intx(chip->pci, !chip->msi);
2874
2875         return 0;
2876 }
2877
2878
2879 static void azx_stop_chip(struct azx *chip)
2880 {
2881         if (!chip->initialized)
2882                 return;
2883
2884         /* disable interrupts */
2885         azx_int_disable(chip);
2886         azx_int_clear(chip);
2887
2888         /* disable CORB/RIRB */
2889         azx_free_cmd_io(chip);
2890
2891         /* disable position buffer */
2892         azx_writel(chip, DPLBASE, 0);
2893         azx_writel(chip, DPUBASE, 0);
2894
2895         chip->initialized = 0;
2896 }
2897
2898 #ifdef CONFIG_SND_HDA_DSP_LOADER
2899 /*
2900  * DSP loading code (e.g. for CA0132)
2901  */
2902
2903 /* use the first stream for loading DSP */
2904 static struct azx_dev *
2905 azx_get_dsp_loader_dev(struct azx *chip)
2906 {
2907         return &chip->azx_dev[chip->playback_index_offset];
2908 }
2909
2910 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2911                                 unsigned int byte_size,
2912                                 struct snd_dma_buffer *bufp)
2913 {
2914         u32 *bdl;
2915         struct azx *chip = bus->private_data;
2916         struct azx_dev *azx_dev;
2917         int err;
2918
2919         azx_dev = azx_get_dsp_loader_dev(chip);
2920
2921         dsp_lock(azx_dev);
2922         spin_lock_irq(&chip->reg_lock);
2923         if (azx_dev->running || azx_dev->locked) {
2924                 spin_unlock_irq(&chip->reg_lock);
2925                 err = -EBUSY;
2926                 goto unlock;
2927         }
2928         azx_dev->prepared = 0;
2929         chip->saved_azx_dev = *azx_dev;
2930         azx_dev->locked = 1;
2931         spin_unlock_irq(&chip->reg_lock);
2932
2933         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2934                                   snd_dma_pci_data(chip->pci),
2935                                   byte_size, bufp);
2936         if (err < 0)
2937                 goto err_alloc;
2938
2939         mark_pages_wc(chip, bufp, true);
2940         azx_dev->bufsize = byte_size;
2941         azx_dev->period_bytes = byte_size;
2942         azx_dev->format_val = format;
2943
2944         azx_stream_reset(chip, azx_dev);
2945
2946         /* reset BDL address */
2947         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2948         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2949
2950         azx_dev->frags = 0;
2951         bdl = (u32 *)azx_dev->bdl.area;
2952         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2953         if (err < 0)
2954                 goto error;
2955
2956         azx_setup_controller(chip, azx_dev);
2957         dsp_unlock(azx_dev);
2958         return azx_dev->stream_tag;
2959
2960  error:
2961         mark_pages_wc(chip, bufp, false);
2962         snd_dma_free_pages(bufp);
2963  err_alloc:
2964         spin_lock_irq(&chip->reg_lock);
2965         if (azx_dev->opened)
2966                 *azx_dev = chip->saved_azx_dev;
2967         azx_dev->locked = 0;
2968         spin_unlock_irq(&chip->reg_lock);
2969  unlock:
2970         dsp_unlock(azx_dev);
2971         return err;
2972 }
2973
2974 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2975 {
2976         struct azx *chip = bus->private_data;
2977         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2978
2979         if (start)
2980                 azx_stream_start(chip, azx_dev);
2981         else
2982                 azx_stream_stop(chip, azx_dev);
2983         azx_dev->running = start;
2984 }
2985
2986 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2987                                  struct snd_dma_buffer *dmab)
2988 {
2989         struct azx *chip = bus->private_data;
2990         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2991
2992         if (!dmab->area || !azx_dev->locked)
2993                 return;
2994
2995         dsp_lock(azx_dev);
2996         /* reset BDL address */
2997         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2998         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2999         azx_sd_writel(azx_dev, SD_CTL, 0);
3000         azx_dev->bufsize = 0;
3001         azx_dev->period_bytes = 0;
3002         azx_dev->format_val = 0;
3003
3004         mark_pages_wc(chip, dmab, false);
3005         snd_dma_free_pages(dmab);
3006         dmab->area = NULL;
3007
3008         spin_lock_irq(&chip->reg_lock);
3009         if (azx_dev->opened)
3010                 *azx_dev = chip->saved_azx_dev;
3011         azx_dev->locked = 0;
3012         spin_unlock_irq(&chip->reg_lock);
3013         dsp_unlock(azx_dev);
3014 }
3015 #endif /* CONFIG_SND_HDA_DSP_LOADER */
3016
3017 #ifdef CONFIG_PM
3018 /* power-up/down the controller */
3019 static void azx_power_notify(struct hda_bus *bus, bool power_up)
3020 {
3021         struct azx *chip = bus->private_data;
3022
3023         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3024                 return;
3025
3026         if (power_up)
3027                 pm_runtime_get_sync(&chip->pci->dev);
3028         else
3029                 pm_runtime_put_sync(&chip->pci->dev);
3030 }
3031
3032 static DEFINE_MUTEX(card_list_lock);
3033 static LIST_HEAD(card_list);
3034
3035 static void azx_add_card_list(struct azx *chip)
3036 {
3037         mutex_lock(&card_list_lock);
3038         list_add(&chip->list, &card_list);
3039         mutex_unlock(&card_list_lock);
3040 }
3041
3042 static void azx_del_card_list(struct azx *chip)
3043 {
3044         mutex_lock(&card_list_lock);
3045         list_del_init(&chip->list);
3046         mutex_unlock(&card_list_lock);
3047 }
3048
3049 /* trigger power-save check at writing parameter */
3050 static int param_set_xint(const char *val, const struct kernel_param *kp)
3051 {
3052         struct azx *chip;
3053         struct hda_codec *c;
3054         int prev = power_save;
3055         int ret = param_set_int(val, kp);
3056
3057         if (ret || prev == power_save)
3058                 return ret;
3059
3060         mutex_lock(&card_list_lock);
3061         list_for_each_entry(chip, &card_list, list) {
3062                 if (!chip->bus || chip->disabled)
3063                         continue;
3064                 list_for_each_entry(c, &chip->bus->codec_list, list)
3065                         snd_hda_power_sync(c);
3066         }
3067         mutex_unlock(&card_list_lock);
3068         return 0;
3069 }
3070 #else
3071 #define azx_add_card_list(chip) /* NOP */
3072 #define azx_del_card_list(chip) /* NOP */
3073 #endif /* CONFIG_PM */
3074
3075 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
3076 /*
3077  * power management
3078  */
3079 static int azx_suspend(struct device *dev)
3080 {
3081         struct snd_card *card = dev_get_drvdata(dev);
3082         struct azx *chip = card->private_data;
3083         struct azx_pcm *p;
3084
3085         if (chip->disabled)
3086                 return 0;
3087
3088 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
3089         defined(CONFIG_SND_HDA_POWER_SAVE)
3090         if (chip->pdev)
3091                 azx_platform_enable_clocks(chip);
3092 #endif
3093
3094         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3095         azx_clear_irq_pending(chip);
3096         list_for_each_entry(p, &chip->pcm_list, list)
3097                 snd_pcm_suspend_all(p->pcm);
3098         if (chip->initialized)
3099                 snd_hda_suspend(chip->bus);
3100         azx_stop_chip(chip);
3101         if (chip->irq >= 0) {
3102                 free_irq(chip->irq, chip);
3103                 chip->irq = -1;
3104         }
3105
3106         if (chip->pci) {
3107                 if (chip->msi)
3108                         pci_disable_msi(chip->pci);
3109                 pci_disable_device(chip->pci);
3110                 pci_save_state(chip->pci);
3111                 pci_set_power_state(pci, PCI_D3hot);
3112         }
3113
3114 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3115         if (chip->pdev) {
3116                 /* Disable all clk references */
3117                 while (chip->platform_clk_enable)
3118                         azx_platform_disable_clocks(chip);
3119         }
3120 #endif
3121
3122         return 0;
3123 }
3124
3125 static int azx_resume(struct device *dev)
3126 {
3127         struct snd_card *card = dev_get_drvdata(dev);
3128         struct azx *chip = card->private_data;
3129
3130         if (chip->disabled)
3131                 return 0;
3132
3133 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3134         if (chip->pdev)
3135                 azx_platform_enable_clocks(chip);
3136 #endif
3137
3138         if (chip->pci) {
3139                 pci_set_power_state(chip->pci, PCI_D0);
3140                 pci_restore_state(chip->pci);
3141                 if (pci_enable_device(chip->pci) < 0) {
3142                         printk(KERN_ERR "hda-intel: pci_enable_device failed, "
3143                                "disabling device\n");
3144                         snd_card_disconnect(card);
3145                         return -EIO;
3146                 }
3147                 pci_set_master(chip->pci);
3148                 if (chip->msi)
3149                         if (pci_enable_msi(chip->pci) < 0)
3150                                 chip->msi = 0;
3151         }
3152
3153         if (azx_acquire_irq(chip, 1) < 0)
3154                 return -EIO;
3155
3156         if (chip->pci)
3157                 azx_init_pci(chip);
3158
3159 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3160         if (chip->pdev)
3161                 azx_init_platform(chip);
3162 #endif
3163
3164         azx_init_chip(chip, 1);
3165
3166         snd_hda_resume(chip->bus);
3167         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3168
3169 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
3170         defined(CONFIG_SND_HDA_POWER_SAVE)
3171         if (chip->pdev)
3172                 azx_platform_disable_clocks(chip);
3173 #endif
3174
3175         return 0;
3176 }
3177 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
3178
3179 #ifdef CONFIG_PM_RUNTIME
3180 static int azx_runtime_suspend(struct device *dev)
3181 {
3182         struct snd_card *card = dev_get_drvdata(dev);
3183         struct azx *chip = card->private_data;
3184
3185         azx_stop_chip(chip);
3186 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3187         azx_platform_disable_clocks(chip);
3188 #endif
3189         azx_clear_irq_pending(chip);
3190         return 0;
3191 }
3192
3193 static int azx_runtime_resume(struct device *dev)
3194 {
3195         struct snd_card *card = dev_get_drvdata(dev);
3196         struct azx *chip = card->private_data;
3197
3198         azx_init_pci(chip);
3199 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3200         azx_platform_enable_clocks(chip);
3201 #endif
3202         azx_init_chip(chip, 1);
3203         return 0;
3204 }
3205
3206 static int azx_runtime_idle(struct device *dev)
3207 {
3208         struct snd_card *card = dev_get_drvdata(dev);
3209         struct azx *chip = card->private_data;
3210
3211         if (!power_save_controller ||
3212             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3213                 return -EBUSY;
3214
3215         return 0;
3216 }
3217
3218 #endif /* CONFIG_PM_RUNTIME */
3219
3220 #ifdef CONFIG_PM
3221 static const struct dev_pm_ops azx_pm = {
3222         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3223         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
3224 };
3225
3226 #define AZX_PM_OPS      &azx_pm
3227 #else
3228 #define AZX_PM_OPS      NULL
3229 #endif /* CONFIG_PM */
3230
3231
3232 /*
3233  * reboot notifier for hang-up problem at power-down
3234  */
3235 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3236 {
3237         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
3238
3239 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
3240         defined(CONFIG_SND_HDA_POWER_SAVE)
3241         if (chip->pdev)
3242                 azx_platform_enable_clocks(chip);
3243 #endif
3244
3245         snd_hda_bus_reboot_notify(chip->bus);
3246         azx_stop_chip(chip);
3247
3248 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
3249         defined(CONFIG_SND_HDA_POWER_SAVE)
3250         if (chip->pdev)
3251                 azx_platform_disable_clocks(chip);
3252 #endif
3253
3254         return NOTIFY_OK;
3255 }
3256
3257 static void azx_notifier_register(struct azx *chip)
3258 {
3259         chip->reboot_notifier.notifier_call = azx_halt;
3260         register_reboot_notifier(&chip->reboot_notifier);
3261 }
3262
3263 static void azx_notifier_unregister(struct azx *chip)
3264 {
3265         if (chip->reboot_notifier.notifier_call)
3266                 unregister_reboot_notifier(&chip->reboot_notifier);
3267 }
3268
3269 static int azx_first_init(struct azx *chip);
3270 static int azx_probe_continue(struct azx *chip);
3271
3272 #ifdef SUPPORT_VGA_SWITCHEROO
3273 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
3274
3275 static void azx_vs_set_state(struct pci_dev *pci,
3276                              enum vga_switcheroo_state state)
3277 {
3278         struct snd_card *card = pci_get_drvdata(pci);
3279         struct azx *chip = card->private_data;
3280         bool disabled;
3281
3282         wait_for_completion(&chip->probe_wait);
3283         if (chip->init_failed)
3284                 return;
3285
3286         disabled = (state == VGA_SWITCHEROO_OFF);
3287         if (chip->disabled == disabled)
3288                 return;
3289
3290         if (!chip->bus) {
3291                 chip->disabled = disabled;
3292                 if (!disabled) {
3293                         snd_printk(KERN_INFO SFX
3294                                    "%s: Start delayed initialization\n",
3295                                    pci_name(chip->pci));
3296                         if (azx_first_init(chip) < 0 ||
3297                             azx_probe_continue(chip) < 0) {
3298                                 snd_printk(KERN_ERR SFX
3299                                            "%s: initialization error\n",
3300                                            pci_name(chip->pci));
3301                                 chip->init_failed = true;
3302                         }
3303                 }
3304         } else {
3305                 snd_printk(KERN_INFO SFX
3306                            "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3307                            disabled ? "Disabling" : "Enabling");
3308                 if (disabled) {
3309                         azx_suspend(&pci->dev);
3310                         chip->disabled = true;
3311                         if (snd_hda_lock_devices(chip->bus))
3312                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3313                                            pci_name(chip->pci));
3314                 } else {
3315                         snd_hda_unlock_devices(chip->bus);
3316                         chip->disabled = false;
3317                         azx_resume(&pci->dev);
3318                 }
3319         }
3320 }
3321
3322 static bool azx_vs_can_switch(struct pci_dev *pci)
3323 {
3324         struct snd_card *card = pci_get_drvdata(pci);
3325         struct azx *chip = card->private_data;
3326
3327         wait_for_completion(&chip->probe_wait);
3328         if (chip->init_failed)
3329                 return false;
3330         if (chip->disabled || !chip->bus)
3331                 return true;
3332         if (snd_hda_lock_devices(chip->bus))
3333                 return false;
3334         snd_hda_unlock_devices(chip->bus);
3335         return true;
3336 }
3337
3338 static void init_vga_switcheroo(struct azx *chip)
3339 {
3340         struct pci_dev *p = get_bound_vga(chip->pci);
3341         if (p) {
3342                 snd_printk(KERN_INFO SFX
3343                            "%s: Handle VGA-switcheroo audio client\n",
3344                            pci_name(chip->pci));
3345                 chip->use_vga_switcheroo = 1;
3346                 pci_dev_put(p);
3347         }
3348 }
3349
3350 static const struct vga_switcheroo_client_ops azx_vs_ops = {
3351         .set_gpu_state = azx_vs_set_state,
3352         .can_switch = azx_vs_can_switch,
3353 };
3354
3355 static int register_vga_switcheroo(struct azx *chip)
3356 {
3357         int err;
3358
3359         if (!chip->use_vga_switcheroo)
3360                 return 0;
3361         /* FIXME: currently only handling DIS controller
3362          * is there any machine with two switchable HDMI audio controllers?
3363          */
3364         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3365                                                     VGA_SWITCHEROO_DIS,
3366                                                     chip->bus != NULL);
3367         if (err < 0)
3368                 return err;
3369         chip->vga_switcheroo_registered = 1;
3370         return 0;
3371 }
3372 #else
3373 #define init_vga_switcheroo(chip)               /* NOP */
3374 #define register_vga_switcheroo(chip)           0
3375 #define check_hdmi_disabled(pci)        false
3376 #endif /* SUPPORT_VGA_SWITCHER */
3377
3378 /*
3379  * destructor
3380  */
3381 static int azx_free(struct azx *chip)
3382 {
3383         int i;
3384
3385         azx_del_card_list(chip);
3386
3387         azx_notifier_unregister(chip);
3388
3389         chip->init_failed = 1; /* to be sure */
3390         complete_all(&chip->probe_wait);
3391
3392         if (use_vga_switcheroo(chip)) {
3393                 if (chip->disabled && chip->bus)
3394                         snd_hda_unlock_devices(chip->bus);
3395                 if (chip->vga_switcheroo_registered)
3396                         vga_switcheroo_unregister_client(chip->pci);
3397         }
3398
3399         if (chip->initialized) {
3400                 azx_clear_irq_pending(chip);
3401                 for (i = 0; i < chip->num_streams; i++)
3402                         azx_stream_stop(chip, &chip->azx_dev[i]);
3403                 azx_stop_chip(chip);
3404         }
3405
3406 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3407         azx_platform_disable_clocks(chip);
3408         for (i = 0; i < chip->platform_clk_count; i++)
3409                 clk_put(chip->platform_clks[i]);
3410 #endif
3411
3412         if (chip->irq >= 0)
3413                 free_irq(chip->irq, (void*)chip);
3414         if (chip->pci && chip->msi)
3415                 pci_disable_msi(chip->pci);
3416         if (chip->remap_addr)
3417                 iounmap(chip->remap_addr);
3418
3419         if (chip->azx_dev) {
3420                 for (i = 0; i < chip->num_streams; i++)
3421                         if (chip->azx_dev[i].bdl.area) {
3422                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
3423                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
3424                         }
3425         }
3426         if (chip->rb.area) {
3427                 mark_pages_wc(chip, &chip->rb, false);
3428                 snd_dma_free_pages(&chip->rb);
3429         }
3430         if (chip->posbuf.area) {
3431                 mark_pages_wc(chip, &chip->posbuf, false);
3432                 snd_dma_free_pages(&chip->posbuf);
3433         }
3434         if (chip->pci) {
3435                 if (chip->region_requested)
3436                         pci_release_regions(chip->pci);
3437                 pci_disable_device(chip->pci);
3438         }
3439         kfree(chip->azx_dev);
3440 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3441         if (chip->fw)
3442                 release_firmware(chip->fw);
3443 #endif
3444         kfree(chip);
3445 #ifdef CONFIG_SND_HDA_VPR
3446         if(chip->handle_ref) {
3447                 nvmap_unpin(chip->hda_vpr, chip->handle_ref);
3448                 nvmap_munmap(chip->handle_ref, chip->vaddr);
3449                 nvmap_free(chip->hda_vpr, chip->handle_ref);
3450         }
3451 #endif
3452
3453         return 0;
3454 }
3455
3456 static int azx_dev_free(struct snd_device *device)
3457 {
3458         return azx_free(device->device_data);
3459 }
3460
3461 #ifdef SUPPORT_VGA_SWITCHEROO
3462 /*
3463  * Check of disabled HDMI controller by vga-switcheroo
3464  */
3465 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3466 {
3467         struct pci_dev *p;
3468
3469         /* check only discrete GPU */
3470         switch (pci->vendor) {
3471         case PCI_VENDOR_ID_ATI:
3472         case PCI_VENDOR_ID_AMD:
3473         case PCI_VENDOR_ID_NVIDIA:
3474                 if (pci->devfn == 1) {
3475                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3476                                                         pci->bus->number, 0);
3477                         if (p) {
3478                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3479                                         return p;
3480                                 pci_dev_put(p);
3481                         }
3482                 }
3483                 break;
3484         }
3485         return NULL;
3486 }
3487
3488 static bool check_hdmi_disabled(struct pci_dev *pci)
3489 {
3490         bool vga_inactive = false;
3491         struct pci_dev *p = get_bound_vga(pci);
3492
3493         if (p) {
3494                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3495                         vga_inactive = true;
3496                 pci_dev_put(p);
3497         }
3498         return vga_inactive;
3499 }
3500 #endif /* SUPPORT_VGA_SWITCHEROO */
3501
3502 /*
3503  * white/black-listing for position_fix
3504  */
3505 static struct snd_pci_quirk position_fix_list[] = {
3506         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3507         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3508         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3509         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3510         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3511         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3512         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3513         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3514         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3515         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3516         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3517         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3518         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3519         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3520         {}
3521 };
3522
3523 static int check_position_fix(struct azx *chip, int fix)
3524 {
3525         const struct snd_pci_quirk *q;
3526
3527         switch (fix) {
3528         case POS_FIX_AUTO:
3529         case POS_FIX_LPIB:
3530         case POS_FIX_POSBUF:
3531         case POS_FIX_VIACOMBO:
3532         case POS_FIX_COMBO:
3533                 return fix;
3534         }
3535
3536         if (chip->pci) {
3537                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3538                 if (q) {
3539                         printk(KERN_INFO
3540                                "hda_intel: position_fix set to %d "
3541                                "for device %04x:%04x\n",
3542                                q->value, q->subvendor, q->subdevice);
3543                         return q->value;
3544                 }
3545         }
3546
3547         /* Check VIA/ATI HD Audio Controller exist */
3548         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3549                 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3550                 return POS_FIX_VIACOMBO;
3551         }
3552         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3553                 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3554                 return POS_FIX_LPIB;
3555         }
3556         return POS_FIX_AUTO;
3557 }
3558
3559 /*
3560  * black-lists for probe_mask
3561  */
3562 static struct snd_pci_quirk probe_mask_list[] = {
3563         /* Thinkpad often breaks the controller communication when accessing
3564          * to the non-working (or non-existing) modem codec slot.
3565          */
3566         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3567         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3568         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3569         /* broken BIOS */
3570         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3571         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3572         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3573         /* forced codec slots */
3574         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3575         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3576         /* WinFast VP200 H (Teradici) user reported broken communication */
3577         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3578         {}
3579 };
3580
3581 #define AZX_FORCE_CODEC_MASK    0x100
3582
3583 static void check_probe_mask(struct azx *chip, int dev)
3584 {
3585         const struct snd_pci_quirk *q;
3586
3587         chip->codec_probe_mask = probe_mask[dev];
3588         if (chip->pci && (chip->codec_probe_mask == -1)) {
3589                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3590                 if (q) {
3591                         printk(KERN_INFO
3592                                "hda_intel: probe_mask set to 0x%x "
3593                                "for device %04x:%04x\n",
3594                                q->value, q->subvendor, q->subdevice);
3595                         chip->codec_probe_mask = q->value;
3596                 }
3597         }
3598
3599         /* check forced option */
3600         if (chip->codec_probe_mask != -1 &&
3601             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3602                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3603                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3604                        chip->codec_mask);
3605         }
3606 }
3607
3608 /*
3609  * white/black-list for enable_msi
3610  */
3611 static struct snd_pci_quirk msi_black_list[] = {
3612         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3613         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3614         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3615         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3616         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3617         {}
3618 };
3619
3620 static void check_msi(struct azx *chip)
3621 {
3622         const struct snd_pci_quirk *q;
3623
3624         /* Disable MSI if chip is not a pci device */
3625         if (!chip->pci) {
3626                 chip->msi = 0;
3627                 return;
3628         }
3629
3630         if (enable_msi >= 0) {
3631                 chip->msi = !!enable_msi;
3632                 return;
3633         }
3634         chip->msi = 1;  /* enable MSI as default */
3635         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3636         if (q) {
3637                 printk(KERN_INFO
3638                        "hda_intel: msi for device %04x:%04x set to %d\n",
3639                        q->subvendor, q->subdevice, q->value);
3640                 chip->msi = q->value;
3641                 return;
3642         }
3643
3644         /* NVidia chipsets seem to cause troubles with MSI */
3645         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3646                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3647                 chip->msi = 0;
3648         }
3649 }
3650
3651 /* check the snoop mode availability */
3652 static void azx_check_snoop_available(struct azx *chip)
3653 {
3654         bool snoop = chip->snoop;
3655
3656         switch (chip->driver_type) {
3657         case AZX_DRIVER_VIA:
3658                 /* force to non-snoop mode for a new VIA controller
3659                  * when BIOS is set
3660                  */
3661                 if (snoop) {
3662                         u8 val;
3663                         pci_read_config_byte(chip->pci, 0x42, &val);
3664                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3665                                 snoop = false;
3666                 }
3667                 break;
3668         case AZX_DRIVER_ATIHDMI_NS:
3669                 /* new ATI HDMI requires non-snoop */
3670                 snoop = false;
3671                 break;
3672         case AZX_DRIVER_CTHDA:
3673                 snoop = false;
3674                 break;
3675         }
3676
3677         if (snoop != chip->snoop) {
3678                 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3679                            pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3680                 chip->snoop = snoop;
3681         }
3682 }
3683
3684 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3685 static const char *tegra_clk_names[] = {
3686         "hda",
3687         "hda2codec",
3688         "hda2hdmi",
3689 };
3690 static struct clk *tegra_clks[ARRAY_SIZE(tegra_clk_names)];
3691 #endif
3692
3693 /*
3694  * constructor
3695  */
3696 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3697                                 struct platform_device *pdev,
3698                                 int dev, unsigned int driver_caps,
3699                                 struct azx **rchip)
3700 {
3701         static struct snd_device_ops ops = {
3702                 .dev_free = azx_dev_free,
3703         };
3704         struct azx *chip;
3705         int err;
3706
3707         *rchip = NULL;
3708
3709         if (pci) {
3710                 err = pci_enable_device(pci);
3711                 if (err < 0)
3712                         return err;
3713         }
3714
3715         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3716         if (!chip) {
3717                 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3718                 if (pci)
3719                         pci_disable_device(pci);
3720                 return -ENOMEM;
3721         }
3722
3723         spin_lock_init(&chip->reg_lock);
3724         mutex_init(&chip->open_mutex);
3725         chip->card = card;
3726         chip->pci = pci;
3727         chip->pdev = pdev;
3728         chip->dev = pci ? snd_dma_pci_data(pci) : &pdev->dev;
3729         chip->irq_id = pci ? pci->irq : platform_get_irq(pdev, 0);
3730         chip->irq = -1;
3731         chip->driver_caps = driver_caps;
3732         chip->driver_type = driver_caps & 0xff;
3733         check_msi(chip);
3734         chip->dev_index = dev;
3735         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3736         INIT_LIST_HEAD(&chip->pcm_list);
3737         INIT_LIST_HEAD(&chip->list);
3738         init_vga_switcheroo(chip);
3739         init_completion(&chip->probe_wait);
3740
3741         chip->position_fix[0] = chip->position_fix[1] =
3742                 check_position_fix(chip, position_fix[dev]);
3743         /* combo mode uses LPIB for playback */
3744         if (chip->position_fix[0] == POS_FIX_COMBO) {
3745                 chip->position_fix[0] = POS_FIX_LPIB;
3746                 chip->position_fix[1] = POS_FIX_AUTO;
3747         }
3748
3749         check_probe_mask(chip, dev);
3750
3751         chip->single_cmd = single_cmd;
3752         chip->snoop = hda_snoop;
3753         azx_check_snoop_available(chip);
3754
3755         if (bdl_pos_adj[dev] < 0) {
3756                 switch (chip->driver_type) {
3757                 case AZX_DRIVER_ICH:
3758                 case AZX_DRIVER_PCH:
3759                         bdl_pos_adj[dev] = 1;
3760                         break;
3761                 default:
3762                         bdl_pos_adj[dev] = 32;
3763                         break;
3764                 }
3765         }
3766
3767         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3768         if (err < 0) {
3769                 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3770                    pci_name(chip->pci));
3771                 azx_free(chip);
3772                 return err;
3773         }
3774
3775         *rchip = chip;
3776         return 0;
3777 }
3778
3779 static int azx_first_init(struct azx *chip)
3780 {
3781         int dev = chip->dev_index;
3782         struct pci_dev *pci = chip->pci;
3783         struct snd_card *card = chip->card;
3784         int i, err = 0;
3785         unsigned short gcap;
3786
3787 #if BITS_PER_LONG != 64
3788         /* Fix up base address on ULI M5461 */
3789         if (chip->driver_type == AZX_DRIVER_ULI) {
3790                 u16 tmp3;
3791                 pci_read_config_word(pci, 0x40, &tmp3);
3792                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3793                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3794         }
3795 #endif
3796
3797         if (chip->pci) {
3798                 err = pci_request_regions(pci, "ICH HD audio");
3799                 if (err < 0)
3800                         return err;
3801                 chip->region_requested = 1;
3802
3803                 chip->addr = pci_resource_start(pci, 0);
3804                 chip->remap_addr = pci_ioremap_bar(pci, 0);
3805                 if (chip->remap_addr == NULL) {
3806                         snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3807                         return -ENXIO;
3808                 }
3809         }
3810
3811 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3812         if (chip->pdev) {
3813                 struct resource *res, *region;
3814
3815                 /* Do platform specific initialization */
3816                 switch (chip->driver_type) {
3817 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3818                 case AZX_DRIVER_NVIDIA_TEGRA:
3819                         chip->platform_clk_count = ARRAY_SIZE(tegra_clk_names);
3820                         for (i = 0; i < chip->platform_clk_count; i++) {
3821                                 tegra_clks[i] = clk_get(&pdev->dev,
3822                                                         tegra_clk_names[i]);
3823                                 if (IS_ERR_OR_NULL(tegra_clks[i])) {
3824                                         err = PTR_ERR(tegra_clks[i]);
3825                                         goto errout;
3826                                 }
3827                         }
3828                         chip->platform_clks = tegra_clks;
3829                         break;
3830 #endif
3831                 default:
3832                         break;
3833                 }
3834
3835                 azx_platform_enable_clocks(chip);
3836
3837                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3838                 if (res == NULL) {
3839                         err = EINVAL;
3840                         goto errout;
3841                 }
3842
3843                 region = devm_request_mem_region(chip->dev, res->start,
3844                                                  resource_size(res),
3845                                                  pdev->name);
3846                 if (!region) {
3847                         snd_printk(KERN_ERR SFX "Mem region already claimed\n");
3848                         err = -EINVAL;
3849                         goto errout;
3850                 }
3851
3852                 chip->addr = res->start;
3853                 chip->remap_addr = devm_ioremap(chip->dev,
3854                                                 res->start,
3855                                                 resource_size(res));
3856                 if (chip->remap_addr == NULL) {
3857                         snd_printk(KERN_ERR SFX "ioremap error\n");
3858                         err = -ENXIO;
3859                         goto errout;
3860                 }
3861
3862 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3863                 if (chip->driver_type == AZX_DRIVER_NVIDIA_TEGRA) {
3864                         chip->remap_config_addr = chip->remap_addr;
3865                         chip->remap_addr += NVIDIA_TEGRA_HDA_BAR0_OFFSET;
3866                         chip->addr += NVIDIA_TEGRA_HDA_BAR0_OFFSET;
3867                 }
3868 #endif
3869
3870                 azx_init_platform(chip);
3871         }
3872 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
3873
3874         if (azx_acquire_irq(chip, 0) < 0)
3875                 return -EBUSY;
3876
3877         if (chip->pci)
3878                 pci_set_master(pci);
3879
3880         synchronize_irq(chip->irq);
3881
3882         gcap = azx_readw(chip, GCAP);
3883         snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3884
3885         /* disable SB600 64bit support for safety */
3886         if (chip->pci && chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3887                 struct pci_dev *p_smbus;
3888                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3889                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3890                                          NULL);
3891                 if (p_smbus) {
3892                         if (p_smbus->revision < 0x30)
3893                                 gcap &= ~ICH6_GCAP_64OK;
3894                         pci_dev_put(p_smbus);
3895                 }
3896         }
3897
3898         /* disable 64bit DMA address on some devices */
3899         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3900                 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3901                 gcap &= ~ICH6_GCAP_64OK;
3902         }
3903
3904         /* disable buffer size rounding to 128-byte multiples if supported */
3905         if (align_buffer_size >= 0)
3906                 chip->align_buffer_size = !!align_buffer_size;
3907         else {
3908                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3909                         chip->align_buffer_size = 0;
3910                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3911                         chip->align_buffer_size = 1;
3912                 else
3913                         chip->align_buffer_size = 1;
3914         }
3915
3916         if (chip->pci) {
3917                 /* allow 64bit DMA address if supported by H/W */
3918                 if ((gcap & ICH6_GCAP_64OK) &&
3919                     !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3920                         pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3921                 else {
3922                         pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3923                         pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3924                 }
3925         }
3926
3927         /* read number of streams from GCAP register instead of using
3928          * hardcoded value
3929          */
3930         chip->capture_streams = (gcap >> 8) & 0x0f;
3931         chip->playback_streams = (gcap >> 12) & 0x0f;
3932         if (!chip->playback_streams && !chip->capture_streams) {
3933                 /* gcap didn't give any info, switching to old method */
3934
3935                 switch (chip->driver_type) {
3936                 case AZX_DRIVER_ULI:
3937                         chip->playback_streams = ULI_NUM_PLAYBACK;
3938                         chip->capture_streams = ULI_NUM_CAPTURE;
3939                         break;
3940                 case AZX_DRIVER_ATIHDMI:
3941                 case AZX_DRIVER_ATIHDMI_NS:
3942                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3943                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3944                         break;
3945                 case AZX_DRIVER_GENERIC:
3946                 default:
3947                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3948                         chip->capture_streams = ICH6_NUM_CAPTURE;
3949                         break;
3950                 }
3951         }
3952         chip->capture_index_offset = 0;
3953         chip->playback_index_offset = chip->capture_streams;
3954         chip->num_streams = chip->playback_streams + chip->capture_streams;
3955         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3956                                 GFP_KERNEL);
3957         if (!chip->azx_dev) {
3958                 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3959                 return -ENOMEM;
3960         }
3961
3962         for (i = 0; i < chip->num_streams; i++) {
3963                 dsp_lock_init(&chip->azx_dev[i]);
3964                 /* allocate memory for the BDL for each stream */
3965                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3966                                           chip->dev,
3967                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3968                 if (err < 0) {
3969                         snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3970                         return -ENOMEM;
3971                 }
3972                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3973         }
3974         /* allocate memory for the position buffer */
3975         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3976                                   chip->dev,
3977                                   chip->num_streams * 8, &chip->posbuf);
3978         if (err < 0) {
3979                 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3980                 return -ENOMEM;
3981         }
3982         mark_pages_wc(chip, &chip->posbuf, true);
3983         /* allocate CORB/RIRB */
3984         err = azx_alloc_cmd_io(chip);
3985         if (err < 0)
3986                 return err;
3987
3988         /* initialize streams */
3989         azx_init_stream(chip);
3990
3991         /* initialize chip */
3992         if (chip->pci)
3993                 azx_init_pci(chip);
3994         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3995
3996         /* codec detection */
3997         if (!chip->codec_mask) {
3998                 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3999                 return -ENODEV;
4000         }
4001
4002         strcpy(card->driver, "HDA-Intel");
4003         strlcpy(card->shortname, driver_short_names[chip->driver_type],
4004                 sizeof(card->shortname));
4005         snprintf(card->longname, sizeof(card->longname),
4006                  "%s at 0x%lx irq %i",
4007                  card->shortname, chip->addr, chip->irq);
4008
4009         return 0;
4010 }
4011
4012 static void power_down_all_codecs(struct azx *chip)
4013 {
4014 #ifdef CONFIG_PM
4015         /* The codecs were powered up in snd_hda_codec_new().
4016          * Now all initialization done, so turn them down if possible
4017          */
4018         struct hda_codec *codec;
4019         list_for_each_entry(codec, &chip->bus->codec_list, list) {
4020                 snd_hda_power_down(codec);
4021         }
4022 #endif
4023 }
4024
4025 #ifdef CONFIG_SND_HDA_PATCH_LOADER
4026 /* callback from request_firmware_nowait() */
4027 static void azx_firmware_cb(const struct firmware *fw, void *context)
4028 {
4029         struct snd_card *card = context;
4030         struct azx *chip = card->private_data;
4031         struct pci_dev *pci = chip->pci;
4032
4033         if (!fw) {
4034                 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
4035                            pci_name(chip->pci));
4036                 goto error;
4037         }
4038
4039         chip->fw = fw;
4040         if (!chip->disabled) {
4041                 /* continue probing */
4042                 if (azx_probe_continue(chip))
4043                         goto error;
4044         }
4045         return; /* OK */
4046
4047  error:
4048         snd_card_free(card);
4049         pci_set_drvdata(pci, NULL);
4050 }
4051 #endif
4052
4053 static int azx_probe(struct pci_dev *pci,
4054                                struct platform_device *pdev,
4055                                int driver_data)
4056 {
4057         static int dev;
4058         struct snd_card *card;
4059         struct azx *chip;
4060         bool probe_now;
4061         struct device *azx_dev = pci ? &pci->dev : &pdev->dev;
4062         int err;
4063
4064         if (dev >= SNDRV_CARDS)
4065                 return -ENODEV;
4066         if (!enable[dev]) {
4067                 dev++;
4068                 return -ENOENT;
4069         }
4070
4071         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
4072         if (err < 0) {
4073                 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
4074                 return err;
4075         }
4076
4077         snd_card_set_dev(card, azx_dev);
4078
4079         err = azx_create(card, pci, pdev, dev, driver_data, &chip);
4080         if (err < 0)
4081                 goto out_free;
4082         card->private_data = chip;
4083
4084         if (pci)
4085                 pci_set_drvdata(pci, card);
4086         else
4087                 dev_set_drvdata(&pdev->dev, card);
4088
4089         err = register_vga_switcheroo(chip);
4090         if (err < 0) {
4091                 snd_printk(KERN_ERR SFX
4092                            "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
4093                 goto out_free;
4094         }
4095
4096         if (check_hdmi_disabled(pci)) {
4097                 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
4098                            pci_name(pci));
4099                 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
4100                 chip->disabled = true;
4101         }
4102
4103         probe_now = !chip->disabled;
4104         if (probe_now) {
4105                 err = azx_first_init(chip);
4106                 if (err < 0)
4107                         goto out_free;
4108         }
4109
4110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
4111         if (patch[dev] && *patch[dev]) {
4112                 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
4113                            pci_name(pci), patch[dev]);
4114                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
4115                                               &pci->dev, GFP_KERNEL, card,
4116                                               azx_firmware_cb);
4117                 if (err < 0)
4118                         goto out_free;
4119                 probe_now = false; /* continued in azx_firmware_cb() */
4120         }
4121 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
4122
4123         if (probe_now) {
4124                 err = azx_probe_continue(chip);
4125                 if (err < 0)
4126                         goto out_free;
4127         }
4128
4129         if (pci_dev_run_wake(pci))
4130                 pm_runtime_put_noidle(&pci->dev);
4131
4132         dev++;
4133         complete_all(&chip->probe_wait);
4134         return 0;
4135
4136 out_free:
4137         snd_card_free(card);
4138         pci_set_drvdata(pci, NULL);
4139         return err;
4140 }
4141
4142 static int azx_probe_continue(struct azx *chip)
4143 {
4144         int dev = chip->dev_index;
4145         int err;
4146
4147 #ifdef CONFIG_SND_HDA_INPUT_BEEP
4148         chip->beep_mode = beep_mode[dev];
4149 #endif
4150
4151         /* create codec instances */
4152         err = azx_codec_create(chip, model[dev]);
4153         if (err < 0)
4154                 goto out_free;
4155 #ifdef CONFIG_SND_HDA_PATCH_LOADER
4156         if (chip->fw) {
4157                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
4158                                          chip->fw->data);
4159                 if (err < 0)
4160                         goto out_free;
4161 #ifndef CONFIG_PM
4162                 release_firmware(chip->fw); /* no longer needed */
4163                 chip->fw = NULL;
4164 #endif
4165         }
4166 #endif
4167         if ((probe_only[dev] & 1) == 0) {
4168                 err = azx_codec_configure(chip);
4169                 if (err < 0)
4170                         goto out_free;
4171         }
4172
4173         /* create PCM streams */
4174         err = snd_hda_build_pcms(chip->bus);
4175         if (err < 0)
4176                 goto out_free;
4177
4178         /* create mixer controls */
4179         err = azx_mixer_create(chip);
4180         if (err < 0)
4181                 goto out_free;
4182
4183         err = snd_card_register(chip->card);
4184         if (err < 0)
4185                 goto out_free;
4186
4187         chip->running = 1;
4188         power_down_all_codecs(chip);
4189         azx_notifier_register(chip);
4190         azx_add_card_list(chip);
4191
4192         return 0;
4193
4194 out_free:
4195         chip->init_failed = 1;
4196         return err;
4197 }
4198
4199 static int azx_probe_pci(struct pci_dev *pci,
4200                                    const struct pci_device_id *pci_id)
4201 {
4202         return azx_probe(pci, NULL, pci_id->driver_data);
4203 }
4204
4205 static void azx_remove_pci(struct pci_dev *pci)
4206 {
4207         struct snd_card *card = pci_get_drvdata(pci);
4208
4209         if (pci_dev_run_wake(pci))
4210                 pm_runtime_get_noresume(&pci->dev);
4211
4212         if (card)
4213                 snd_card_free(card);
4214         pci_set_drvdata(pci, NULL);
4215 }
4216
4217 /* PCI IDs */
4218 static DEFINE_PCI_DEVICE_TABLE(azx_pci_ids) = {
4219         /* CPT */
4220         { PCI_DEVICE(0x8086, 0x1c20),
4221           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
4222         /* PBG */
4223         { PCI_DEVICE(0x8086, 0x1d20),
4224           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
4225         /* Panther Point */
4226         { PCI_DEVICE(0x8086, 0x1e20),
4227           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
4228         /* Lynx Point */
4229         { PCI_DEVICE(0x8086, 0x8c20),
4230           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4231         /* Wellsburg */
4232         { PCI_DEVICE(0x8086, 0x8d20),
4233           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4234         { PCI_DEVICE(0x8086, 0x8d21),
4235           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4236         /* Lynx Point-LP */
4237         { PCI_DEVICE(0x8086, 0x9c20),
4238           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4239         /* Lynx Point-LP */
4240         { PCI_DEVICE(0x8086, 0x9c21),
4241           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4242         /* Haswell */
4243         { PCI_DEVICE(0x8086, 0x0a0c),
4244           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
4245         { PCI_DEVICE(0x8086, 0x0c0c),
4246           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
4247         { PCI_DEVICE(0x8086, 0x0d0c),
4248           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
4249         /* 5 Series/3400 */
4250         { PCI_DEVICE(0x8086, 0x3b56),
4251           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4252         /* Poulsbo */
4253         { PCI_DEVICE(0x8086, 0x811b),
4254           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4255         /* Oaktrail */
4256         { PCI_DEVICE(0x8086, 0x080a),
4257           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4258         /* ICH */
4259         { PCI_DEVICE(0x8086, 0x2668),
4260           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4261           AZX_DCAPS_BUFSIZE },  /* ICH6 */
4262         { PCI_DEVICE(0x8086, 0x27d8),
4263           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4264           AZX_DCAPS_BUFSIZE },  /* ICH7 */
4265         { PCI_DEVICE(0x8086, 0x269a),
4266           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4267           AZX_DCAPS_BUFSIZE },  /* ESB2 */
4268         { PCI_DEVICE(0x8086, 0x284b),
4269           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4270           AZX_DCAPS_BUFSIZE },  /* ICH8 */
4271         { PCI_DEVICE(0x8086, 0x293e),
4272           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4273           AZX_DCAPS_BUFSIZE },  /* ICH9 */
4274         { PCI_DEVICE(0x8086, 0x293f),
4275           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4276           AZX_DCAPS_BUFSIZE },  /* ICH9 */
4277         { PCI_DEVICE(0x8086, 0x3a3e),
4278           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4279           AZX_DCAPS_BUFSIZE },  /* ICH10 */
4280         { PCI_DEVICE(0x8086, 0x3a6e),
4281           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4282           AZX_DCAPS_BUFSIZE },  /* ICH10 */
4283         /* Generic Intel */
4284         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
4285           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4286           .class_mask = 0xffffff,
4287           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
4288         /* ATI SB 450/600/700/800/900 */
4289         { PCI_DEVICE(0x1002, 0x437b),
4290           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4291         { PCI_DEVICE(0x1002, 0x4383),
4292           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4293         /* AMD Hudson */
4294         { PCI_DEVICE(0x1022, 0x780d),
4295           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
4296         /* ATI HDMI */
4297         { PCI_DEVICE(0x1002, 0x793b),
4298           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4299         { PCI_DEVICE(0x1002, 0x7919),
4300           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4301         { PCI_DEVICE(0x1002, 0x960f),
4302           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4303         { PCI_DEVICE(0x1002, 0x970f),
4304           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4305         { PCI_DEVICE(0x1002, 0xaa00),
4306           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4307         { PCI_DEVICE(0x1002, 0xaa08),
4308           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4309         { PCI_DEVICE(0x1002, 0xaa10),
4310           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4311         { PCI_DEVICE(0x1002, 0xaa18),
4312           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4313         { PCI_DEVICE(0x1002, 0xaa20),
4314           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4315         { PCI_DEVICE(0x1002, 0xaa28),
4316           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4317         { PCI_DEVICE(0x1002, 0xaa30),
4318           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4319         { PCI_DEVICE(0x1002, 0xaa38),
4320           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4321         { PCI_DEVICE(0x1002, 0xaa40),
4322           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4323         { PCI_DEVICE(0x1002, 0xaa48),
4324           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4325         { PCI_DEVICE(0x1002, 0x9902),
4326           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4327         { PCI_DEVICE(0x1002, 0xaaa0),
4328           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4329         { PCI_DEVICE(0x1002, 0xaaa8),
4330           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4331         { PCI_DEVICE(0x1002, 0xaab0),
4332           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4333         /* VIA VT8251/VT8237A */
4334         { PCI_DEVICE(0x1106, 0x3288),
4335           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
4336         /* VIA GFX VT7122/VX900 */
4337         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
4338         /* VIA GFX VT6122/VX11 */
4339         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
4340         /* SIS966 */
4341         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
4342         /* ULI M5461 */
4343         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
4344         /* NVIDIA MCP */
4345         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
4346           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4347           .class_mask = 0xffffff,
4348           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
4349         /* Teradici */
4350         { PCI_DEVICE(0x6549, 0x1200),
4351           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4352         { PCI_DEVICE(0x6549, 0x2200),
4353           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4354         /* Creative X-Fi (CA0110-IBG) */
4355         /* CTHDA chips */
4356         { PCI_DEVICE(0x1102, 0x0010),
4357           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4358         { PCI_DEVICE(0x1102, 0x0012),
4359           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4360 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4361         /* the following entry conflicts with snd-ctxfi driver,
4362          * as ctxfi driver mutates from HD-audio to native mode with
4363          * a special command sequence.
4364          */
4365         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4366           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4367           .class_mask = 0xffffff,
4368           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4369           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4370 #else
4371         /* this entry seems still valid -- i.e. without emu20kx chip */
4372         { PCI_DEVICE(0x1102, 0x0009),
4373           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4374           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4375 #endif
4376         /* Vortex86MX */
4377         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
4378         /* VMware HDAudio */
4379         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
4380         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
4381         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4382           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4383           .class_mask = 0xffffff,
4384           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4385         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4386           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4387           .class_mask = 0xffffff,
4388           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4389         { 0, }
4390 };
4391 MODULE_DEVICE_TABLE(pci, azx_pci_ids);
4392
4393 /* pci_driver definition */
4394 static struct pci_driver azx_driver = {
4395         .name = KBUILD_MODNAME,
4396         .id_table = azx_ids,
4397         .probe = azx_probe,
4398         .remove = azx_remove,
4399         .driver = {
4400                 .pm = AZX_PM_OPS,
4401         },
4402 };
4403
4404 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
4405 static int azx_probe_platform(struct platform_device *pdev)
4406 {
4407         const struct platform_device_id *pdev_id = platform_get_device_id(pdev);
4408
4409         return azx_probe(NULL, pdev, pdev_id->driver_data);
4410 }
4411
4412 static int azx_remove_platform(struct platform_device *pdev)
4413 {
4414         return snd_card_free(dev_get_drvdata(&pdev->dev));
4415 }
4416
4417 static const struct platform_device_id azx_platform_ids[] = {
4418 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
4419         { "tegra30-hda",
4420           .driver_data = AZX_DRIVER_NVIDIA_TEGRA | AZX_DCAPS_RIRB_DELAY },
4421 #endif
4422         { },
4423 };
4424 MODULE_DEVICE_TABLE(platform, azx_platform_ids);
4425
4426 /* platform_driver definition */
4427 static struct platform_driver hda_platform_driver = {
4428         .driver = {
4429                 .name = "hda-platform"
4430                 .pm = AZX_PM_OPS,
4431         },
4432         .probe = azx_probe_platform,
4433         .remove = azx_remove_platform,
4434         .id_table = azx_platform_ids,
4435 };
4436 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
4437
4438 module_pci_driver(azx_driver);
4439 module_platform_driver(hda_platform_driver);